2 * COMPILE: arm-none-eabi-gcc -mthumb -march=armv7-m ...
3 * ... plus, provide at least a default exception vector table.
5 * RUN: this is best run from SRAM. It starts at main() then triggers
6 * a fault before more than a handful of instructions have executed.
7 * Run each test case in two modes:
9 * (1) Faults caught on the Cortex-M3. Default handlers are usually
10 * loop-to-self NOPs, so a debugger won't notice faults until they
11 * halt the core and examine xSPR and other registers.
13 * To verify the fault triggered, issue "halt" from OpenOCD; you
14 * should be told about the fault and (some of) its details.
15 * Then it's time to run the next test.
17 * NOTE however that "reset" will restart everything; verify that
18 * case by observing your reset handler doing its normal work.
20 * (2) Faults intercepted by OpenOCD "vector_catch ..." commands.
22 * OpenOCD should tell you about the fault, and show the same
23 * details, without your "halt" command.
25 * Someday, a fancy version of this code could provide a vector table and
26 * fault handlers which use semihosting (when that works on Cortex-M3) to
27 * report what happened, again without needing a "halt" command.
31 /* These symbols match the OpenOCD "cortex_m3 vector_catch" bit names. */
43 /* REVISIT come up with a way to avoid recompiling, maybe:
44 * - write it in RAM before starting
45 * - compiled-in BKPT, manual patch of r0, then resume
50 #warning "no VC_ID ... using reset"
54 int main(void) __attribute__ ((externally_visible
, noreturn
));
57 * Trigger various Cortex-M3 faults to verify that OpenOCD behaves OK
58 * in terms of its vector_catch handling.
60 * Fault handling should be left entirely up to the application code
61 * UNLESS a "vector_catch" command tells OpenOCD to intercept a fault.
63 * See ARMv7-M architecure spec table B1-9 for the list of faults and
64 * their mappings to the vector catch bits.
68 /* One test case for each vector catch bit. We're not doing
69 * hardware testing; so it doesn't matter when some DEMCR bits
70 * could apply in multiple ways.
74 /* "cortex_m3 vector_catch hard_err" */
76 /* FORCED - Fault escalation */
81 /* "cortex_m3 vector_catch int_err" */
83 /* STKERR -- Exception stack BusFault */
88 /* "cortex_m3 vector_catch bus_err" */
90 /* PRECISERR -- precise data bus read
91 * Here we assume a Cortex-M3 with 512 MBytes SRAM is very
92 * unlikely, so the last SRAM byte isn't a valid address.
95 "mov r0, #0x3fffffff\n"
100 /* "cortex_m3 vector_catch state_err" */
102 /* UNDEFINSTR -- architectural undefined instruction */
103 __asm__
volatile(".hword 0xde00");
106 /* "cortex_m3 vector_catch chk_err" */
115 /* "cortex_m3 vector_catch nocp_err" */
117 /* NOCP ... Cortex-M3 has no coprocessors (like CP14 DCC),
118 * but these instructions are allowed by ARMv7-M.
120 __asm__
volatile("mrc p14, 0, r0, c0, c5, 0");
123 /* "cortex_m3 vector_catch mm_err" */
125 /* IACCVIOL -- instruction fetch from an XN region */
127 "mov r0, #0xe0000000\n"
132 /* "cortex_m3 vector_catch reset" */
135 /* r1 = SYSRESETREQ */