| blob | 4a21028c3e47fe5e0fe8af7acfab8792916e4d64 |
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
24 /***************************************************************************
25 * STELLARIS flash is tested on LM3S811, LM3S6965, LM3s3748, more.
26 ***************************************************************************/
27 #ifdef HAVE_CONFIG_H
29 #endif
32 #include <target/algorithm.h>
33 #include <target/armv7m.h>
36 #define DID0_VER(did0) ((did0 >> 28)&0x07)
38 /* STELLARIS control registers */
39 #define SCB_BASE 0x400FE000
40 #define DID0 0x000
41 #define DID1 0x004
42 #define DC0 0x008
43 #define DC1 0x010
44 #define DC2 0x014
45 #define DC3 0x018
46 #define DC4 0x01C
48 #define RIS 0x050
49 #define RCC 0x060
50 #define PLLCFG 0x064
51 #define RCC2 0x070
52 #define NVMSTAT 0x1a0
54 /* "legacy" flash memory protection registers (64KB max) */
55 #define FMPRE 0x130
56 #define FMPPE 0x134
58 /* new flash memory protection registers (for more than 64KB) */
62 #define USECRL 0x140
64 #define FLASH_CONTROL_BASE 0x400FD000
65 #define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
66 #define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
67 #define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
68 #define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
69 #define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
70 #define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
72 #define AMISC 1
73 #define PMISC 2
75 #define AMASK 1
76 #define PMASK 2
78 /* Flash Controller Command bits */
79 #define FMC_WRKEY (0xA442 << 16)
80 #define FMC_COMT (1 << 3)
81 #define FMC_MERASE (1 << 2)
82 #define FMC_ERASE (1 << 1)
83 #define FMC_WRITE (1 << 0)
85 /* STELLARIS constants */
87 /* values to write in FMA to commit write-"once" values */
95 struct stellaris_flash_bank
96 {
97 /* chip id register */
107 /* flash geometry */
112 /* nv memory bits */
115 /* main clock status */
124 };
126 // Autogenerated by contrib/gen-stellaris-part-header.pl
127 // From Stellaris Firmware Development Package revision 8049
132 {
371 };
374 {
381 "Firestorm"
382 };
384 /***************************************************************************
385 * openocd command interface *
386 ***************************************************************************/
388 /* flash_bank stellaris <base> <size> 0 0 <target#>
389 */
391 {
395 {
398 }
406 /* part wasn't probed for info yet */
409 /* TODO Specify the main crystal speed in kHz using an optional
410 * argument; ditto, the speed of an external oscillator used
411 * instead of a crystal. Avoid programming flash using IOSC.
412 */
414 }
417 {
424 /* Read main and master clock freqency register */
428 {
430 }
431 else
432 {
434 }
436 buf_size,
439 device_class,
448 buf_size,
460 buf_size,
461 "master clock: %ikHz%s, "
471 {
473 buf_size,
482 }
484 }
486 /***************************************************************************
487 * chip identification and status *
488 ***************************************************************************/
490 /* Set the flash timimg register to match current clocking */
492 {
499 }
522 /* parts before DustDevil use just 4 bits for xtal spec */
532 };
534 /** Read clock configuration and set stellaris_info->usec_clocks. */
536 {
561 /* NOTE: post-Sandstorm parts have RCC2 which may override
562 * parts of RCC ... with more sysdiv options, option for
563 * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
564 * as zero, so the "use RCC2" flag is always clear.
565 */
571 /* FIXME Tempest parts have an additional lsb for
572 * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
573 */
574 }
579 {
592 /* Sandstorm doesn't have this 30K +/- 30% osc */
597 /* not all parts support hibernation */
604 }
606 /* PLL is used if it's not bypassed; its output is 200 MHz
607 * even when it runs at 400 MHz (adds divide-by-two stage).
608 */
614 else
616 }
618 /* Read device id register, main clock frequency register and fill in driver info structure */
620 {
626 /* Read and parse chip identification register */
636 {
639 }
642 {
645 }
650 {
653 }
655 /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
656 * is 12 MHz, but some older parts have 15 MHz. A few data sheets
657 * even give _both_ numbers! We'll use current numbers; IOSC is
658 * always approximate.
659 *
660 * For Tempest: IOSC is calibrated, 16 MHz
661 */
668 /*
669 * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
670 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
671 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
672 */
676 }
685 /* FALL THROUGH */
691 }
696 }
699 {
702 }
714 /* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
715 * That exposes a 32-word Flash Write Buffer ... enabling
716 * writes of more than one word at a time.
717 */
720 }
722 /***************************************************************************
723 * flash operations *
724 ***************************************************************************/
727 {
739 /* Read each Flash Memory Protection Program Enable (FMPPE) register
740 * to report any pages that we can't write. Ignore the Read Enable
741 * register (FMPRE).
742 */
745 i++) {
764 }
765 }
766 }
768 done:
770 }
773 {
780 {
783 }
789 {
791 }
794 {
796 }
798 /* Refresh flash controller timing */
802 /* Clear and disable flash programming interrupts */
806 /* REVISIT this clobbers state set by any halted firmware ...
807 * it might want to process those IRQs.
808 */
811 {
812 /* Address is first word in page */
814 /* Write erase command */
816 /* Wait until erase complete */
817 do
818 {
820 }
823 /* Check acess violations */
826 {
830 }
833 }
836 }
839 {
847 {
850 }
853 {
857 }
862 /* lockregions are 2 pages ... must protect [even..odd] */
866 {
869 }
871 /* Refresh flash controller timing */
875 /* convert from pages to lockregions */
879 /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
880 * Current parts can be much bigger.
881 */
885 }
892 /* Clear and disable flash programming interrupts */
896 /* REVISIT this clobbers state set by any halted firmware ...
897 * it might want to process those IRQs.
898 */
903 /* Commit FMPPE */
906 /* Write commit command */
907 /* REVISIT safety check, since this cannot be undone
908 * except by the "Recover a locked device" procedure.
909 * REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
910 * inadvisable ... it makes future mass erase operations fail.
911 */
913 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
915 /* Wait until erase complete */
916 do
917 {
919 }
922 /* Check acess violations */
925 {
929 }
932 }
934 /* see contib/loaders/flash/stellaris.s for src */
937 {
938 /*
939 Call with :
940 r0 = buffer address
941 r1 = destination address
942 r2 = bytecount (in) - endaddr (work)
944 Used registers:
945 r3 = pFLASH_CTRL_BASE
946 r4 = FLASHWRITECMD
947 r5 = #1
948 r6 = bytes written
949 r7 = temp reg
950 */
955 /* mainloop: */
960 /* waitloop: */
969 /* pFLASH_CTRL_BASE: */
971 /* FLASHWRITECMD: */
973 };
977 {
987 /* power of two, and multiple of word size */
990 /* for small buffers it's faster not to download an algorithm */
997 /* flash write code */
998 if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
999 {
1002 };
1004 /* plus a buffer big enough for this data */
1008 /* memory buffer */
1010 {
1013 {
1016 }
1019 };
1033 {
1050 {
1053 retval);
1056 }
1061 }
1063 /* REVISIT we could speed up writing multi-section images by
1064 * not freeing the initialized write_algorithm this way.
1065 */
1075 }
1077 static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1078 {
1089 {
1092 }
1101 {
1104 }
1109 /* Refresh flash controller timing */
1113 /* Clear and disable flash programming interrupts */
1117 /* REVISIT this clobbers state set by any halted firmware ...
1118 * it might want to process those IRQs.
1119 */
1121 /* multiple words to be programmed? */
1123 {
1124 /* try using a block write */
1126 words_remaining);
1128 {
1130 {
1132 }
1134 {
1135 /* if an error occured, we examine the reason, and quit */
1140 }
1141 }
1142 else
1143 {
1147 }
1148 }
1151 {
1155 /* Program one word */
1159 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1160 /* Wait until write complete */
1161 do
1162 {
1168 words_remaining--;
1169 }
1172 {
1177 {
1179 bytes_remaining--;
1180 bytes_written++;
1181 }
1186 /* Program one word */
1190 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1191 /* Wait until write complete */
1192 do
1193 {
1196 }
1198 /* Check access violations */
1201 {
1204 }
1206 }
1209 {
1213 /* If this is a stellaris chip, it has flash; probe() is just
1214 * to figure out how much is present. Only do it once.
1215 */
1219 /* stellaris_read_part_info() already handled error checking and
1220 * reporting. Note that it doesn't write, so we don't care about
1221 * whether the target is halted or not.
1222 */
1228 {
1231 }
1233 /* provide this for the benefit of the NOR flash framework */
1238 {
1243 }
1246 }
1249 {
1258 {
1261 }
1266 /* Refresh flash controller timing */
1270 /* Clear and disable flash programming interrupts */
1274 /* REVISIT this clobbers state set by any halted firmware ...
1275 * it might want to process those IRQs.
1276 */
1280 /* Wait until erase complete */
1281 do
1282 {
1284 }
1287 /* if device has > 128k, then second erase cycle is needed
1288 * this is only valid for older devices, but will not hurt */
1290 {
1293 /* Wait until erase complete */
1294 do
1295 {
1297 }
1299 }
1302 }
1305 {
1309 {
1312 }
1320 {
1321 /* set all sectors as erased */
1323 {
1325 }
1328 }
1329 else
1330 {
1332 }
1335 }
1337 /**
1338 * Perform the Stellaris "Recovering a 'Locked' Device procedure.
1339 * This performs a mass erase and then restores all nonvolatile registers
1340 * (including USER_* registers and flash lock bits) to their defaults.
1341 * Accordingly, flash can be reprogrammed, and JTAG can be used.
1342 *
1343 * NOTE that DustDevil parts (at least rev A0 silicon) have errata which
1344 * can affect this operation if flash protection has been enabled.
1345 */
1347 {
1355 /* REVISIT ... it may be worth sanity checking that the AP is
1356 * inactive before we start. ARM documents that switching a DP's
1357 * mode while it's active can cause fault modes that need a power
1358 * cycle to recover.
1359 */
1361 /* assert SRST */
1365 }
1376 }
1378 /* de-assert SRST */
1382 /* wait 400+ msec ... OK, "1+ second" is simpler */
1385 /* USER INTERVENTION required for the power cycle
1386 * Restarting OpenOCD is likely needed because of mode switching.
1387 */
1391 done:
1393 }
1396 {
1402 },
1403 {
1409 },
1410 COMMAND_REGISTRATION_DONE
1411 };
1413 {
1418 },
1419 COMMAND_REGISTRATION_DONE
1420 };
1435 };