tcl/chip/st/spear/spear3xx.tcl

   1 # Generic init scripts for all ST SPEAr3xx family
   2 # http://www.st.com/spear
   3 #
   4 # Date:      2010-09-23
   5 # Author:    Antonio Borneo <borneo.antonio@gmail.com>
   6
   7
   8 # Initialize internal clock
   9 # Default:
  10 # - Crystal =  24 MHz
  11 # - PLL1    = 332 MHz
  12 # - PLL2    = 332 MHz
  13 # - CPU_CLK = 332 MHz
  14 # - DDR_CLK = 332 MHz async
  15 # - HCLK    = 166 MHz
  16 # - PCLK    =  83 MHz
  17 proc sp3xx_clock_default {} {
  18         mww 0xfca00000 0x00000002       # set sysclk slow
  19         mww 0xfca00014 0x0ffffff8       # set pll timeout to minimum (100us ?!?)
  20
  21         # DDRCORE disable to change frequency
  22         set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
  23         mww 0xfca8002c $val
  24         mww 0xfca8002c $val # Yes, write twice!
  25
  26         # programming PLL1
  27         mww 0xfca8000c 0xa600010c       # M=166 P=1 N=12
  28         mww 0xfca80008 0x00001c0a       # power down
  29         mww 0xfca80008 0x00001c0e       # enable
  30         mww 0xfca80008 0x00001c06       # strobe
  31         mww 0xfca80008 0x00001c0e
  32         while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
  33
  34         # programming PLL2
  35         mww 0xfca80018 0xa600010c       # M=166, P=1, N=12
  36         mww 0xfca80014 0x00001c0a       # power down
  37         mww 0xfca80014 0x00001c0e       # enable
  38         mww 0xfca80014 0x00001c06       # strobe
  39         mww 0xfca80014 0x00001c0e
  40         while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
  41
  42         mww 0xfca80028 0x00000082       # enable plltimeen
  43         mww 0xfca80024 0x00000511       # set hclkdiv="/2" & pclkdiv="/2"
  44
  45         mww 0xfca00000 0x00000004       # setting SYSCTL to NORMAL mode
  46         while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
  47
  48         # Select source of DDR clock
  49         #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
  50         mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
  51
  52         # DDRCORE enable after change frequency
  53         mmw 0xfca8002c 0x20000000 0x00000000
  54 }
  55
  56 proc sp3xx_common_init {} {
  57         mww 0xfca8002c 0xfffffff8       # enable clock of all peripherals
  58         mww 0xfca80038 0x00000000       # remove reset of all peripherals
  59
  60         mww 0xfca800e4 0x78000008       # COMP1V8_REG
  61         mww 0xfca800ec 0x78000008       # COMP3V3_REG
  62
  63         mww 0xfca80050 0x00000001       # Enable clk mem port 1
  64
  65         mww 0xfc000000 0x10000f5f       # init SMI and set HW mode
  66         mww 0xfc000000 0x00000f5f
  67
  68         # Initialize Bus Interconnection Matrix
  69         # All ports Round-Robin and lowest priority
  70         mww 0xfca8007c 0x80000007
  71         mww 0xfca80080 0x80000007
  72         mww 0xfca80084 0x80000007
  73         mww 0xfca80088 0x80000007
  74         mww 0xfca8008c 0x80000007
  75         mww 0xfca80090 0x80000007
  76         mww 0xfca80094 0x80000007
  77         mww 0xfca80098 0x80000007
  78         mww 0xfca8009c 0x80000007
  79 }