1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
28 #include "breakpoints.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
35 int mips_m4k_examine_debug_reason(struct target
*target
)
37 uint32_t break_status
;
40 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
41 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
43 /* get info about inst breakpoint support */
44 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
46 if (break_status
& 0x1f)
48 /* we have halted on a breakpoint */
49 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
51 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
54 /* get info about data breakpoint support */
55 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &break_status
)) != ERROR_OK
)
57 if (break_status
& 0x1f)
59 /* we have halted on a breakpoint */
60 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
62 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
69 int mips_m4k_debug_entry(struct target
*target
)
71 struct mips32_common
*mips32
= target_to_mips32(target
);
72 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
75 /* read debug register */
76 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
78 /* make sure break unit configured */
79 mips32_configure_break_unit(target
);
81 /* attempt to find halt reason */
82 mips_m4k_examine_debug_reason(target
);
84 /* clear single step if active */
85 if (debug_reg
& EJTAG_DEBUG_DSS
)
87 /* stopped due to single step - clear step bit */
88 mips_ejtag_config_step(ejtag_info
, 0);
91 mips32_save_context(target
);
93 /* default to mips32 isa, it will be changed below if required */
94 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
96 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
97 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
100 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
101 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
102 target_state_name(target
));
107 int mips_m4k_poll(struct target
*target
)
110 struct mips32_common
*mips32
= target_to_mips32(target
);
111 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
112 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
114 /* read ejtag control reg */
115 jtag_set_end_state(TAP_IDLE
);
116 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
117 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
119 /* clear this bit before handling polling
120 * as after reset registers will read zero */
121 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
123 /* we have detected a reset, clear flag
124 * otherwise ejtag will not work */
125 jtag_set_end_state(TAP_IDLE
);
126 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
128 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
129 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
130 LOG_DEBUG("Reset Detected");
133 /* check for processor halted */
134 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
136 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
138 jtag_set_end_state(TAP_IDLE
);
139 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
141 target
->state
= TARGET_HALTED
;
143 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
146 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
148 else if (target
->state
== TARGET_DEBUG_RUNNING
)
150 target
->state
= TARGET_HALTED
;
152 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
155 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
160 target
->state
= TARGET_RUNNING
;
163 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
168 int mips_m4k_halt(struct target
*target
)
170 struct mips32_common
*mips32
= target_to_mips32(target
);
171 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
173 LOG_DEBUG("target->state: %s",
174 target_state_name(target
));
176 if (target
->state
== TARGET_HALTED
)
178 LOG_DEBUG("target was already halted");
182 if (target
->state
== TARGET_UNKNOWN
)
184 LOG_WARNING("target was in unknown state when halt was requested");
187 if (target
->state
== TARGET_RESET
)
189 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
191 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
192 return ERROR_TARGET_FAILURE
;
196 /* we came here in a reset_halt or reset_init sequence
197 * debug entry was already prepared in mips32_prepare_reset_halt()
199 target
->debug_reason
= DBG_REASON_DBGRQ
;
205 /* break processor */
206 mips_ejtag_enter_debug(ejtag_info
);
208 target
->debug_reason
= DBG_REASON_DBGRQ
;
213 int mips_m4k_assert_reset(struct target
*target
)
215 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
216 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
219 LOG_DEBUG("target->state: %s",
220 target_state_name(target
));
222 enum reset_types jtag_reset_config
= jtag_get_reset_config();
224 if (!(jtag_reset_config
& RESET_HAS_SRST
))
227 if (target
->reset_halt
)
229 /* use hardware to catch reset */
230 jtag_set_end_state(TAP_IDLE
);
231 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
235 jtag_set_end_state(TAP_IDLE
);
236 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
241 /* here we should issue a srst only, but we may have to assert trst as well */
242 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
244 jtag_add_reset(1, 1);
248 jtag_add_reset(0, 1);
253 if (mips_m4k
->is_pic32mx
)
257 LOG_DEBUG("Using MTAP reset to reset processor...");
259 /* use microchip specific MTAP reset */
260 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
, NULL
);
261 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
, NULL
);
263 mchip_cmd
= MCHP_ASERT_RST
;
264 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
265 mchip_cmd
= MCHP_DE_ASSERT_RST
;
266 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
267 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
, NULL
);
271 /* use ejtag reset - not supported by all cores */
272 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
273 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
274 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
275 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
279 target
->state
= TARGET_RESET
;
280 jtag_add_sleep(50000);
282 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
284 if (target
->reset_halt
)
287 if ((retval
= target_halt(target
)) != ERROR_OK
)
294 int mips_m4k_deassert_reset(struct target
*target
)
296 LOG_DEBUG("target->state: %s",
297 target_state_name(target
));
299 /* deassert reset lines */
300 jtag_add_reset(0, 0);
305 int mips_m4k_soft_reset_halt(struct target
*target
)
311 int mips_m4k_single_step_core(struct target
*target
)
313 struct mips32_common
*mips32
= target_to_mips32(target
);
314 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
316 /* configure single step mode */
317 mips_ejtag_config_step(ejtag_info
, 1);
319 /* disable interrupts while stepping */
320 mips32_enable_interrupts(target
, 0);
322 /* exit debug mode */
323 mips_ejtag_exit_debug(ejtag_info
);
325 mips_m4k_debug_entry(target
);
330 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
332 struct mips32_common
*mips32
= target_to_mips32(target
);
333 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
334 struct breakpoint
*breakpoint
= NULL
;
337 if (target
->state
!= TARGET_HALTED
)
339 LOG_WARNING("target not halted");
340 return ERROR_TARGET_NOT_HALTED
;
343 if (!debug_execution
)
345 target_free_all_working_areas(target
);
346 mips_m4k_enable_breakpoints(target
);
347 mips_m4k_enable_watchpoints(target
);
350 /* current = 1: continue on current pc, otherwise continue at <address> */
353 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
354 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
355 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
358 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
359 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
362 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
364 mips32_restore_context(target
);
366 /* the front-end may request us not to handle breakpoints */
367 if (handle_breakpoints
)
369 /* Single step past breakpoint at current address */
370 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
372 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
373 mips_m4k_unset_breakpoint(target
, breakpoint
);
374 mips_m4k_single_step_core(target
);
375 mips_m4k_set_breakpoint(target
, breakpoint
);
379 /* enable interrupts if we are running */
380 mips32_enable_interrupts(target
, !debug_execution
);
382 /* exit debug mode */
383 mips_ejtag_exit_debug(ejtag_info
);
384 target
->debug_reason
= DBG_REASON_NOTHALTED
;
386 /* registers are now invalid */
387 register_cache_invalidate(mips32
->core_cache
);
389 if (!debug_execution
)
391 target
->state
= TARGET_RUNNING
;
392 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
393 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
397 target
->state
= TARGET_DEBUG_RUNNING
;
398 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
399 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
405 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
407 /* get pointers to arch-specific information */
408 struct mips32_common
*mips32
= target_to_mips32(target
);
409 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
410 struct breakpoint
*breakpoint
= NULL
;
412 if (target
->state
!= TARGET_HALTED
)
414 LOG_WARNING("target not halted");
415 return ERROR_TARGET_NOT_HALTED
;
418 /* current = 1: continue on current pc, otherwise continue at <address> */
420 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
422 /* the front-end may request us not to handle breakpoints */
423 if (handle_breakpoints
) {
424 breakpoint
= breakpoint_find(target
,
425 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
427 mips_m4k_unset_breakpoint(target
, breakpoint
);
430 /* restore context */
431 mips32_restore_context(target
);
433 /* configure single step mode */
434 mips_ejtag_config_step(ejtag_info
, 1);
436 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
438 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
440 /* disable interrupts while stepping */
441 mips32_enable_interrupts(target
, 0);
443 /* exit debug mode */
444 mips_ejtag_exit_debug(ejtag_info
);
446 /* registers are now invalid */
447 register_cache_invalidate(mips32
->core_cache
);
450 mips_m4k_set_breakpoint(target
, breakpoint
);
452 LOG_DEBUG("target stepped ");
454 mips_m4k_debug_entry(target
);
455 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
460 void mips_m4k_enable_breakpoints(struct target
*target
)
462 struct breakpoint
*breakpoint
= target
->breakpoints
;
464 /* set any pending breakpoints */
467 if (breakpoint
->set
== 0)
468 mips_m4k_set_breakpoint(target
, breakpoint
);
469 breakpoint
= breakpoint
->next
;
473 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
475 struct mips32_common
*mips32
= target_to_mips32(target
);
476 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
481 LOG_WARNING("breakpoint already set");
485 if (breakpoint
->type
== BKPT_HARD
)
489 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
491 if (bp_num
>= mips32
->num_inst_bpoints
)
493 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
494 breakpoint
->unique_id
);
497 breakpoint
->set
= bp_num
+ 1;
498 comparator_list
[bp_num
].used
= 1;
499 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
500 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
501 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
502 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
503 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
504 breakpoint
->unique_id
,
505 bp_num
, comparator_list
[bp_num
].bp_value
);
507 else if (breakpoint
->type
== BKPT_SOFT
)
509 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
510 if (breakpoint
->length
== 4)
512 uint32_t verify
= 0xffffffff;
514 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
515 breakpoint
->orig_instr
)) != ERROR_OK
)
519 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
524 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
528 if (verify
!= MIPS32_SDBBP
)
530 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
536 uint16_t verify
= 0xffff;
538 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
539 breakpoint
->orig_instr
)) != ERROR_OK
)
543 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
548 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
552 if (verify
!= MIPS16_SDBBP
)
554 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
559 breakpoint
->set
= 20; /* Any nice value but 0 */
565 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
567 /* get pointers to arch-specific information */
568 struct mips32_common
*mips32
= target_to_mips32(target
);
569 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
572 if (!breakpoint
->set
)
574 LOG_WARNING("breakpoint not set");
578 if (breakpoint
->type
== BKPT_HARD
)
580 int bp_num
= breakpoint
->set
- 1;
581 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
583 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
584 breakpoint
->unique_id
);
587 LOG_DEBUG("bpid: %d - releasing hw: %d",
588 breakpoint
->unique_id
,
590 comparator_list
[bp_num
].used
= 0;
591 comparator_list
[bp_num
].bp_value
= 0;
592 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
597 /* restore original instruction (kept in target endianness) */
598 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
599 if (breakpoint
->length
== 4)
601 uint32_t current_instr
;
603 /* check that user program has not modified breakpoint instruction */
604 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
605 (uint8_t*)¤t_instr
)) != ERROR_OK
)
609 if (current_instr
== MIPS32_SDBBP
)
611 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
612 breakpoint
->orig_instr
)) != ERROR_OK
)
620 uint16_t current_instr
;
622 /* check that user program has not modified breakpoint instruction */
623 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
624 (uint8_t*)¤t_instr
)) != ERROR_OK
)
629 if (current_instr
== MIPS16_SDBBP
)
631 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
632 breakpoint
->orig_instr
)) != ERROR_OK
)
644 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
646 struct mips32_common
*mips32
= target_to_mips32(target
);
648 if (breakpoint
->type
== BKPT_HARD
)
650 if (mips32
->num_inst_bpoints_avail
< 1)
652 LOG_INFO("no hardware breakpoint available");
653 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
656 mips32
->num_inst_bpoints_avail
--;
659 mips_m4k_set_breakpoint(target
, breakpoint
);
664 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
666 /* get pointers to arch-specific information */
667 struct mips32_common
*mips32
= target_to_mips32(target
);
669 if (target
->state
!= TARGET_HALTED
)
671 LOG_WARNING("target not halted");
672 return ERROR_TARGET_NOT_HALTED
;
677 mips_m4k_unset_breakpoint(target
, breakpoint
);
680 if (breakpoint
->type
== BKPT_HARD
)
681 mips32
->num_inst_bpoints_avail
++;
686 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
688 struct mips32_common
*mips32
= target_to_mips32(target
);
689 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
692 * watchpoint enabled, ignore all byte lanes in value register
693 * and exclude both load and store accesses from watchpoint
694 * condition evaluation
696 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
697 (0xff << EJTAG_DBCn_BLM_SHIFT
);
701 LOG_WARNING("watchpoint already set");
705 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
707 if (wp_num
>= mips32
->num_data_bpoints
)
709 LOG_ERROR("Can not find free FP Comparator");
713 if (watchpoint
->length
!= 4)
715 LOG_ERROR("Only watchpoints of length 4 are supported");
716 return ERROR_TARGET_UNALIGNED_ACCESS
;
719 if (watchpoint
->address
% 4)
721 LOG_ERROR("Watchpoints address should be word aligned");
722 return ERROR_TARGET_UNALIGNED_ACCESS
;
725 switch (watchpoint
->rw
)
728 enable
&= ~EJTAG_DBCn_NOLB
;
731 enable
&= ~EJTAG_DBCn_NOSB
;
734 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
737 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
740 watchpoint
->set
= wp_num
+ 1;
741 comparator_list
[wp_num
].used
= 1;
742 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
743 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
744 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
745 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
746 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
747 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
748 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
753 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
755 /* get pointers to arch-specific information */
756 struct mips32_common
*mips32
= target_to_mips32(target
);
757 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
759 if (!watchpoint
->set
)
761 LOG_WARNING("watchpoint not set");
765 int wp_num
= watchpoint
->set
- 1;
766 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
768 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
771 comparator_list
[wp_num
].used
= 0;
772 comparator_list
[wp_num
].bp_value
= 0;
773 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
779 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
781 struct mips32_common
*mips32
= target_to_mips32(target
);
783 if (mips32
->num_data_bpoints_avail
< 1)
785 LOG_INFO("no hardware watchpoints available");
786 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
789 mips32
->num_data_bpoints_avail
--;
791 mips_m4k_set_watchpoint(target
, watchpoint
);
795 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
797 /* get pointers to arch-specific information */
798 struct mips32_common
*mips32
= target_to_mips32(target
);
800 if (target
->state
!= TARGET_HALTED
)
802 LOG_WARNING("target not halted");
803 return ERROR_TARGET_NOT_HALTED
;
808 mips_m4k_unset_watchpoint(target
, watchpoint
);
811 mips32
->num_data_bpoints_avail
++;
816 void mips_m4k_enable_watchpoints(struct target
*target
)
818 struct watchpoint
*watchpoint
= target
->watchpoints
;
820 /* set any pending watchpoints */
823 if (watchpoint
->set
== 0)
824 mips_m4k_set_watchpoint(target
, watchpoint
);
825 watchpoint
= watchpoint
->next
;
829 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
831 struct mips32_common
*mips32
= target_to_mips32(target
);
832 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
834 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
836 if (target
->state
!= TARGET_HALTED
)
838 LOG_WARNING("target not halted");
839 return ERROR_TARGET_NOT_HALTED
;
842 /* sanitize arguments */
843 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
844 return ERROR_INVALID_ARGUMENTS
;
846 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
847 return ERROR_TARGET_UNALIGNED_ACCESS
;
849 /* if noDMA off, use DMAACC mode for memory read */
851 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
852 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
854 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
855 if (ERROR_OK
!= retval
)
861 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
,
862 uint32_t count
, uint8_t *buffer
)
864 struct mips32_common
*mips32
= target_to_mips32(target
);
865 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
867 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
868 address
, size
, count
);
870 if (target
->state
!= TARGET_HALTED
)
872 LOG_WARNING("target not halted");
873 return ERROR_TARGET_NOT_HALTED
;
876 /* sanitize arguments */
877 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
878 return ERROR_INVALID_ARGUMENTS
;
880 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
881 return ERROR_TARGET_UNALIGNED_ACCESS
;
883 /* if noDMA off, use DMAACC mode for memory write */
884 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
885 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
887 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
890 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
892 mips32_build_reg_cache(target
);
897 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
,
898 struct jtag_tap
*tap
)
900 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
902 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
904 /* initialize mips4k specific info */
905 mips32_init_arch_info(target
, mips32
, tap
);
906 mips32
->arch_info
= mips_m4k
;
911 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
913 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
915 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
920 int mips_m4k_examine(struct target
*target
)
923 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
924 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
927 if (!target_was_examined(target
))
929 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
930 ejtag_info
->idcode
= idcode
;
932 if (((idcode
>> 1) & 0x7FF) == 0x29)
934 /* we are using a pic32mx so select ejtag port
935 * as it is not selected by default */
936 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
, NULL
);
937 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
938 mips_m4k
->is_pic32mx
= true;
942 /* init rest of ejtag interface */
943 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
946 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
952 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
953 uint32_t count
, uint8_t *buffer
)
955 struct mips32_common
*mips32
= target_to_mips32(target
);
956 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
957 struct working_area
*source
;
961 LOG_DEBUG("address: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, count
);
963 if (target
->state
!= TARGET_HALTED
)
965 LOG_WARNING("target not halted");
966 return ERROR_TARGET_NOT_HALTED
;
969 /* check alignment */
971 return ERROR_TARGET_UNALIGNED_ACCESS
;
973 /* Get memory for block write handler */
974 retval
= target_alloc_working_area(target
, MIPS32_FASTDATA_HANDLER_SIZE
, &source
);
975 if (retval
!= ERROR_OK
)
977 LOG_WARNING("No working area available, falling back to non-bulk write");
978 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
981 /* TAP data register is loaded LSB first (little endian) */
982 if (target
->endianness
== TARGET_BIG_ENDIAN
)
985 for(i
= 0; i
< (count
* 4); i
+= 4)
987 t32
= be_to_h_u32((uint8_t *) &buffer
[i
]);
988 h_u32_to_le(&buffer
[i
], t32
);
992 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, source
, write
, address
,
993 count
, (uint32_t*) buffer
);
994 if (retval
!= ERROR_OK
)
996 /* FASTDATA access failed, try normal memory write */
997 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
998 retval
= mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
1002 target_free_working_area(target
, source
);
1007 struct target_type mips_m4k_target
=
1011 .poll
= mips_m4k_poll
,
1012 .arch_state
= mips32_arch_state
,
1014 .target_request_data
= NULL
,
1016 .halt
= mips_m4k_halt
,
1017 .resume
= mips_m4k_resume
,
1018 .step
= mips_m4k_step
,
1020 .assert_reset
= mips_m4k_assert_reset
,
1021 .deassert_reset
= mips_m4k_deassert_reset
,
1022 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
1024 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1026 .read_memory
= mips_m4k_read_memory
,
1027 .write_memory
= mips_m4k_write_memory
,
1028 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
1029 .checksum_memory
= mips32_checksum_memory
,
1030 .blank_check_memory
= mips32_blank_check_memory
,
1032 .run_algorithm
= mips32_run_algorithm
,
1034 .add_breakpoint
= mips_m4k_add_breakpoint
,
1035 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1036 .add_watchpoint
= mips_m4k_add_watchpoint
,
1037 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1039 .target_create
= mips_m4k_target_create
,
1040 .init_target
= mips_m4k_init_target
,
1041 .examine
= mips_m4k_examine
,