1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
57 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
58 static void cortex_m3_enable_watchpoints(struct target
*target
);
59 static int cortex_m3_store_core_reg_u32(struct target
*target
,
60 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
63 uint32_t *value
, int regnum
)
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
71 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
73 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
75 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
76 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
77 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
79 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
80 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
81 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
83 retval
= swjdp_transaction_endcheck(swjdp
);
85 /* restore DCB_DCRDR - this needs to be in a seperate
86 * transaction otherwise the emulated DCC channel breaks */
87 if (retval
== ERROR_OK
)
88 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
93 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
94 uint32_t value
, int regnum
)
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
102 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
104 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
106 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
107 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
108 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
110 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
111 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
112 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
114 retval
= swjdp_transaction_endcheck(swjdp
);
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
124 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
125 uint32_t mask_on
, uint32_t mask_off
)
127 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
128 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
130 /* mask off status bits */
131 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
132 /* create new register mask */
133 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
135 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
138 static int cortex_m3_clear_halt(struct target
*target
)
140 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
141 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
143 /* clear step if any */
144 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
146 /* Read Debug Fault Status Register */
147 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
149 /* Clear Debug Fault Status */
150 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
151 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
156 static int cortex_m3_single_step_core(struct target
*target
)
158 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
159 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
162 /* backup dhcsr reg */
163 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
165 /* Mask interrupts before clearing halt, if done already. This avoids
166 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
167 * HALT can put the core into an unknown state.
169 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
170 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
171 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
172 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
173 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
176 /* restore dhcsr reg */
177 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
178 cortex_m3_clear_halt(target
);
183 static int cortex_m3_endreset_event(struct target
*target
)
187 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
188 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
189 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
190 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
192 /* FIXME handling of DEMCR clobbers vector_catch config ... */
193 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
194 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
196 /* this register is used for emulated dcc channel */
197 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
199 /* Enable debug requests */
200 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
201 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
202 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
204 /* clear any interrupt masking */
205 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
207 /* Enable trace and DWT; trap hard and bus faults.
209 * REVISIT why trap those two? And why trash the vector_catch
210 * config, instead of preserving it? Catching HARDERR and BUSERR
211 * will interfere with code that handles those itself...
213 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
215 /* Monitor bus faults as such (instead of as generic HARDERR), but
216 * leave memory management and usage faults disabled.
218 * REVISIT setting BUSFAULTENA interferes with code which relies
219 * on the default setting. Why do it?
221 mem_ap_write_u32(swjdp
, NVIC_SHCSR
, SHCSR_BUSFAULTENA
);
223 /* Paranoia: evidently some (early?) chips don't preserve all the
224 * debug state (including FBP, DWT, etc) across reset...
228 target_write_u32(target
, FP_CTRL
, 3);
229 cortex_m3
->fpb_enabled
= 1;
231 /* Restore FPB registers */
232 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
234 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
237 /* Restore DWT registers */
238 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
240 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
242 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
244 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
245 dwt_list
[i
].function
);
247 swjdp_transaction_endcheck(swjdp
);
249 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
251 /* make sure we have latest dhcsr flags */
252 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
257 static int cortex_m3_examine_debug_reason(struct target
*target
)
259 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
261 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
262 /* only check the debug reason if we don't know it already */
264 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
265 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
267 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
269 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
270 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
271 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
273 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
274 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
275 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
276 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
277 else /* EXTERNAL, HALTED */
278 target
->debug_reason
= DBG_REASON_UNDEFINED
;
284 static int cortex_m3_examine_exception_reason(struct target
*target
)
286 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
287 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
288 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
290 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
291 switch (armv7m
->exception_number
)
295 case 3: /* Hard Fault */
296 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
297 if (except_sr
& 0x40000000)
299 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
302 case 4: /* Memory Management */
303 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
304 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
306 case 5: /* Bus Fault */
307 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
308 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
310 case 6: /* Usage Fault */
311 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
313 case 11: /* SVCall */
315 case 12: /* Debug Monitor */
316 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
318 case 14: /* PendSV */
320 case 15: /* SysTick */
326 swjdp_transaction_endcheck(swjdp
);
327 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
"", armv7m_exception_string(armv7m
->exception_number
), \
328 shcsr
, except_sr
, cfsr
, except_ar
);
332 static int cortex_m3_debug_entry(struct target
*target
)
337 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
338 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
339 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
344 cortex_m3_clear_halt(target
);
345 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
347 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
350 /* Examine target state and mode */
351 /* First load register acessible through core debug port*/
352 int num_regs
= armv7m
->core_cache
->num_regs
;
354 for (i
= 0; i
< num_regs
; i
++)
356 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
357 armv7m
->read_core_reg(target
, i
);
360 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
361 xPSR
= buf_get_u32(r
->value
, 0, 32);
363 #ifdef ARMV7_GDB_HACKS
364 /* FIXME this breaks on scan chains with more than one Cortex-M3.
365 * Instead, each CM3 should have its own dummy value...
367 /* copy real xpsr reg for gdb, setting thumb bit */
368 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
369 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
370 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
371 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
374 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
378 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
381 /* Are we in an exception handler */
384 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
385 armv7m
->exception_number
= (xPSR
& 0x1FF);
389 armv7m
->core_mode
= buf_get_u32(armv7m
->core_cache
390 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 1);
391 armv7m
->exception_number
= 0;
394 if (armv7m
->exception_number
)
396 cortex_m3_examine_exception_reason(target
);
399 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
400 armv7m_mode_strings
[armv7m
->core_mode
],
401 *(uint32_t*)(armv7m
->core_cache
->reg_list
[15].value
),
402 target_state_name(target
));
404 if (armv7m
->post_debug_entry
)
405 armv7m
->post_debug_entry(target
);
410 static int cortex_m3_poll(struct target
*target
)
413 enum target_state prev_target_state
= target
->state
;
414 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
415 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
417 /* Read from Debug Halting Control and Status Register */
418 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
419 if (retval
!= ERROR_OK
)
421 target
->state
= TARGET_UNKNOWN
;
425 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
427 /* check if still in reset */
428 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
430 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
432 target
->state
= TARGET_RESET
;
437 if (target
->state
== TARGET_RESET
)
439 /* Cannot switch context while running so endreset is
440 * called with target->state == TARGET_RESET
442 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
443 cortex_m3
->dcb_dhcsr
);
444 cortex_m3_endreset_event(target
);
445 target
->state
= TARGET_RUNNING
;
446 prev_target_state
= TARGET_RUNNING
;
449 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
451 target
->state
= TARGET_HALTED
;
453 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
455 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
458 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
460 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
463 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
466 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
470 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
471 * How best to model low power modes?
474 if (target
->state
== TARGET_UNKNOWN
)
476 /* check if processor is retiring instructions */
477 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
479 target
->state
= TARGET_RUNNING
;
487 static int cortex_m3_halt(struct target
*target
)
489 LOG_DEBUG("target->state: %s",
490 target_state_name(target
));
492 if (target
->state
== TARGET_HALTED
)
494 LOG_DEBUG("target was already halted");
498 if (target
->state
== TARGET_UNKNOWN
)
500 LOG_WARNING("target was in unknown state when halt was requested");
503 if (target
->state
== TARGET_RESET
)
505 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
507 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
508 return ERROR_TARGET_FAILURE
;
512 /* we came here in a reset_halt or reset_init sequence
513 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
515 target
->debug_reason
= DBG_REASON_DBGRQ
;
521 /* Write to Debug Halting Control and Status Register */
522 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
524 target
->debug_reason
= DBG_REASON_DBGRQ
;
529 static int cortex_m3_soft_reset_halt(struct target
*target
)
531 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
532 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
533 uint32_t dcb_dhcsr
= 0;
534 int retval
, timeout
= 0;
536 /* Enter debug state on reset; see end_reset_event() */
537 mem_ap_write_u32(swjdp
, DCB_DEMCR
,
538 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
540 /* Request a core-only reset */
541 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
542 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
543 target
->state
= TARGET_RESET
;
545 /* registers are now invalid */
546 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
548 while (timeout
< 100)
550 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
551 if (retval
== ERROR_OK
)
553 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
554 &cortex_m3
->nvic_dfsr
);
555 if ((dcb_dhcsr
& S_HALT
)
556 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
558 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
560 (unsigned) dcb_dhcsr
,
561 (unsigned) cortex_m3
->nvic_dfsr
);
562 cortex_m3_poll(target
);
563 /* FIXME restore user's vector catch config */
567 LOG_DEBUG("waiting for system reset-halt, "
568 "DHCSR 0x%08x, %d ms",
569 (unsigned) dcb_dhcsr
, timeout
);
578 static void cortex_m3_enable_breakpoints(struct target
*target
)
580 struct breakpoint
*breakpoint
= target
->breakpoints
;
582 /* set any pending breakpoints */
585 if (!breakpoint
->set
)
586 cortex_m3_set_breakpoint(target
, breakpoint
);
587 breakpoint
= breakpoint
->next
;
591 static int cortex_m3_resume(struct target
*target
, int current
,
592 uint32_t address
, int handle_breakpoints
, int debug_execution
)
594 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
595 struct breakpoint
*breakpoint
= NULL
;
599 if (target
->state
!= TARGET_HALTED
)
601 LOG_WARNING("target not halted");
602 return ERROR_TARGET_NOT_HALTED
;
605 if (!debug_execution
)
607 target_free_all_working_areas(target
);
608 cortex_m3_enable_breakpoints(target
);
609 cortex_m3_enable_watchpoints(target
);
614 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
616 /* Disable interrupts */
617 /* We disable interrupts in the PRIMASK register instead of
618 * masking with C_MASKINTS. This is probably the same issue
619 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
620 * in parallel with disabled interrupts can cause local faults
623 * REVISIT this clearly breaks non-debug execution, since the
624 * PRIMASK register state isn't saved/restored... workaround
625 * by never resuming app code after debug execution.
627 buf_set_u32(r
->value
, 0, 1, 1);
631 /* Make sure we are in Thumb mode */
632 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
633 buf_set_u32(r
->value
, 24, 1, 1);
638 /* current = 1: continue on current pc, otherwise continue at <address> */
639 r
= armv7m
->core_cache
->reg_list
+ 15;
642 buf_set_u32(r
->value
, 0, 32, address
);
647 resume_pc
= buf_get_u32(r
->value
, 0, 32);
649 armv7m_restore_context(target
);
651 /* the front-end may request us not to handle breakpoints */
652 if (handle_breakpoints
)
654 /* Single step past breakpoint at current address */
655 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
657 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
659 breakpoint
->unique_id
);
660 cortex_m3_unset_breakpoint(target
, breakpoint
);
661 cortex_m3_single_step_core(target
);
662 cortex_m3_set_breakpoint(target
, breakpoint
);
667 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
669 target
->debug_reason
= DBG_REASON_NOTHALTED
;
671 /* registers are now invalid */
672 register_cache_invalidate(armv7m
->core_cache
);
674 if (!debug_execution
)
676 target
->state
= TARGET_RUNNING
;
677 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
678 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
682 target
->state
= TARGET_DEBUG_RUNNING
;
683 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
684 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
690 /* int irqstepcount = 0; */
691 static int cortex_m3_step(struct target
*target
, int current
,
692 uint32_t address
, int handle_breakpoints
)
694 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
695 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
696 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
697 struct breakpoint
*breakpoint
= NULL
;
698 struct reg
*pc
= armv7m
->core_cache
->reg_list
+ 15;
700 if (target
->state
!= TARGET_HALTED
)
702 LOG_WARNING("target not halted");
703 return ERROR_TARGET_NOT_HALTED
;
706 /* current = 1: continue on current pc, otherwise continue at <address> */
708 buf_set_u32(pc
->value
, 0, 32, address
);
710 /* the front-end may request us not to handle breakpoints */
711 if (handle_breakpoints
) {
712 breakpoint
= breakpoint_find(target
,
713 buf_get_u32(pc
->value
, 0, 32));
715 cortex_m3_unset_breakpoint(target
, breakpoint
);
718 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
720 armv7m_restore_context(target
);
722 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
724 /* set step and clear halt */
725 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
726 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
728 /* registers are now invalid */
729 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
732 cortex_m3_set_breakpoint(target
, breakpoint
);
734 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
735 " nvic_icsr = 0x%" PRIx32
,
736 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
738 cortex_m3_debug_entry(target
);
739 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
741 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
742 " nvic_icsr = 0x%" PRIx32
,
743 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
747 static int cortex_m3_assert_reset(struct target
*target
)
749 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
750 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
753 LOG_DEBUG("target->state: %s",
754 target_state_name(target
));
756 enum reset_types jtag_reset_config
= jtag_get_reset_config();
759 * We can reset Cortex-M3 targets using just the NVIC without
760 * requiring SRST, getting a SoC reset (or a core-only reset)
761 * instead of a system reset.
763 if (!(jtag_reset_config
& RESET_HAS_SRST
))
766 /* Enable debug requests */
767 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
768 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
769 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
771 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
773 if (!target
->reset_halt
)
775 /* Set/Clear C_MASKINTS in a separate operation */
776 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
777 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
778 DBGKEY
| C_DEBUGEN
| C_HALT
);
780 /* clear any debug flags before resuming */
781 cortex_m3_clear_halt(target
);
783 /* clear C_HALT in dhcsr reg */
784 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
786 /* Enter debug state on reset, cf. end_reset_event() */
787 mem_ap_write_u32(swjdp
, DCB_DEMCR
,
788 TRCENA
| VC_HARDERR
| VC_BUSERR
);
792 /* Enter debug state on reset, cf. end_reset_event() */
793 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
794 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
798 * When nRST is asserted on most Stellaris devices, it clears some of
799 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
800 * and OpenOCD depends on those TRMs. So we won't use SRST on those
801 * chips. (Only power-on reset should affect debug state, beyond a
802 * few specified bits; not the chip's nRST input, wired to SRST.)
804 * REVISIT current errata specs don't seem to cover this issue.
805 * Do we have more details than this email?
806 * https://lists.berlios.de/pipermail
807 * /openocd-development/2008-August/003065.html
809 if (strcmp(target
->variant
, "lm3s") == 0)
811 /* Check for silicon revisions with the issue. */
814 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
816 switch ((did0
>> 16) & 0xff)
819 /* all Sandstorm suffer issue */
825 /* Fury and DustDevil rev A have
826 * this nRST problem. It should
827 * be fixed in rev B silicon.
829 if (((did0
>> 8) & 0xff) == 0)
833 /* Tempest should be fine. */
841 /* default to asserting srst */
842 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
844 jtag_add_reset(1, 1);
848 jtag_add_reset(0, 1);
853 /* Use a standard Cortex-M3 software reset mechanism.
854 * SYSRESETREQ will reset SoC peripherals outside the
855 * core, like watchdog timers, if the SoC wires it up
856 * correctly. Else VECRESET can reset just the core.
858 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
859 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
860 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
863 /* I do not know why this is necessary, but it
864 * fixes strange effects (step/resume cause NMI
865 * after reset) on LM3S6918 -- Michael Schwingen
868 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
872 target
->state
= TARGET_RESET
;
873 jtag_add_sleep(50000);
875 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
877 if (target
->reset_halt
)
880 if ((retval
= target_halt(target
)) != ERROR_OK
)
887 static int cortex_m3_deassert_reset(struct target
*target
)
889 LOG_DEBUG("target->state: %s",
890 target_state_name(target
));
892 /* deassert reset lines */
893 jtag_add_reset(0, 0);
899 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
904 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
905 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
909 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
913 if (cortex_m3
->auto_bp_type
)
915 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
918 if (breakpoint
->type
== BKPT_HARD
)
920 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
922 if (fp_num
>= cortex_m3
->fp_num_code
)
924 LOG_ERROR("Can not find free FPB Comparator!");
927 breakpoint
->set
= fp_num
+ 1;
928 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
929 comparator_list
[fp_num
].used
= 1;
930 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
931 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
932 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
933 if (!cortex_m3
->fpb_enabled
)
935 LOG_DEBUG("FPB wasn't enabled, do it now");
936 target_write_u32(target
, FP_CTRL
, 3);
939 else if (breakpoint
->type
== BKPT_SOFT
)
943 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
944 * semihosting; don't use that. Otherwise the BKPT
945 * parameter is arbitrary.
947 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
948 retval
= target_read_memory(target
,
949 breakpoint
->address
& 0xFFFFFFFE,
950 breakpoint
->length
, 1,
951 breakpoint
->orig_instr
);
952 if (retval
!= ERROR_OK
)
954 retval
= target_write_memory(target
,
955 breakpoint
->address
& 0xFFFFFFFE,
956 breakpoint
->length
, 1,
958 if (retval
!= ERROR_OK
)
960 breakpoint
->set
= true;
963 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
964 breakpoint
->unique_id
,
965 (int)(breakpoint
->type
),
974 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
977 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
978 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
980 if (!breakpoint
->set
)
982 LOG_WARNING("breakpoint not set");
986 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
987 breakpoint
->unique_id
,
988 (int)(breakpoint
->type
),
993 if (breakpoint
->type
== BKPT_HARD
)
995 int fp_num
= breakpoint
->set
- 1;
996 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
998 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1001 comparator_list
[fp_num
].used
= 0;
1002 comparator_list
[fp_num
].fpcr_value
= 0;
1003 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1007 /* restore original instruction (kept in target endianness) */
1008 if (breakpoint
->length
== 4)
1010 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1017 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1023 breakpoint
->set
= false;
1029 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1031 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1033 if (cortex_m3
->auto_bp_type
)
1035 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1036 #ifdef ARMV7_GDB_HACKS
1037 if (breakpoint
->length
!= 2) {
1038 /* XXX Hack: Replace all breakpoints with length != 2 with
1039 * a hardware breakpoint. */
1040 breakpoint
->type
= BKPT_HARD
;
1041 breakpoint
->length
= 2;
1046 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
1048 LOG_INFO("flash patch comparator requested outside code memory region");
1049 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1052 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
1054 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1055 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1058 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1060 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1061 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1064 if ((breakpoint
->length
!= 2))
1066 LOG_INFO("only breakpoints of two bytes length supported");
1067 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1070 if (breakpoint
->type
== BKPT_HARD
)
1071 cortex_m3
->fp_code_available
--;
1072 cortex_m3_set_breakpoint(target
, breakpoint
);
1078 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1080 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1082 /* REVISIT why check? FBP can be updated with core running ... */
1083 if (target
->state
!= TARGET_HALTED
)
1085 LOG_WARNING("target not halted");
1086 return ERROR_TARGET_NOT_HALTED
;
1089 if (cortex_m3
->auto_bp_type
)
1091 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1094 if (breakpoint
->set
)
1096 cortex_m3_unset_breakpoint(target
, breakpoint
);
1099 if (breakpoint
->type
== BKPT_HARD
)
1100 cortex_m3
->fp_code_available
++;
1106 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1109 uint32_t mask
, temp
;
1110 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1112 /* watchpoint params were validated earlier */
1114 temp
= watchpoint
->length
;
1121 /* REVISIT Don't fully trust these "not used" records ... users
1122 * may set up breakpoints by hand, e.g. dual-address data value
1123 * watchpoint using comparator #1; comparator #0 matching cycle
1124 * count; send data trace info through ITM and TPIU; etc
1126 struct cortex_m3_dwt_comparator
*comparator
;
1128 for (comparator
= cortex_m3
->dwt_comparator_list
;
1129 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1130 comparator
++, dwt_num
++)
1132 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1134 LOG_ERROR("Can not find free DWT Comparator");
1137 comparator
->used
= 1;
1138 watchpoint
->set
= dwt_num
+ 1;
1140 comparator
->comp
= watchpoint
->address
;
1141 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1144 comparator
->mask
= mask
;
1145 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1148 switch (watchpoint
->rw
) {
1150 comparator
->function
= 5;
1153 comparator
->function
= 6;
1156 comparator
->function
= 7;
1159 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1160 comparator
->function
);
1162 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1163 watchpoint
->unique_id
, dwt_num
,
1164 (unsigned) comparator
->comp
,
1165 (unsigned) comparator
->mask
,
1166 (unsigned) comparator
->function
);
1171 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1173 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1174 struct cortex_m3_dwt_comparator
*comparator
;
1177 if (!watchpoint
->set
)
1179 LOG_WARNING("watchpoint (wpid: %d) not set",
1180 watchpoint
->unique_id
);
1184 dwt_num
= watchpoint
->set
- 1;
1186 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1187 watchpoint
->unique_id
, dwt_num
,
1188 (unsigned) watchpoint
->address
);
1190 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1192 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1196 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1197 comparator
->used
= 0;
1198 comparator
->function
= 0;
1199 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1200 comparator
->function
);
1202 watchpoint
->set
= false;
1208 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1210 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1212 if (cortex_m3
->dwt_comp_available
< 1)
1214 LOG_DEBUG("no comparators?");
1215 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1218 /* hardware doesn't support data value masking */
1219 if (watchpoint
->mask
!= ~(uint32_t)0) {
1220 LOG_DEBUG("watchpoint value masks not supported");
1221 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1224 /* hardware allows address masks of up to 32K */
1227 for (mask
= 0; mask
< 16; mask
++) {
1228 if ((1u << mask
) == watchpoint
->length
)
1232 LOG_DEBUG("unsupported watchpoint length");
1233 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1235 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1236 LOG_DEBUG("watchpoint address is unaligned");
1237 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1240 /* Caller doesn't seem to be able to describe watching for data
1241 * values of zero; that flags "no value".
1243 * REVISIT This DWT may well be able to watch for specific data
1244 * values. Requires comparator #1 to set DATAVMATCH and match
1245 * the data, and another comparator (DATAVADDR0) matching addr.
1247 if (watchpoint
->value
) {
1248 LOG_DEBUG("data value watchpoint not YET supported");
1249 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1252 cortex_m3
->dwt_comp_available
--;
1253 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1259 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1261 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1263 /* REVISIT why check? DWT can be updated with core running ... */
1264 if (target
->state
!= TARGET_HALTED
)
1266 LOG_WARNING("target not halted");
1267 return ERROR_TARGET_NOT_HALTED
;
1270 if (watchpoint
->set
)
1272 cortex_m3_unset_watchpoint(target
, watchpoint
);
1275 cortex_m3
->dwt_comp_available
++;
1276 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1281 static void cortex_m3_enable_watchpoints(struct target
*target
)
1283 struct watchpoint
*watchpoint
= target
->watchpoints
;
1285 /* set any pending watchpoints */
1288 if (!watchpoint
->set
)
1289 cortex_m3_set_watchpoint(target
, watchpoint
);
1290 watchpoint
= watchpoint
->next
;
1294 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1295 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1298 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1299 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1301 /* NOTE: we "know" here that the register identifiers used
1302 * in the v7m header match the Cortex-M3 Debug Core Register
1303 * Selector values for R0..R15, xPSR, MSP, and PSP.
1307 /* read a normal core register */
1308 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1310 if (retval
!= ERROR_OK
)
1312 LOG_ERROR("JTAG failure %i",retval
);
1313 return ERROR_JTAG_DEVICE_ERROR
;
1315 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1318 case ARMV7M_PRIMASK
:
1319 case ARMV7M_BASEPRI
:
1320 case ARMV7M_FAULTMASK
:
1321 case ARMV7M_CONTROL
:
1322 /* Cortex-M3 packages these four registers as bitfields
1323 * in one Debug Core register. So say r0 and r2 docs;
1324 * it was removed from r1 docs, but still works.
1326 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1330 case ARMV7M_PRIMASK
:
1331 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1334 case ARMV7M_BASEPRI
:
1335 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1338 case ARMV7M_FAULTMASK
:
1339 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1342 case ARMV7M_CONTROL
:
1343 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1347 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1351 return ERROR_INVALID_ARGUMENTS
;
1357 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1358 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1362 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1363 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1365 #ifdef ARMV7_GDB_HACKS
1366 /* If the LR register is being modified, make sure it will put us
1367 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1368 * hack to deal with the fact that gdb will sometimes "forge"
1369 * return addresses, and doesn't set the LSB correctly (i.e., when
1370 * printing expressions containing function calls, it sets LR = 0.)
1371 * Valid exception return codes have bit 0 set too.
1373 if (num
== ARMV7M_R14
)
1377 /* NOTE: we "know" here that the register identifiers used
1378 * in the v7m header match the Cortex-M3 Debug Core Register
1379 * Selector values for R0..R15, xPSR, MSP, and PSP.
1383 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1384 if (retval
!= ERROR_OK
)
1388 LOG_ERROR("JTAG failure %i", retval
);
1389 r
= armv7m
->core_cache
->reg_list
+ num
;
1390 r
->dirty
= r
->valid
;
1391 return ERROR_JTAG_DEVICE_ERROR
;
1393 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1396 case ARMV7M_PRIMASK
:
1397 case ARMV7M_BASEPRI
:
1398 case ARMV7M_FAULTMASK
:
1399 case ARMV7M_CONTROL
:
1400 /* Cortex-M3 packages these four registers as bitfields
1401 * in one Debug Core register. So say r0 and r2 docs;
1402 * it was removed from r1 docs, but still works.
1404 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1408 case ARMV7M_PRIMASK
:
1409 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1412 case ARMV7M_BASEPRI
:
1413 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1416 case ARMV7M_FAULTMASK
:
1417 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1420 case ARMV7M_CONTROL
:
1421 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1425 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1427 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1431 return ERROR_INVALID_ARGUMENTS
;
1437 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1438 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1440 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1441 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1442 int retval
= ERROR_INVALID_ARGUMENTS
;
1444 /* cortex_m3 handles unaligned memory access */
1445 if (count
&& buffer
) {
1448 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1451 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1454 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1462 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1463 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1465 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1466 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1467 int retval
= ERROR_INVALID_ARGUMENTS
;
1469 if (count
&& buffer
) {
1472 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1475 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1478 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1486 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1487 uint32_t count
, uint8_t *buffer
)
1489 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1492 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1493 struct target
*target
)
1495 armv7m_build_reg_cache(target
);
1499 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1500 * on r/w if the core is not running, and clear on resume or reset ... or
1501 * at least, in a post_restore_context() method.
1504 struct dwt_reg_state
{
1505 struct target
*target
;
1507 uint32_t value
; /* scratch/cache */
1510 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1512 struct dwt_reg_state
*state
= reg
->arch_info
;
1514 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1517 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1519 struct dwt_reg_state
*state
= reg
->arch_info
;
1521 return target_write_u32(state
->target
, state
->addr
,
1522 buf_get_u32(buf
, 0, reg
->size
));
1531 static struct dwt_reg dwt_base_regs
[] = {
1532 { DWT_CTRL
, "dwt_ctrl", 32, },
1533 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1534 * increments while the core is asleep.
1536 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1537 /* plus some 8 bit counters, useful for profiling with TPIU */
1540 static struct dwt_reg dwt_comp
[] = {
1541 #define DWT_COMPARATOR(i) \
1542 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1543 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1544 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1549 #undef DWT_COMPARATOR
1552 static const struct reg_arch_type dwt_reg_type
= {
1553 .get
= cortex_m3_dwt_get_reg
,
1554 .set
= cortex_m3_dwt_set_reg
,
1558 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1560 struct dwt_reg_state
*state
;
1562 state
= calloc(1, sizeof *state
);
1565 state
->addr
= d
->addr
;
1570 r
->value
= &state
->value
;
1571 r
->arch_info
= state
;
1572 r
->type
= &dwt_reg_type
;
1576 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1579 struct reg_cache
*cache
;
1580 struct cortex_m3_dwt_comparator
*comparator
;
1583 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1585 LOG_DEBUG("no DWT");
1589 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1590 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1591 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1592 sizeof(struct cortex_m3_dwt_comparator
));
1593 if (!cm3
->dwt_comparator_list
) {
1595 cm3
->dwt_num_comp
= 0;
1596 LOG_ERROR("out of mem");
1600 cache
= calloc(1, sizeof *cache
);
1603 free(cm3
->dwt_comparator_list
);
1606 cache
->name
= "cortex-m3 dwt registers";
1607 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1608 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1609 if (!cache
->reg_list
) {
1614 for (reg
= 0; reg
< 2; reg
++)
1615 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1616 dwt_base_regs
+ reg
);
1618 comparator
= cm3
->dwt_comparator_list
;
1619 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1622 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1623 for (j
= 0; j
< 3; j
++, reg
++)
1624 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1625 dwt_comp
+ 3 * i
+ j
);
1628 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1629 cm3
->dwt_cache
= cache
;
1631 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1632 dwtcr
, cm3
->dwt_num_comp
,
1633 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1635 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1636 * implement single-address data value watchpoints ... so we
1637 * won't need to check it later, when asked to set one up.
1641 static int cortex_m3_examine(struct target
*target
)
1644 uint32_t cpuid
, fpcr
;
1646 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1647 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1649 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1652 if (!target_was_examined(target
))
1654 target_set_examined(target
);
1656 /* Read from Device Identification Registers */
1657 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1658 if (retval
!= ERROR_OK
)
1661 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1662 LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
1663 (cpuid
>> 20) & 0xf, (cpuid
>> 0) & 0xf);
1664 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1666 /* NOTE: FPB and DWT are both optional. */
1669 target_read_u32(target
, FP_CTRL
, &fpcr
);
1670 cortex_m3
->auto_bp_type
= 1;
1671 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1672 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1673 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1674 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1675 cortex_m3
->fpb_enabled
= fpcr
& 1;
1676 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1678 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1679 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1681 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1684 cortex_m3_dwt_setup(cortex_m3
, target
);
1686 /* These hardware breakpoints only work for code in flash! */
1687 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1688 target_name(target
),
1689 cortex_m3
->fp_num_code
,
1690 cortex_m3
->dwt_num_comp
);
1696 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1700 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1701 *ctrl
= (uint8_t)dcrdr
;
1702 *value
= (uint8_t)(dcrdr
>> 8);
1704 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1706 /* write ack back to software dcc register
1707 * signify we have read data */
1708 if (dcrdr
& (1 << 0))
1711 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1717 static int cortex_m3_target_request_data(struct target
*target
,
1718 uint32_t size
, uint8_t *buffer
)
1720 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1721 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1726 for (i
= 0; i
< (size
* 4); i
++)
1728 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1735 static int cortex_m3_handle_target_request(void *priv
)
1737 struct target
*target
= priv
;
1738 if (!target_was_examined(target
))
1740 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1741 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1743 if (!target
->dbg_msg_enabled
)
1746 if (target
->state
== TARGET_RUNNING
)
1751 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1753 /* check if we have data */
1754 if (ctrl
& (1 << 0))
1758 /* we assume target is quick enough */
1760 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1761 request
|= (data
<< 8);
1762 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1763 request
|= (data
<< 16);
1764 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1765 request
|= (data
<< 24);
1766 target_request(target
, request
);
1773 static int cortex_m3_init_arch_info(struct target
*target
,
1774 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1777 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1779 armv7m_init_arch_info(target
, armv7m
);
1781 /* prepare JTAG information for the new target */
1782 cortex_m3
->jtag_info
.tap
= tap
;
1783 cortex_m3
->jtag_info
.scann_size
= 4;
1785 armv7m
->swjdp_info
.dp_select_value
= -1;
1786 armv7m
->swjdp_info
.ap_csw_value
= -1;
1787 armv7m
->swjdp_info
.ap_tar_value
= -1;
1788 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1789 armv7m
->swjdp_info
.memaccess_tck
= 8;
1790 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1792 /* register arch-specific functions */
1793 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1795 armv7m
->post_debug_entry
= NULL
;
1797 armv7m
->pre_restore_context
= NULL
;
1798 armv7m
->post_restore_context
= NULL
;
1800 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1801 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1803 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1805 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1813 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1815 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1817 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1818 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1823 /*--------------------------------------------------------------------------*/
1825 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1826 struct cortex_m3_common
*cm3
)
1828 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1829 command_print(cmd_ctx
, "target is not a Cortex-M3");
1830 return ERROR_TARGET_INVALID
;
1836 * Only stuff below this line should need to verify that its target
1837 * is a Cortex-M3. Everything else should have indirected through the
1838 * cortexm3_target structure, which is only used with CM3 targets.
1842 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1843 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1844 * that *only* Thumb2 disassembly matters. There are also some small
1845 * additions to Thumb2 that are specific to ARMv7-M.
1847 COMMAND_HANDLER(handle_cortex_m3_disassemble_command
)
1850 struct target
*target
= get_current_target(CMD_CTX
);
1851 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1853 unsigned long count
= 1;
1854 struct arm_instruction cur_instruction
;
1856 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1857 if (retval
!= ERROR_OK
)
1863 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[1], count
);
1866 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1869 command_print(CMD_CTX
,
1870 "usage: cortex_m3 disassemble <address> [<count>]");
1875 retval
= thumb2_opcode(target
, address
, &cur_instruction
);
1876 if (retval
!= ERROR_OK
)
1878 command_print(CMD_CTX
, "%s", cur_instruction
.text
);
1879 address
+= cur_instruction
.instruction_size
;
1885 static const struct {
1889 { "hard_err", VC_HARDERR
, },
1890 { "int_err", VC_INTERR
, },
1891 { "bus_err", VC_BUSERR
, },
1892 { "state_err", VC_STATERR
, },
1893 { "chk_err", VC_CHKERR
, },
1894 { "nocp_err", VC_NOCPERR
, },
1895 { "mm_err", VC_MMERR
, },
1896 { "reset", VC_CORERESET
, },
1899 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1901 struct target
*target
= get_current_target(CMD_CTX
);
1902 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1903 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1904 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1908 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1909 if (retval
!= ERROR_OK
)
1912 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1917 if (CMD_ARGC
== 1) {
1918 if (strcmp(CMD_ARGV
[0], "all") == 0) {
1919 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1920 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1921 | VC_MMERR
| VC_CORERESET
;
1923 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
1927 while (CMD_ARGC
-- > 0) {
1929 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1930 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
1932 catch |= vec_ids
[i
].mask
;
1935 if (i
== ARRAY_SIZE(vec_ids
)) {
1936 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
1937 return ERROR_INVALID_ARGUMENTS
;
1944 /* write, but don't assume it stuck */
1945 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1946 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1949 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1951 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
1952 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1958 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1960 struct target
*target
= get_current_target(CMD_CTX
);
1961 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1964 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1965 if (retval
!= ERROR_OK
)
1968 if (target
->state
!= TARGET_HALTED
)
1970 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1977 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], enable
);
1978 uint32_t mask_on
= C_HALT
| (enable
? C_MASKINTS
: 0);
1979 uint32_t mask_off
= enable
? 0 : C_MASKINTS
;
1980 cortex_m3_write_debug_halt_mask(target
, mask_on
, mask_off
);
1983 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s",
1984 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
1989 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
1991 .name
= "disassemble",
1992 .handler
= &handle_cortex_m3_disassemble_command
,
1993 .mode
= COMMAND_EXEC
,
1994 .help
= "disassemble Thumb2 instructions",
1995 .usage
= "<address> [<count>]",
1999 .handler
= &handle_cortex_m3_mask_interrupts_command
,
2000 .mode
= COMMAND_EXEC
,
2001 .help
= "mask cortex_m3 interrupts",
2002 .usage
= "['on'|'off']",
2005 .name
= "vector_catch",
2006 .handler
= &handle_cortex_m3_vector_catch_command
,
2007 .mode
= COMMAND_EXEC
,
2008 .help
= "catch hardware vectors",
2009 .usage
= "['all'|'none'|<list>]",
2011 COMMAND_REGISTRATION_DONE
2013 static const struct command_registration cortex_m3_command_handlers
[] = {
2015 .chain
= armv7m_command_handlers
,
2018 .name
= "cortex_m3",
2019 .mode
= COMMAND_EXEC
,
2020 .help
= "Cortex-M3 command group",
2021 .chain
= cortex_m3_exec_command_handlers
,
2023 COMMAND_REGISTRATION_DONE
2026 struct target_type cortexm3_target
=
2028 .name
= "cortex_m3",
2030 .poll
= cortex_m3_poll
,
2031 .arch_state
= armv7m_arch_state
,
2033 .target_request_data
= cortex_m3_target_request_data
,
2035 .halt
= cortex_m3_halt
,
2036 .resume
= cortex_m3_resume
,
2037 .step
= cortex_m3_step
,
2039 .assert_reset
= cortex_m3_assert_reset
,
2040 .deassert_reset
= cortex_m3_deassert_reset
,
2041 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2043 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2045 .read_memory
= cortex_m3_read_memory
,
2046 .write_memory
= cortex_m3_write_memory
,
2047 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2048 .checksum_memory
= armv7m_checksum_memory
,
2049 .blank_check_memory
= armv7m_blank_check_memory
,
2051 .run_algorithm
= armv7m_run_algorithm
,
2053 .add_breakpoint
= cortex_m3_add_breakpoint
,
2054 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2055 .add_watchpoint
= cortex_m3_add_watchpoint
,
2056 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2058 .commands
= cortex_m3_command_handlers
,
2059 .target_create
= cortex_m3_target_create
,
2060 .init_target
= cortex_m3_init_target
,
2061 .examine
= cortex_m3_examine
,