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zy1000: fix optimisation gaffe
[openocd/dnglaze.git] / tcl / target / c100helper.tcl
blob477fe5c2a038d21d83f036058cb506d360f7aefc
1
2 proc helpC100 {} {
3 puts "List of useful functions for C100 processor:"
4 puts "1) reset init: will set up your Telo board"
5 puts "2) setupNOR: will setup NOR access"
6 puts "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
7 puts "4) setupGPIO: will setup GPIOs for Telo board"
8 puts "5) showGPIO: will show current GPIO config registers"
9 puts "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
10 puts "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
11 puts "8) showAmbaClk: will show current config registers for Amba Bus Clock"
12 puts "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
13 puts "10) showArmClk: will show current config registers for Arm Bus Clock"
14 puts "11) setupArmClk: will setup Amba Bus Clock=450MHz"
15 puts "12) ooma_board_detect: will show which version of Telo you have"
16 puts "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
17 puts "14) showDDR2: will show DDR2 config registers"
18 puts "15) showWatchdog: will show current regster config for watchdog"
19 puts "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
20 puts "17) bootNOR: will boot Telo from NOR"
21 puts "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
22 puts "19) putcUART0: will print a character on UART0"
23 puts "20) putsUART0: will print a string on UART0"
24 puts "21) trainDDR2: will run DDR2 training program"
25 puts "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
26 }
27
28 # mrw,mmw from davinci.cfg
29 # mrw: "memory read word", returns value of $reg
30 proc mrw {reg} {
31 set value ""
32 ocd_mem2array value 32 $reg 1
33 return $value(0)
34 }
35
36 # read a 64-bit register (memory mapped)
37 proc mr64bit {reg} {
38 set value ""
39 ocd_mem2array value 32 $reg 2
40 return $value
41 }
42
43
44 # write a 64-bit register (memory mapped)
45 proc mw64bit {reg value} {
46 set high [expr $value >> 32]
47 set low [expr $value & 0xffffffff]
48 #puts [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
49 mww $reg $low
50 mww [expr $reg+4] $high
51 }
52
53 # mmw: "memory modify word", updates value of $reg
54 # $reg <== ((value & ~$clearbits) | $setbits)
55 proc mmw {reg setbits clearbits} {
56 set old [mrw $reg]
57 set new [expr ($old & ~$clearbits) | $setbits]
58 mww $reg $new
59 }
60
61
62 proc showNOR {} {
63 puts "This is the current NOR setup"
64 set EX_CSEN_REG [regs EX_CSEN_REG ]
65 set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
66 set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
67 set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
68 set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
69 set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
70 set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
71 set EX_MFSM_REG [regs EX_MFSM_REG ]
72 set EX_CSFSM_REG [regs EX_CSFSM_REG ]
73 set EX_WRFSM_REG [regs EX_WRFSM_REG ]
74 set EX_RDFSM_REG [regs EX_RDFSM_REG ]
75
76 puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
77 puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
78 puts [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
79 puts [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
80 puts [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
81 puts [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
82 puts [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
83 puts [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
84 puts [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
85 puts [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
86 puts [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
87 }
88
89
90
91 proc showGPIO {} {
92 puts "This is the current GPIO register setup"
93 # GPIO outputs register
94 set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
95 # GPIO Output Enable register
96 set GPIO_OE_REG [regs GPIO_OE_REG]
97 set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
98 set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
99 # GPIO input register
100 set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
101 set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
102 set MUX_CONF_REG [regs MUX_CONF_REG]
103 set SYSCONF_REG [regs SYSCONF_REG]
104 set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
105 set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
106 set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
107 set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
108 set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
109
110 puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
111 puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
112 puts [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
113 puts [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
114 puts [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
115 puts [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
116 puts [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
117 puts [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
118 puts [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
119 puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
120 puts [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
121 puts [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
122 puts [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
123 }
124
125
126
127 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
128 proc showAmbaClk {} {
129 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
130 set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
131 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
132
133 puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
134 ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
135 # see if the PLL is in bypass mode
136 set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
137 puts [format "PLL bypass bit: %d" $bypass]
138 if {$bypass == 1} {
139 puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
140 } else {
141 # nope, extract x,y,w and compute the PLL output freq.
142 set x [expr ($value(0) & 0x0001F0000) >> 16]
143 puts [format "x: %d" $x]
144 set y [expr ($value(0) & 0x00000007F)]
145 puts [format "y: %d" $y]
146 set w [expr ($value(0) & 0x000000300) >> 8]
147 puts [format "w: %d" $w]
148 puts [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
149 }
150 }
151
152
153 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
154 # this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
155 proc setupAmbaClk {} {
156 set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
157 set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
158 set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
159 set ARM_AHB_BYP [regs ARM_AHB_BYP]
160 set PLL_DISABLE [regs PLL_DISABLE]
161 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
162 set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
163 set DIV_BYPASS [regs DIV_BYPASS]
164 set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
165 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
166 set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
167 set w [config w_amba]
168 set x [config x_amba]
169 set y [config y_amba]
170
171 puts [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
172 #puts [format "setupAmbaClk: w= %d" $w]
173 #puts [format "setupAmbaClk: x= %d" $x]
174 #puts [format "setupAmbaClk: y= %d" $y]
175 # set PLL into BYPASS mode using MUX
176 mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
177 # do an internal PLL bypass
178 mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
179 # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
180 # openocd smallest resolution is 1ms so, wait 1ms
181 sleep 1
182 # disable the PLL
183 mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
184 # wait 1ms
185 sleep 1
186 # enable the PLL
187 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
188 sleep 1
189 # set X, W and X
190 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
191 mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
192 # wait for PLL to lock
193 puts "Wating for Amba PLL to lock"
194 while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
195 # remove the internal PLL bypass
196 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
197 # remove PLL from BYPASS mode using MUX
198 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
199 }
200
201
202 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
203 proc showArmClk {} {
204 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
205 set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
206 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
207
208 puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
209 ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
210 # see if the PLL is in bypass mode
211 set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
212 puts [format "PLL bypass bit: %d" $bypass]
213 if {$bypass == 1} {
214 puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
215 } else {
216 # nope, extract x,y,w and compute the PLL output freq.
217 set x [expr ($value(0) & 0x0001F0000) >> 16]
218 puts [format "x: %d" $x]
219 set y [expr ($value(0) & 0x00000007F)]
220 puts [format "y: %d" $y]
221 set w [expr ($value(0) & 0x000000300) >> 8]
222 puts [format "w: %d" $w]
223 puts [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
224 }
225 }
226
227 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
228 # Arm Clock is used by two ARM1136 cores
229 proc setupArmClk {} {
230 set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
231 set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
232 set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
233 set ARM_AHB_BYP [regs ARM_AHB_BYP]
234 set PLL_DISABLE [regs PLL_DISABLE]
235 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
236 set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
237 set DIV_BYPASS [regs DIV_BYPASS]
238 set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
239 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
240 set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
241 set w [config w_arm]
242 set x [config x_arm]
243 set y [config y_arm]
244
245 puts [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
246 #puts [format "setupArmClk: w= %d" $w]
247 #puts [format "setupArmaClk: x= %d" $x]
248 #puts [format "setupArmaClk: y= %d" $y]
249 # set PLL into BYPASS mode using MUX
250 mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
251 # do an internal PLL bypass
252 mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
253 # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
254 # openocd smallest resolution is 1ms so, wait 1ms
255 sleep 1
256 # disable the PLL
257 mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
258 # wait 1ms
259 sleep 1
260 # enable the PLL
261 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
262 sleep 1
263 # set X, W and X
264 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
265 mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
266 # wait for PLL to lock
267 puts "Wating for Amba PLL to lock"
268 while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
269 # remove the internal PLL bypass
270 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
271 # remove PLL from BYPASS mode using MUX
272 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
273 }
274
275
276
277 proc setupPLL {} {
278 puts "PLLs setup"
279 setupAmbaClk
280 setupArmClk
281 }
282
283 # converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
284 proc setupDDR2 {} {
285 puts "Configuring DDR2"
286
287 set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
288 set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
289 set MEMORY_CR [regs MEMORY_CR]
290 set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
291 set DDR_RST [regs DDR_RST]
292
293 # put DDR controller in reset (so that it is reset and correctly configured)
294 # this is only necessary if DDR was previously confiured
295 # and not reset.
296 mmw $BLOCK_RESET_REG 0x0 $DDR_RST
297
298 set M [expr 1024 * 1024]
299 set DDR_SZ_1024M [expr 1024 * $M]
300 set DDR_SZ_256M [expr 256 * $M]
301 set DDR_SZ_128M [expr 128 * $M]
302 set DDR_SZ_64M [expr 64 * $M]
303 # ooma_board_detect returns DDR2 memory size
304 set tmp [ooma_board_detect]
305 if {$tmp == "128M"} {
306 puts "DDR2 size 128MB"
307 set ddr_size $DDR_SZ_128M
308 } elseif {$tmp == "256M"} {
309 puts "DDR2 size 256MB"
310 set ddr_size $DDR_SZ_256M
311 } else {
312 puts "Don't know how to handle this DDR2 size?"
313 }
314
315 # Memory setup register
316 mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
317 # disbale ROM remap
318 mww $MEMORY_CR 0x0
319 # Take DDR controller out of reset
320 mmw $BLOCK_RESET_REG $DDR_RST 0x0
321 # min. 20 ops delay
322 sleep 1
323
324 # This will setup Denali DDR2 controller
325 if {$tmp == "128M"} {
326 configureDDR2regs_128M
327 } elseif {$tmp == "256M"} {
328 configureDDR2regs_256M
329 } else {
330 puts "Don't know how to configure DDR2 setup?"
331 }
332 }
333
334
335
336 proc showDDR2 {} {
337
338 set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
339 set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
340 set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
341 set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
342 set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
343 set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
344 set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
345 set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
346 set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
347 set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
348 set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
349 set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
350 set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
351 set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
352 set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
353 set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
354 set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
355 set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
356 set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
357 set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
358 set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
359
360 set tmp [mr64bit $DENALI_CTL_00_DATA]
361 puts [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
362 set tmp [mr64bit $DENALI_CTL_01_DATA]
363 puts [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
364 set tmp [mr64bit $DENALI_CTL_02_DATA]
365 puts [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
366 set tmp [mr64bit $DENALI_CTL_03_DATA]
367 puts [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
368 set tmp [mr64bit $DENALI_CTL_04_DATA]
369 puts [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
370 set tmp [mr64bit $DENALI_CTL_05_DATA]
371 puts [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
372 set tmp [mr64bit $DENALI_CTL_06_DATA]
373 puts [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
374 set tmp [mr64bit $DENALI_CTL_07_DATA]
375 puts [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
376 set tmp [mr64bit $DENALI_CTL_08_DATA]
377 puts [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
378 set tmp [mr64bit $DENALI_CTL_09_DATA]
379 puts [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
380 set tmp [mr64bit $DENALI_CTL_10_DATA]
381 puts [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
382 set tmp [mr64bit $DENALI_CTL_11_DATA]
383 puts [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
384 set tmp [mr64bit $DENALI_CTL_12_DATA]
385 puts [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
386 set tmp [mr64bit $DENALI_CTL_13_DATA]
387 puts [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
388 set tmp [mr64bit $DENALI_CTL_14_DATA]
389 puts [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
390 set tmp [mr64bit $DENALI_CTL_15_DATA]
391 puts [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
392 set tmp [mr64bit $DENALI_CTL_16_DATA]
393 puts [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
394 set tmp [mr64bit $DENALI_CTL_17_DATA]
395 puts [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
396 set tmp [mr64bit $DENALI_CTL_18_DATA]
397 puts [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
398 set tmp [mr64bit $DENALI_CTL_19_DATA]
399 puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
400 set tmp [mr64bit $DENALI_CTL_20_DATA]
401 puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
402
403 }
404
405 proc initC100 {} {
406 # this follows u-boot/cpu/arm1136/start.S
407 set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
408 set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
409 set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
410 set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
411 set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
412 set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
413 set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
414 set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
415 set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
416 set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
417 set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
418 set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
419 set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
420 set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
421 set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
422
423
424 # unlock writing to IOCTRL register
425 mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
426 # enable address lines A15-A21
427 mmw $GPIO_IOCTRL_REG 0xf 0x0
428 # set ARM into supervisor mode (SVC32)
429 # disable IRQ, FIQ
430 # Do I need this in JTAG mode?
431 # it really should be done as 'and ~0x1f | 0xd3 but
432 # openocd does not support this yet
433 reg cpsr 0xd3
434 # /*
435 # * flush v4 I/D caches
436 # */
437 # mov r0, #0
438 # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
439 arm mcr 15 0 7 7 0 0x0
440 # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
441 arm mcr 15 0 8 7 0 0x0
442
443 # /*
444 # * disable MMU stuff and caches
445 # */
446 # mrc p15, 0, r0, c1, c0, 0
447 arm mrc 15 0 1 0 0
448 # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
449 # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
450 # orr r0, r0, #0x00000002 @ set bit 2 (A) Align
451 # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
452 # orr r0, r0, #0x00400000 @ set bit 22 (U)
453 # mcr p15, 0, r0, c1, c0, 0
454 arm mcr 15 0 1 0 0 0x401002
455 # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
456 # APB init
457 # // Setting APB Bus Wait states to 1, set post write
458 # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
459 mww [expr $APB_ACCESS_WS_REG] 0x40
460 # AHB init
461 # // enable all 6 masters for ARAM
462 mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
463 # // enable all 6 masters for EBUS
464 mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
465
466 # ARAM init
467 # // disable pipeline mode in ARAM
468 # I don't think this is documented anywhere?
469 mww $INTC_ARM1_CONTROL_REG 0x1
470 # configure clocks
471 setupPLL
472 # enable cache
473 # ? (u-boot does nothing here)
474 # DDR2 memory init
475 setupDDR2
476 setupUART0
477 putsUART0 "C100 initialization complete.\n"
478 puts "C100 initialization complete."
479 }
480
481 # show current state of watchdog timer
482 proc showWatchdog {} {
483 set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
484 set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
485 set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
486
487 puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
488 puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
489 puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
490 }
491
492 # converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
493 # this will trigger watchdog reset
494 # the sw. reset does not work on C100
495 # watchdog reset effectively works as hw. reset
496 proc reboot {} {
497 set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
498 set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
499 set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
500
501 # allow the counter to count to high value before triggering
502 # this is because regsiter writes are slow over JTAG and
503 # I don't want to miss the high_bound==curr_count condition
504 mww $TIMER_WDT_HIGH_BOUND 0xffffff
505 mww $TIMER_WDT_CURRENT_COUNT 0x0
506 puts "JTAG speed lowered to 100kHz"
507 adapter_khz 100
508 mww $TIMER_WDT_CONTROL 0x1
509 # wait until the reset
510 puts -nonewline "Wating for watchdog to trigger..."
511 #while {[mrw $TIMER_WDT_CONTROL] == 1} {
512 # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
513 # sleep 1
514 #
515 #}
516 while {[c100.cpu curstate] != "running"} { sleep 1}
517 puts "done."
518 puts [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
519 }
Unoffical Testing Grounds for Dean Glazeski