1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "arm11_dbgtap.h"
30 #include <helper/time_support.h>
33 #define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
35 #define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
39 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
40 behavior of the FTDI driver IIRC was to go via RTI.
42 Conversely there may be other places in this code where the ARM11 code relies
43 on the driver to hit through RTI when coming from Update-?R.
45 static const tap_state_t arm11_move_pi_to_si_via_ci
[] =
47 TAP_IREXIT2
, TAP_IRUPDATE
, TAP_DRSELECT
, TAP_IRSELECT
, TAP_IRCAPTURE
, TAP_IRSHIFT
51 /* REVISIT no error handling here! */
52 static void arm11_add_ir_scan_vc(int num_fields
, struct scan_field
*fields
,
55 if (cmd_queue_cur_state
== TAP_IRPAUSE
)
56 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
58 jtag_add_ir_scan(num_fields
, fields
, state
);
61 static const tap_state_t arm11_move_pd_to_sd_via_cd
[] =
63 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
66 /* REVISIT no error handling here! */
67 void arm11_add_dr_scan_vc(int num_fields
, struct scan_field
*fields
,
70 if (cmd_queue_cur_state
== TAP_DRPAUSE
)
71 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
73 jtag_add_dr_scan(num_fields
, fields
, state
);
77 /** Code de-clutter: Construct struct scan_field to write out a value
79 * \param arm11 Target state variable.
80 * \param num_bits Length of the data field
81 * \param out_data pointer to the data that will be sent out
82 * <em > (data is read when it is added to the JTAG queue)</em>
83 * \param in_data pointer to the memory that will receive data that was clocked in
84 * <em > (data is written when the JTAG queue is executed)</em>
85 * \param field target data structure that will be initialized
87 void arm11_setup_field(struct arm11_common
*arm11
, int num_bits
,
88 void *out_data
, void *in_data
, struct scan_field
*field
)
90 field
->tap
= arm11
->arm
.target
->tap
;
91 field
->num_bits
= num_bits
;
92 field
->out_value
= out_data
;
93 field
->in_value
= in_data
;
96 static const char *arm11_ir_to_string(uint8_t ir
)
98 const char *s
= "unknown";
129 /** Write JTAG instruction register
131 * \param arm11 Target state variable.
132 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
133 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
135 * \remarks This adds to the JTAG command queue but does \em not execute it.
137 void arm11_add_IR(struct arm11_common
* arm11
, uint8_t instr
, tap_state_t state
)
139 struct jtag_tap
*tap
= arm11
->arm
.target
->tap
;
141 if (buf_get_u32(tap
->cur_instr
, 0, 5) == instr
)
143 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
147 JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr
), instr
);
149 struct scan_field field
;
151 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
153 arm11_add_ir_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_IRPAUSE
: state
);
156 /** Verify data shifted out from Scan Chain Register (SCREG). */
157 static void arm11_in_handler_SCAN_N(uint8_t *in_value
)
159 /* Don't expect JTAG layer to modify bits we didn't ask it to read */
160 uint8_t v
= *in_value
& 0x1F;
164 LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v
);
165 jtag_set_error(ERROR_FAIL
);
169 /** Select and write to Scan Chain Register (SCREG)
171 * This function sets the instruction register to SCAN_N and writes
172 * the data register with the selected chain number.
174 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
176 * \param arm11 Target state variable.
177 * \param chain Scan chain that will be selected.
178 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
181 * Changes the current scan chain if needed, transitions to the specified
182 * TAP state, and leaves the IR undefined.
184 * The chain takes effect when Update-DR is passed (usually when subsequently
185 * the INTEXT/EXTEST instructions are written).
187 * \warning (Obsolete) Using this twice in a row will \em fail. The first
188 * call will end in Pause-DR. The second call, due to the IR
189 * caching, will not go through Capture-DR when shifting in the
190 * new scan chain number. As a result the verification in
191 * arm11_in_handler_SCAN_N() must fail.
193 * \remarks This adds to the JTAG command queue but does \em not execute it.
196 int arm11_add_debug_SCAN_N(struct arm11_common
*arm11
,
197 uint8_t chain
, tap_state_t state
)
199 /* Don't needlessly switch the scan chain.
200 * NOTE: the ITRSEL instruction fakes SCREG changing;
201 * but leaves its actual value unchanged.
203 if (arm11
->jtag_info
.cur_scan_chain
== chain
) {
204 JTAG_DEBUG("SCREG <= %d SKIPPED", chain
);
205 return jtag_add_statemove((state
== ARM11_TAP_DEFAULT
)
206 ? TAP_DRPAUSE
: state
);
208 JTAG_DEBUG("SCREG <= %d", chain
);
210 arm11_add_IR(arm11
, ARM11_SCAN_N
, ARM11_TAP_DEFAULT
);
212 struct scan_field field
;
215 arm11_setup_field(arm11
, 5, &chain
, &tmp
, &field
);
217 arm11_add_dr_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_DRPAUSE
: state
);
219 jtag_execute_queue_noclear();
221 arm11_in_handler_SCAN_N(tmp
);
223 arm11
->jtag_info
.cur_scan_chain
= chain
;
225 return jtag_execute_queue();
229 * Queue a DR scan of the ITR register. Caller must have selected
230 * scan chain 4 (ITR), possibly using ITRSEL.
232 * \param arm11 Target state variable.
233 * \param inst An ARM11 processor instruction/opcode.
234 * \param flag Optional parameter to retrieve the Ready flag;
235 * this address will be written when the JTAG chain is scanned.
236 * \param state The TAP state to enter after the DR scan.
238 * Going through the TAP_DRUPDATE state writes ITR only if Ready was
239 * previously set. Only the Ready flag is readable by the scan.
241 * An instruction loaded into ITR is executed when going through the
242 * TAP_IDLE state only if Ready was previously set and the debug state
243 * is properly set up. Depending on the instruction, you may also need
244 * to ensure that the rDTR is ready before that Run-Test/Idle state.
246 static void arm11_add_debug_INST(struct arm11_common
* arm11
,
247 uint32_t inst
, uint8_t * flag
, tap_state_t state
)
249 JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst
);
251 struct scan_field itr
[2];
253 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
254 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
256 arm11_add_dr_scan_vc(ARRAY_SIZE(itr
), itr
, state
);
260 * Read and save the Debug Status and Control Register (DSCR).
262 * \param arm11 Target state variable.
263 * \return Error status; arm11->dscr is updated on success.
265 * \remarks This is a stand-alone function that executes the JTAG
266 * command queue. It does not require the ARM11 debug TAP to be
267 * in any particular state.
269 int arm11_read_DSCR(struct arm11_common
*arm11
)
273 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
274 if (retval
!= ERROR_OK
)
277 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
280 struct scan_field chain1_field
;
282 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
284 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
286 CHECK_RETVAL(jtag_execute_queue());
288 if (arm11
->dscr
!= dscr
)
289 JTAG_DEBUG("DSCR = %08x (OLD %08x)",
291 (unsigned) arm11
->dscr
);
298 /** Write the Debug Status and Control Register (DSCR)
302 * \param arm11 Target state variable.
303 * \param dscr DSCR content
305 * \remarks This is a stand-alone function that executes the JTAG command queue.
307 int arm11_write_DSCR(struct arm11_common
* arm11
, uint32_t dscr
)
310 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
311 if (retval
!= ERROR_OK
)
314 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
316 struct scan_field chain1_field
;
318 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
320 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
322 CHECK_RETVAL(jtag_execute_queue());
324 JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
326 (unsigned) arm11
->dscr
);
333 /** Prepare the stage for ITR/DTR operations
334 * from the arm11_run_instr... group of functions.
336 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
337 * around a block of arm11_run_instr_... calls.
339 * Select scan chain 5 to allow quick access to DTR. When scan
340 * chain 4 is needed to put in a register the ITRSel instruction
341 * shortcut is used instead of actually changing the Scan_N
344 * \param arm11 Target state variable.
347 int arm11_run_instr_data_prepare(struct arm11_common
* arm11
)
349 return arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
352 /** Cleanup after ITR/DTR operations
353 * from the arm11_run_instr... group of functions
355 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
356 * around a block of arm11_run_instr_... calls.
358 * Any IDLE can lead to an instruction execution when
359 * scan chains 4 or 5 are selected and the IR holds
360 * INTEST or EXTEST. So we must disable that before
361 * any following activities lead to an IDLE.
363 * \param arm11 Target state variable.
366 int arm11_run_instr_data_finish(struct arm11_common
* arm11
)
368 return arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
374 * Execute one or more instructions via ITR.
375 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
376 * is set, the ITR Ready flag is set (as seen on the previous entry to
377 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
379 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
381 * \param arm11 Target state variable.
382 * \param opcode Pointer to sequence of ARM opcodes
383 * \param count Number of opcodes to execute
387 int arm11_run_instr_no_data(struct arm11_common
* arm11
,
388 uint32_t * opcode
, size_t count
)
390 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
394 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_IDLE
);
401 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_IDLE
: TAP_DRPAUSE
);
403 CHECK_RETVAL(jtag_execute_queue());
416 if ((timeval_ms()-then
) > 1000)
418 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
430 /** Execute one instruction via ITR
432 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
434 * \param arm11 Target state variable.
435 * \param opcode ARM opcode
438 int arm11_run_instr_no_data1(struct arm11_common
* arm11
, uint32_t opcode
)
440 return arm11_run_instr_no_data(arm11
, &opcode
, 1);
444 /** Execute one instruction via ITR repeatedly while
445 * passing data to the core via DTR on each execution.
447 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
448 * is set, the ITR Ready flag is set (as seen on the previous entry to
449 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
451 * The executed instruction \em must read data from DTR.
453 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
455 * \param arm11 Target state variable.
456 * \param opcode ARM opcode
457 * \param data Pointer to the data words to be passed to the core
458 * \param count Number of data words and instruction repetitions
461 int arm11_run_instr_data_to_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
463 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
465 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
467 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
469 struct scan_field chain5_fields
[3];
475 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
476 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
477 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
486 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
488 CHECK_RETVAL(jtag_execute_queue());
490 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
500 if ((timeval_ms()-then
) > 1000)
502 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
514 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
521 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
523 CHECK_RETVAL(jtag_execute_queue());
525 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
526 (unsigned) Data
, Ready
, nRetry
);
536 if ((timeval_ms()-then
) > 1000)
538 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
550 /** JTAG path for arm11_run_instr_data_to_core_noack
552 * The repeated TAP_IDLE's do not cause a repeated execution
553 * if passed without leaving the state.
555 * Since this is more than 7 bits (adjustable via adding more
556 * TAP_IDLE's) it produces an artificial delay in the lower
557 * layer (FT2232) that is long enough to finish execution on
558 * the core but still shorter than any manually inducible delays.
560 * To disable this code, try "memwrite burst false"
562 * FIX!!! should we use multiple TAP_IDLE here or not???
564 * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
565 * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
567 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
[] =
569 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_IDLE
, TAP_IDLE
, TAP_IDLE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
574 /** Execute one instruction via ITR repeatedly while
575 * passing data to the core via DTR on each execution.
577 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
578 * is set, the ITR Ready flag is set (as seen on the previous entry to
579 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
581 * No Ready check during transmission.
583 * The executed instruction \em must read data from DTR.
585 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
587 * \param arm11 Target state variable.
588 * \param opcode ARM opcode
589 * \param data Pointer to the data words to be passed to the core
590 * \param count Number of data words and instruction repetitions
593 int arm11_run_instr_data_to_core_noack(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
595 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
597 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
599 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
601 struct scan_field chain5_fields
[3];
603 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
604 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
605 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
608 unsigned readiesNum
= count
+ 1;
609 unsigned bytes
= sizeof(*Readies
)*readiesNum
;
611 Readies
= (uint8_t *) malloc(bytes
);
614 LOG_ERROR("Out of memory allocating %u bytes", bytes
);
618 uint8_t * ReadyPos
= Readies
;
622 chain5_fields
[0].out_value
= (void *)(data
++);
623 chain5_fields
[1].in_value
= ReadyPos
++;
627 jtag_add_dr_scan(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_DRPAUSE
));
628 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
),
629 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
);
633 jtag_add_dr_scan(ARRAY_SIZE(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
637 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
639 chain5_fields
[0].out_value
= 0;
640 chain5_fields
[1].in_value
= ReadyPos
++;
642 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
644 int retval
= jtag_execute_queue();
645 if (retval
== ERROR_OK
)
647 unsigned error_count
= 0;
649 for (size_t i
= 0; i
< readiesNum
; i
++)
657 if (error_count
> 0 )
658 LOG_ERROR("%u words out of %u not transferred",
659 error_count
, readiesNum
);
669 /** Execute an instruction via ITR while handing data into the core via DTR.
671 * The executed instruction \em must read data from DTR.
673 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
675 * \param arm11 Target state variable.
676 * \param opcode ARM opcode
677 * \param data Data word to be passed to the core via DTR
680 int arm11_run_instr_data_to_core1(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
682 return arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
686 /** Execute one instruction via ITR repeatedly while
687 * reading data from the core via DTR on each execution.
689 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
690 * is set, the ITR Ready flag is set (as seen on the previous entry to
691 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
693 * The executed instruction \em must write data to DTR.
695 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
697 * \param arm11 Target state variable.
698 * \param opcode ARM opcode
699 * \param data Pointer to an array that receives the data words from the core
700 * \param count Number of data words and instruction repetitions
703 int arm11_run_instr_data_from_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
705 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
707 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_IDLE
);
709 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
711 struct scan_field chain5_fields
[3];
717 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
718 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
719 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
726 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, count
? TAP_IDLE
: TAP_DRPAUSE
);
728 CHECK_RETVAL(jtag_execute_queue());
730 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
731 (unsigned) Data
, Ready
, nRetry
);
741 if ((timeval_ms()-then
) > 1000)
743 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
758 /** Execute one instruction via ITR
759 * then load r0 into DTR and read DTR from core.
761 * The first executed instruction (\p opcode) should write data to r0.
763 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
765 * \param arm11 Target state variable.
766 * \param opcode ARM opcode to write r0 with the value of interest
767 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
770 int arm11_run_instr_data_from_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
)
773 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
774 if (retval
!= ERROR_OK
)
777 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
778 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
783 /** Load data into core via DTR then move it to r0 then
784 * execute one instruction via ITR
786 * The final executed instruction (\p opcode) should read data from r0.
788 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
790 * \param arm11 Target state variable.
791 * \param opcode ARM opcode to read r0 act upon it
792 * \param data Data word that will be written to r0 before \p opcode is executed
795 int arm11_run_instr_data_to_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
798 /* MRC p14,0,r0,c0,c5,0 */
799 retval
= arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
800 if (retval
!= ERROR_OK
)
803 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
804 if (retval
!= ERROR_OK
)
810 /** Apply reads and writes to scan chain 7
812 * \see struct arm11_sc7_action
814 * \param arm11 Target state variable.
815 * \param actions A list of read and/or write instructions
816 * \param count Number of instructions in the list.
819 int arm11_sc7_run(struct arm11_common
* arm11
, struct arm11_sc7_action
* actions
, size_t count
)
823 retval
= arm11_add_debug_SCAN_N(arm11
, 0x07, ARM11_TAP_DEFAULT
);
824 if (retval
!= ERROR_OK
)
827 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
829 struct scan_field chain7_fields
[3];
838 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
839 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
840 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
842 for (size_t i
= 0; i
< count
+ 1; i
++)
846 nRW
= actions
[i
].write
? 1 : 0;
847 DataOut
= actions
[i
].value
;
848 AddressOut
= actions
[i
].address
;
857 /* Timeout here so we don't get stuck. */
861 JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
862 (unsigned) AddressOut
,
864 nRW
? "write" : "read");
866 arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields
),
867 chain7_fields
, TAP_DRPAUSE
);
869 CHECK_RETVAL(jtag_execute_queue());
871 /* 'nRW' is 'Ready' on read out */
883 if ((timeval_ms()-then
) > 1000)
885 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
894 JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn
);
898 if (actions
[i
- 1].address
!= AddressIn
)
900 LOG_WARNING("Scan chain 7 shifted out unexpected address");
903 if (!actions
[i
- 1].write
)
905 actions
[i
- 1].value
= DataIn
;
909 if (actions
[i
- 1].value
!= DataIn
)
911 LOG_WARNING("Scan chain 7 shifted out unexpected data");
919 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
921 * \param arm11 Target state variable.
924 void arm11_sc7_clear_vbw(struct arm11_common
* arm11
)
926 size_t clear_bw_size
= arm11
->brp
+ 1;
927 struct arm11_sc7_action
*clear_bw
= malloc(sizeof(struct arm11_sc7_action
) * clear_bw_size
);
928 struct arm11_sc7_action
* pos
= clear_bw
;
930 for (size_t i
= 0; i
< clear_bw_size
; i
++)
932 clear_bw
[i
].write
= true;
933 clear_bw
[i
].value
= 0;
936 for (size_t i
= 0; i
< arm11
->brp
; i
++)
937 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
939 (pos
++)->address
= ARM11_SC7_VCR
;
941 arm11_sc7_run(arm11
, clear_bw
, clear_bw_size
);
946 /** Write VCR register
948 * \param arm11 Target state variable.
949 * \param value Value to be written
951 void arm11_sc7_set_vcr(struct arm11_common
* arm11
, uint32_t value
)
953 struct arm11_sc7_action set_vcr
;
955 set_vcr
.write
= true;
956 set_vcr
.address
= ARM11_SC7_VCR
;
957 set_vcr
.value
= value
;
959 arm11_sc7_run(arm11
, &set_vcr
, 1);
964 /** Read word from address
966 * \param arm11 Target state variable.
967 * \param address Memory address to be read
968 * \param result Pointer where to store result
971 int arm11_read_memory_word(struct arm11_common
* arm11
, uint32_t address
, uint32_t * result
)
974 retval
= arm11_run_instr_data_prepare(arm11
);
975 if (retval
!= ERROR_OK
)
978 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
979 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
));
981 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
982 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1));
984 return arm11_run_instr_data_finish(arm11
);
988 /************************************************************************/
991 * ARM11 provider for the OpenOCD implementation of the standard
992 * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
995 static inline struct arm11_common
*dpm_to_arm11(struct arm_dpm
*dpm
)
997 return container_of(dpm
, struct arm11_common
, dpm
);
1000 static int arm11_dpm_prepare(struct arm_dpm
*dpm
)
1002 struct arm11_common
*arm11
= dpm_to_arm11(dpm
);
1004 arm11
= container_of(dpm
->arm
, struct arm11_common
, arm
);
1006 return arm11_run_instr_data_prepare(dpm_to_arm11(dpm
));
1009 static int arm11_dpm_finish(struct arm_dpm
*dpm
)
1011 return arm11_run_instr_data_finish(dpm_to_arm11(dpm
));
1014 static int arm11_dpm_instr_write_data_dcc(struct arm_dpm
*dpm
,
1015 uint32_t opcode
, uint32_t data
)
1017 return arm11_run_instr_data_to_core(dpm_to_arm11(dpm
),
1021 static int arm11_dpm_instr_write_data_r0(struct arm_dpm
*dpm
,
1022 uint32_t opcode
, uint32_t data
)
1024 return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm
),
1028 static int arm11_dpm_instr_read_data_dcc(struct arm_dpm
*dpm
,
1029 uint32_t opcode
, uint32_t *data
)
1031 return arm11_run_instr_data_from_core(dpm_to_arm11(dpm
),
1035 static int arm11_dpm_instr_read_data_r0(struct arm_dpm
*dpm
,
1036 uint32_t opcode
, uint32_t *data
)
1038 return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm
),
1042 /* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
1043 * and watchpoint operations instead of running them right away. Since we
1044 * pre-allocated our vector, we don't need to worry about space.
1046 static int arm11_bpwp_enable(struct arm_dpm
*dpm
, unsigned index
,
1047 uint32_t addr
, uint32_t control
)
1049 struct arm11_common
*arm11
= dpm_to_arm11(dpm
);
1050 struct arm11_sc7_action
*action
;
1052 action
= arm11
->bpwp_actions
+ arm11
->bpwp_n
;
1054 /* Invariant: this bp/wp is disabled.
1055 * It also happens that the core is halted here, but for
1056 * DPM-based cores we don't actually care about that.
1059 action
[0].write
= action
[1].write
= true;
1061 action
[0].value
= addr
;
1062 action
[1].value
= control
;
1066 action
[0].address
= ARM11_SC7_BVR0
+ index
;
1067 action
[1].address
= ARM11_SC7_BCR0
+ index
;
1071 action
[0].address
= ARM11_SC7_WVR0
+ index
;
1072 action
[1].address
= ARM11_SC7_WCR0
+ index
;
1083 static int arm11_bpwp_disable(struct arm_dpm
*dpm
, unsigned index
)
1085 struct arm11_common
*arm11
= dpm_to_arm11(dpm
);
1086 struct arm11_sc7_action
*action
;
1088 action
= arm11
->bpwp_actions
+ arm11
->bpwp_n
;
1090 action
[0].write
= true;
1091 action
[0].value
= 0;
1095 action
[0].address
= ARM11_SC7_BCR0
+ index
;
1099 action
[0].address
= ARM11_SC7_WCR0
+ index
;
1110 /** Flush any pending breakpoint and watchpoint updates. */
1111 int arm11_bpwp_flush(struct arm11_common
*arm11
)
1118 retval
= arm11_sc7_run(arm11
, arm11
->bpwp_actions
, arm11
->bpwp_n
);
1124 /** Set up high-level debug module utilities */
1125 int arm11_dpm_init(struct arm11_common
*arm11
, uint32_t didr
)
1127 struct arm_dpm
*dpm
= &arm11
->dpm
;
1130 dpm
->arm
= &arm11
->arm
;
1134 dpm
->prepare
= arm11_dpm_prepare
;
1135 dpm
->finish
= arm11_dpm_finish
;
1137 dpm
->instr_write_data_dcc
= arm11_dpm_instr_write_data_dcc
;
1138 dpm
->instr_write_data_r0
= arm11_dpm_instr_write_data_r0
;
1140 dpm
->instr_read_data_dcc
= arm11_dpm_instr_read_data_dcc
;
1141 dpm
->instr_read_data_r0
= arm11_dpm_instr_read_data_r0
;
1143 dpm
->bpwp_enable
= arm11_bpwp_enable
;
1144 dpm
->bpwp_disable
= arm11_bpwp_disable
;
1146 retval
= arm_dpm_setup(dpm
);
1147 if (retval
!= ERROR_OK
)
1150 /* alloc enough to enable all breakpoints and watchpoints at once */
1151 arm11
->bpwp_actions
= calloc(2 * (dpm
->nbp
+ dpm
->nwp
),
1152 sizeof *arm11
->bpwp_actions
);
1153 if (!arm11
->bpwp_actions
)
1156 retval
= arm_dpm_initialize(dpm
);
1157 if (retval
!= ERROR_OK
)
1160 return arm11_bpwp_flush(arm11
);