src/target/cortex_a8.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifndef CORTEX_A8_H
  30 #define CORTEX_A8_H
  31
  32 #include "armv7a.h"
  33
  34 extern char* cortex_a8_state_strings[];
  35
  36 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
  37
  38 /* See Cortex-A8 TRM section 12.5 */
  39 #define CPUDBG_CPUID    0xD00
  40 #define CPUDBG_CTYPR    0xD04
  41 #define CPUDBG_TTYPR    0xD0C
  42 #define CPUDBG_LOCKACCESS 0xFB0
  43 #define CPUDBG_LOCKSTATUS 0xFB4
  44
  45 #define BRP_NORMAL 0
  46 #define BRP_CONTEXT 1
  47
  48 struct cortex_a8_brp
  49 {
  50         int used;
  51         int type;
  52         uint32_t value;
  53         uint32_t control;
  54         uint8_t BRPn;
  55 };
  56
  57 struct cortex_a8_wrp
  58 {
  59         int used;
  60         int type;
  61         uint32_t value;
  62         uint32_t control;
  63         uint8_t WRPn;
  64 };
  65
  66 struct cortex_a8_common
  67 {
  68         int common_magic;
  69         struct arm_jtag jtag_info;
  70
  71         /* Context information */
  72         uint32_t cpudbg_dscr;
  73         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
  74         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
  75
  76         /* Saved cp15 registers */
  77         uint32_t cp15_control_reg;
  78         uint32_t cp15_aux_control_reg;
  79
  80         /* Breakpoint register pairs */
  81         int brp_num_context;
  82         int brp_num;
  83         int brp_num_available;
  84 //      int brp_enabled;
  85         struct cortex_a8_brp *brp_list;
  86
  87         /* Watchpoint register pairs */
  88         int wrp_num;
  89         int wrp_num_available;
  90         struct cortex_a8_wrp *wrp_list;
  91
  92         /* Interrupts */
  93         int intlinesnum;
  94         uint32_t *intsetenable;
  95
  96         /* Use cortex_a8_read_regs_through_mem for fast register reads */
  97         int fast_reg_read;
  98
  99         struct armv7a_common armv7a_common;
 100 };
 101
 102 static inline struct cortex_a8_common *
 103 target_to_cortex_a8(struct target *target)
 104 {
 105         return container_of(target->arch_info, struct cortex_a8_common,
 106                         armv7a_common.armv4_5_common);
 107 }
 108
 109 #endif /* CORTEX_A8_H */