src/target/armv7a.h

   1 /***************************************************************************
   2  *    Copyright (C) 2009 by David Brownell                                 *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19 #ifndef ARMV7A_H
  20 #define ARMV7A_H
  21
  22 #include "arm_adi_v5.h"
  23 #include "armv4_5.h"
  24 #include "armv4_5_mmu.h"
  25 #include "armv4_5_cache.h"
  26 #include "arm_dpm.h"
  27
  28 enum
  29 {
  30         ARM_PC  = 15,
  31         ARM_CPSR = 16
  32 }
  33 ;
  34
  35 #define ARMV7_COMMON_MAGIC 0x0A450999
  36
  37 /* VA to PA translation operations opc2 values*/
  38 #define V2PCWPR  0
  39 #define V2PCWPW  1
  40 #define V2PCWUR  2
  41 #define V2PCWUW  3
  42 #define V2POWPR  4
  43 #define V2POWPW  5
  44 #define V2POWUR  6
  45 #define V2POWUW  7
  46
  47 struct armv7a_common
  48 {
  49         struct arm armv4_5_common;
  50         int common_magic;
  51         struct reg_cache *core_cache;
  52
  53         /* arm adp debug port */
  54         struct swjdp_common swjdp_info;
  55
  56         /* Core Debug Unit */
  57         struct arm_dpm dpm;
  58         uint32_t debug_base;
  59         uint8_t debug_ap;
  60         uint8_t memory_ap;
  61
  62         /* Cache and Memory Management Unit */
  63         struct armv4_5_mmu_common armv4_5_mmu;
  64
  65         int (*examine_debug_reason)(struct target *target);
  66         void (*post_debug_entry)(struct target *target);
  67
  68         void (*pre_restore_context)(struct target *target);
  69         void (*post_restore_context)(struct target *target);
  70
  71 };
  72
  73 static inline struct armv7a_common *
  74 target_to_armv7a(struct target *target)
  75 {
  76         return container_of(target->arch_info, struct armv7a_common,
  77                         armv4_5_common);
  78 }
  79
  80 /* register offsets from armv7a.debug_base */
  81
  82 /* See ARMv7a arch spec section C10.2 */
  83 #define CPUDBG_DIDR             0x000
  84
  85 /* See ARMv7a arch spec section C10.3 */
  86 #define CPUDBG_WFAR             0x018
  87 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
  88 #define CPUDBG_DSCR             0x088
  89 #define CPUDBG_DRCR             0x090
  90 #define CPUDBG_PRCR             0x310
  91 #define CPUDBG_PRSR             0x314
  92
  93 /* See ARMv7a arch spec section C10.4 */
  94 #define CPUDBG_DTRRX            0x080
  95 #define CPUDBG_ITR              0x084
  96 #define CPUDBG_DTRTX            0x08c
  97
  98 /* See ARMv7a arch spec section C10.5 */
  99 #define CPUDBG_BVR_BASE         0x100
 100 #define CPUDBG_BCR_BASE         0x140
 101 #define CPUDBG_WVR_BASE         0x180
 102 #define CPUDBG_WCR_BASE         0x1C0
 103 #define CPUDBG_VCR              0x01C
 104
 105 /* See ARMv7a arch spec section C10.6 */
 106 #define CPUDBG_OSLAR            0x300
 107 #define CPUDBG_OSLSR            0x304
 108 #define CPUDBG_OSSRR            0x308
 109 #define CPUDBG_ECR              0x024
 110
 111 /* See ARMv7a arch spec section C10.7 */
 112 #define CPUDBG_DSCCR            0x028
 113
 114 /* See ARMv7a arch spec section C10.8 */
 115 #define CPUDBG_AUTHSTATUS       0xFB8
 116
 117 /* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
 118 #define DSCR_CORE_HALTED        0
 119 #define DSCR_CORE_RESTARTED     1
 120 #define DSCR_EXT_INT_EN         13
 121 #define DSCR_HALT_DBG_MODE      14
 122 #define DSCR_MON_DBG_MODE       15
 123 #define DSCR_INSTR_COMP         24
 124 #define DSCR_DTR_TX_FULL        29
 125 #define DSCR_DTR_RX_FULL        30
 126
 127 struct armv7a_algorithm
 128 {
 129         int common_magic;
 130
 131         enum armv4_5_mode core_mode;
 132         enum armv4_5_state core_state;
 133 };
 134
 135 struct armv7a_core_reg
 136 {
 137         int num;
 138         enum armv4_5_mode mode;
 139         struct target *target;
 140         struct armv7a_common *armv7a_common;
 141 };
 142
 143 int armv7a_arch_state(struct target *target);
 144 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 145                 struct armv7a_common *armv7a_common);
 146 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 147
 148 extern const struct command_registration armv7a_command_handlers[];
 149
 150 #endif /* ARMV4_5_H */