src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "register.h"
  30 #include "target.h"
  31 #include "etm.h"
  32
  33 typedef enum armv4_5_mode
  34 {
  35         ARMV4_5_MODE_USR = 16,
  36         ARMV4_5_MODE_FIQ = 17,
  37         ARMV4_5_MODE_IRQ = 18,
  38         ARMV4_5_MODE_SVC = 19,
  39         ARMV4_5_MODE_ABT = 23,
  40         ARMV4_5_MODE_UND = 27,
  41         ARMV4_5_MODE_SYS = 31,
  42         ARMV4_5_MODE_ANY = -1
  43 } armv4_5_mode_t;
  44
  45 extern char** armv4_5_mode_strings;
  46
  47 typedef enum armv4_5_state
  48 {
  49         ARMV4_5_STATE_ARM,
  50         ARMV4_5_STATE_THUMB,
  51         ARMV4_5_STATE_JAZELLE,
  52 } armv4_5_state_t;
  53
  54 extern char* armv4_5_state_strings[];
  55
  56 extern int armv4_5_core_reg_map[7][17];
  57
  58 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  59                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  60 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  61                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  62
  63 /* offsets into armv4_5 core register cache */
  64 enum
  65 {
  66         ARMV4_5_CPSR = 31,
  67         ARMV4_5_SPSR_FIQ = 32,
  68         ARMV4_5_SPSR_IRQ = 33,
  69         ARMV4_5_SPSR_SVC = 34,
  70         ARMV4_5_SPSR_ABT = 35,
  71         ARMV4_5_SPSR_UND = 36
  72 };
  73
  74 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  75
  76 /* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
  77 #define armv4_5_common_s arm
  78
  79 /**
  80  * Represents a generic ARM core, with standard application registers.
  81  *
  82  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  83  * Cortex-M series cores do not support as many core states or shadowed
  84  * registers as traditional ARM cores, and only support Thumb2 instructions.
  85  */
  86 struct arm
  87 {
  88         int common_magic;
  89         struct reg_cache *core_cache;
  90
  91         int /* armv4_5_mode */ core_mode;
  92         enum armv4_5_state core_state;
  93
  94         /** Flag reporting unavailability of the BKPT instruction. */
  95         bool is_armv4;
  96
  97         /** Handle for the Embedded Trace Module, if one is present. */
  98         struct etm_context *etm;
  99
 100         int (*full_context)(struct target *target);
 101         int (*read_core_reg)(struct target *target,
 102                         int num, enum armv4_5_mode mode);
 103         int (*write_core_reg)(struct target *target,
 104                         int num, enum armv4_5_mode mode, uint32_t value);
 105         void *arch_info;
 106 };
 107
 108 #define target_to_armv4_5 target_to_arm
 109
 110 /** Convert target handle to generic ARM target state handle. */
 111 static inline struct arm *target_to_arm(struct target *target)
 112 {
 113         return target->arch_info;
 114 }
 115
 116 static inline bool is_arm(struct arm *arm)
 117 {
 118         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 119 }
 120
 121 struct armv4_5_algorithm
 122 {
 123         int common_magic;
 124
 125         enum armv4_5_mode core_mode;
 126         enum armv4_5_state core_state;
 127 };
 128
 129 struct armv4_5_core_reg
 130 {
 131         int num;
 132         enum armv4_5_mode mode;
 133         struct target *target;
 134         struct arm *armv4_5_common;
 135 };
 136
 137 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 138                 struct arm *armv4_5_common);
 139
 140 /* map psr mode bits to linear number */
 141 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 142 {
 143         switch (mode)
 144         {
 145                 case ARMV4_5_MODE_USR: return 0; break;
 146                 case ARMV4_5_MODE_FIQ: return 1; break;
 147                 case ARMV4_5_MODE_IRQ: return 2; break;
 148                 case ARMV4_5_MODE_SVC: return 3; break;
 149                 case ARMV4_5_MODE_ABT: return 4; break;
 150                 case ARMV4_5_MODE_UND: return 5; break;
 151                 case ARMV4_5_MODE_SYS: return 6; break;
 152                 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
 153                 default:
 154                         LOG_ERROR("invalid mode value encountered %d", mode);
 155                         return -1;
 156         }
 157 }
 158
 159 /* map linear number to mode bits */
 160 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 161 {
 162         switch (number)
 163         {
 164                 case 0: return ARMV4_5_MODE_USR; break;
 165                 case 1: return ARMV4_5_MODE_FIQ; break;
 166                 case 2: return ARMV4_5_MODE_IRQ; break;
 167                 case 3: return ARMV4_5_MODE_SVC; break;
 168                 case 4: return ARMV4_5_MODE_ABT; break;
 169                 case 5: return ARMV4_5_MODE_UND; break;
 170                 case 6: return ARMV4_5_MODE_SYS; break;
 171                 default:
 172                         LOG_ERROR("mode index out of bounds %d", number);
 173                         return ARMV4_5_MODE_ANY;
 174         }
 175 };
 176
 177 int armv4_5_arch_state(struct target *target);
 178 int armv4_5_get_gdb_reg_list(struct target *target,
 179                 struct reg **reg_list[], int *reg_list_size);
 180
 181 int armv4_5_register_commands(struct command_context *cmd_ctx);
 182 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 183
 184 int armv4_5_run_algorithm(struct target *target,
 185                 int num_mem_params, struct mem_param *mem_params,
 186                 int num_reg_params, struct reg_param *reg_params,
 187                 uint32_t entry_point, uint32_t exit_point,
 188                 int timeout_ms, void *arch_info);
 189
 190 int armv4_5_invalidate_core_regs(struct target *target);
 191
 192 int arm_checksum_memory(struct target *target,
 193                 uint32_t address, uint32_t count, uint32_t *checksum);
 194 int arm_blank_check_memory(struct target *target,
 195                 uint32_t address, uint32_t count, uint32_t *blank);
 196
 197
 198 /* ARM mode instructions
 199  */
 200
 201 /* Store multiple increment after
 202  * Rn: base register
 203  * List: for each bit in list: store register
 204  * S: in priviledged mode: store user-mode registers
 205  * W = 1: update the base register. W = 0: leave the base register untouched
 206  */
 207 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 208
 209 /* Load multiple increment after
 210  * Rn: base register
 211  * List: for each bit in list: store register
 212  * S: in priviledged mode: store user-mode registers
 213  * W = 1: update the base register. W = 0: leave the base register untouched
 214  */
 215 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 216
 217 /* MOV r8, r8 */
 218 #define ARMV4_5_NOP                                     (0xe1a08008)
 219
 220 /* Move PSR to general purpose register
 221  * R = 1: SPSR R = 0: CPSR
 222  * Rn: target register
 223  */
 224 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 225
 226 /* Store register
 227  * Rd: register to store
 228  * Rn: base register
 229  */
 230 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 231
 232 /* Load register
 233  * Rd: register to load
 234  * Rn: base register
 235  */
 236 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 237
 238 /* Move general purpose register to PSR
 239  * R = 1: SPSR R = 0: CPSR
 240  * Field: Field mask
 241  * 1: control field 2: extension field 4: status field 8: flags field
 242  * Rm: source register
 243  */
 244 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 245 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 246
 247 /* Load Register Halfword Immediate Post-Index
 248  * Rd: register to load
 249  * Rn: base register
 250  */
 251 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 252
 253 /* Load Register Byte Immediate Post-Index
 254  * Rd: register to load
 255  * Rn: base register
 256  */
 257 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 258
 259 /* Store register Halfword Immediate Post-Index
 260  * Rd: register to store
 261  * Rn: base register
 262  */
 263 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 264
 265 /* Store register Byte Immediate Post-Index
 266  * Rd: register to store
 267  * Rn: base register
 268  */
 269 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 270
 271 /* Branch (and Link)
 272  * Im: Branch target (left-shifted by 2 bits, added to PC)
 273  * L: 1: branch and link 0: branch only
 274  */
 275 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 276
 277 /* Branch and exchange (ARM state)
 278  * Rm: register holding branch target address
 279  */
 280 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 281
 282 /* Move to ARM register from coprocessor
 283  * CP: Coprocessor number
 284  * op1: Coprocessor opcode
 285  * Rd: destination register
 286  * CRn: first coprocessor operand
 287  * CRm: second coprocessor operand
 288  * op2: Second coprocessor opcode
 289  */
 290 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 291
 292 /* Move to coprocessor from ARM register
 293  * CP: Coprocessor number
 294  * op1: Coprocessor opcode
 295  * Rd: destination register
 296  * CRn: first coprocessor operand
 297  * CRm: second coprocessor operand
 298  * op2: Second coprocessor opcode
 299  */
 300 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 301
 302 /* Breakpoint instruction (ARMv5)
 303  * Im: 16-bit immediate
 304  */
 305 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 306
 307
 308 /* Thumb mode instructions
 309  */
 310
 311 /* Store register (Thumb mode)
 312  * Rd: source register
 313  * Rn: base register
 314  */
 315 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 316
 317 /* Load register (Thumb state)
 318  * Rd: destination register
 319  * Rn: base register
 320  */
 321 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 322
 323 /* Load multiple (Thumb state)
 324  * Rn: base register
 325  * List: for each bit in list: store register
 326  */
 327 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 328
 329 /* Load register with PC relative addressing
 330  * Rd: register to load
 331  */
 332 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 333
 334 /* Move hi register (Thumb mode)
 335  * Rd: destination register
 336  * Rm: source register
 337  */
 338 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 339
 340 /* No operation (Thumb mode)
 341  */
 342 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 343
 344 /* Move immediate to register (Thumb state)
 345  * Rd: destination register
 346  * Im: 8-bit immediate value
 347  */
 348 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 349
 350 /* Branch and Exchange
 351  * Rm: register containing branch target
 352  */
 353 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 354
 355 /* Branch (Thumb state)
 356  * Imm: Branch target
 357  */
 358 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 359
 360 /* Breakpoint instruction (ARMv5) (Thumb state)
 361  * Im: 8-bit immediate
 362  */
 363 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 364
 365 /* build basic mrc/mcr opcode */
 366
 367 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 368 {
 369         uint32_t t = 0;
 370         t|=op1<<21;
 371         t|=op2<<5;
 372         t|=CRn<<16;
 373         t|=CRm<<0;
 374         return t;
 375 }
 376
 377 #endif /* ARMV4_5_H */