1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
29 #include <target/arm.h>
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
34 #define CFI_MAX_BUS_WIDTH 4
35 #define CFI_MAX_CHIP_WIDTH 4
37 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
38 #define CFI_MAX_INTEL_CODESIZE 256
40 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
42 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
43 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
46 /* CFI fixups foward declarations */
47 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
48 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
49 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
51 /* fixup after reading cmdset 0002 primary query table */
52 static const struct cfi_fixup cfi_0002_fixups
[] = {
53 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
54 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
55 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
59 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
60 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
61 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
62 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
63 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
67 /* fixup after reading cmdset 0001 primary query table */
68 static const struct cfi_fixup cfi_0001_fixups
[] = {
72 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
74 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
75 const struct cfi_fixup
*f
;
77 for (f
= fixups
; f
->fixup
; f
++)
79 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
80 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
82 f
->fixup(bank
, f
->param
);
87 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
88 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
90 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
92 if (cfi_info
->x16_as_x8
) offset
*= 2;
94 /* while the sector list isn't built, only accesses to sector 0 work */
96 return bank
->base
+ offset
* bank
->bus_width
;
101 LOG_ERROR("BUG: sector list not yet built");
104 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
109 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
113 /* clear whole buffer, to ensure bits that exceed the bus_width
116 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
119 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
121 for (i
= bank
->bus_width
; i
> 0; i
--)
123 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
128 for (i
= 1; i
<= bank
->bus_width
; i
++)
130 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
135 /* read unsigned 8-bit value from the bank
136 * flash banks are expected to be made of similar chips
137 * the query result should be the same for all
139 static uint8_t cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
141 struct target
*target
= bank
->target
;
142 uint8_t data
[CFI_MAX_BUS_WIDTH
];
144 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
146 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
149 return data
[bank
->bus_width
- 1];
152 /* read unsigned 8-bit value from the bank
153 * in case of a bank made of multiple chips,
154 * the individual values are ORed
156 static uint8_t cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
158 struct target
*target
= bank
->target
;
159 uint8_t data
[CFI_MAX_BUS_WIDTH
];
162 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
164 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
166 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
174 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
175 value
|= data
[bank
->bus_width
- 1 - i
];
181 static uint16_t cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
)
183 struct target
*target
= bank
->target
;
184 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
185 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
187 if (cfi_info
->x16_as_x8
)
190 for (i
= 0;i
< 2;i
++)
191 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
192 &data
[i
*bank
->bus_width
]);
195 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
197 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
198 return data
[0] | data
[bank
->bus_width
] << 8;
200 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
203 static uint32_t cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
)
205 struct target
*target
= bank
->target
;
206 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
207 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
209 if (cfi_info
->x16_as_x8
)
212 for (i
= 0;i
< 4;i
++)
213 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
214 &data
[i
*bank
->bus_width
]);
217 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
219 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
220 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
222 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
223 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
226 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
228 struct target
*target
= bank
->target
;
231 if (target
->state
!= TARGET_HALTED
)
233 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
237 cfi_command(bank
, 0x50, command
);
238 target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
241 uint8_t cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
)
245 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
247 LOG_DEBUG("status: 0x%x", status
);
251 /* mask out bit 0 (reserved) */
252 status
= status
& 0xfe;
254 LOG_DEBUG("status: 0x%x", status
);
256 if ((status
& 0x80) != 0x80)
258 LOG_ERROR("timeout while waiting for WSM to become ready");
260 else if (status
!= 0x80)
262 LOG_ERROR("status register: 0x%x", status
);
264 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
266 LOG_ERROR("Program suspended");
268 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
270 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
272 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
274 LOG_ERROR("Block Erase Suspended");
276 cfi_intel_clear_status_register(bank
);
282 int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
284 uint8_t status
, oldstatus
;
285 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
287 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
290 status
= cfi_get_u8(bank
, 0, 0x0);
291 if ((status
^ oldstatus
) & 0x40) {
292 if (status
& cfi_info
->status_poll_mask
& 0x20) {
293 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
294 status
= cfi_get_u8(bank
, 0, 0x0);
295 if ((status
^ oldstatus
) & 0x40) {
296 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
297 return(ERROR_FLASH_OPERATION_FAILED
);
299 LOG_DEBUG("status: 0x%x", status
);
303 } else { /* no toggle: finished, OK */
304 LOG_DEBUG("status: 0x%x", status
);
310 } while (timeout
-- > 0);
312 LOG_ERROR("timeout, status: 0x%x", status
);
314 return(ERROR_FLASH_BUSY
);
317 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
320 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
321 struct cfi_intel_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
322 struct target
*target
= bank
->target
;
325 cfi_info
->pri_ext
= pri_ext
;
327 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
328 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
329 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
331 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
333 cfi_command(bank
, 0xf0, command
);
334 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
338 cfi_command(bank
, 0xff, command
);
339 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
343 LOG_ERROR("Could not read bank flash bank information");
344 return ERROR_FLASH_BANK_INVALID
;
347 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
348 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
350 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
352 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
353 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
354 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
356 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
357 pri_ext
->feature_support
,
358 pri_ext
->suspend_cmd_support
,
359 pri_ext
->blk_status_reg_mask
);
361 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
362 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
364 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
365 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
366 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
368 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
369 if (pri_ext
->num_protection_fields
!= 1)
371 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
374 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
375 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
376 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
378 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
383 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
386 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
387 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
388 struct target
*target
= bank
->target
;
391 cfi_info
->pri_ext
= pri_ext
;
393 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
394 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
395 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
397 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
399 cfi_command(bank
, 0xf0, command
);
400 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
404 LOG_ERROR("Could not read spansion bank information");
405 return ERROR_FLASH_BANK_INVALID
;
408 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
409 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
411 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
413 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
414 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
415 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
416 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
417 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
418 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
419 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
420 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
421 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
422 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
423 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
425 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
426 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
428 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
429 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
431 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
434 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
435 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
436 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
438 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
440 /* default values for implementation specific workarounds */
441 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
442 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
443 pri_ext
->_reversed_geometry
= 0;
448 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
451 struct cfi_atmel_pri_ext atmel_pri_ext
;
452 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
453 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
454 struct target
*target
= bank
->target
;
457 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
458 * but a different primary extended query table.
459 * We read the atmel table, and prepare a valid AMD/Spansion query table.
462 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
464 cfi_info
->pri_ext
= pri_ext
;
466 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
467 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
468 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
470 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
472 cfi_command(bank
, 0xf0, command
);
473 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
477 LOG_ERROR("Could not read atmel bank information");
478 return ERROR_FLASH_BANK_INVALID
;
481 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
482 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
483 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
485 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
486 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
488 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
490 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
491 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
493 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
494 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
495 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
496 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
498 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
499 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
501 if (atmel_pri_ext
.features
& 0x02)
502 pri_ext
->EraseSuspend
= 2;
504 if (atmel_pri_ext
.bottom_boot
)
505 pri_ext
->TopBottom
= 2;
507 pri_ext
->TopBottom
= 3;
509 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
510 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
515 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
517 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
519 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
521 return cfi_read_atmel_pri_ext(bank
);
525 return cfi_read_spansion_pri_ext(bank
);
529 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
532 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
533 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
535 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
539 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
540 pri_ext
->pri
[1], pri_ext
->pri
[2],
541 pri_ext
->major_version
, pri_ext
->minor_version
);
545 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
546 (pri_ext
->SiliconRevision
) >> 2,
547 (pri_ext
->SiliconRevision
) & 0x03);
551 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
552 pri_ext
->EraseSuspend
,
557 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
558 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
559 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
564 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
567 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
568 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
570 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
574 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
578 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
582 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
583 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
584 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
588 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
593 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
595 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
597 struct cfi_flash_bank
*cfi_info
;
601 LOG_WARNING("incomplete flash_bank cfi configuration");
602 return ERROR_FLASH_BANK_INVALID
;
605 uint16_t chip_width
, bus_width
;
606 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[3], bus_width
);
607 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[4], chip_width
);
609 if ((chip_width
> CFI_MAX_CHIP_WIDTH
)
610 || (bus_width
> CFI_MAX_BUS_WIDTH
))
612 LOG_ERROR("chip and bus width have to specified in bytes");
613 return ERROR_FLASH_BANK_INVALID
;
616 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
617 cfi_info
->probed
= 0;
618 bank
->driver_priv
= cfi_info
;
620 cfi_info
->write_algorithm
= NULL
;
622 cfi_info
->x16_as_x8
= 0;
623 cfi_info
->jedec_probe
= 0;
624 cfi_info
->not_cfi
= 0;
626 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
628 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
630 cfi_info
->x16_as_x8
= 1;
632 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
634 cfi_info
->jedec_probe
= 1;
638 cfi_info
->write_algorithm
= NULL
;
640 /* bank wasn't probed yet */
641 cfi_info
->qry
[0] = -1;
646 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
649 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
650 struct target
*target
= bank
->target
;
654 cfi_intel_clear_status_register(bank
);
656 for (i
= first
; i
<= last
; i
++)
658 cfi_command(bank
, 0x20, command
);
659 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
664 cfi_command(bank
, 0xd0, command
);
665 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
670 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
671 bank
->sectors
[i
].is_erased
= 1;
674 cfi_command(bank
, 0xff, command
);
675 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
680 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
681 return ERROR_FLASH_OPERATION_FAILED
;
685 cfi_command(bank
, 0xff, command
);
686 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
690 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
693 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
694 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
695 struct target
*target
= bank
->target
;
699 for (i
= first
; i
<= last
; i
++)
701 cfi_command(bank
, 0xaa, command
);
702 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
707 cfi_command(bank
, 0x55, command
);
708 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
713 cfi_command(bank
, 0x80, command
);
714 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
719 cfi_command(bank
, 0xaa, command
);
720 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
725 cfi_command(bank
, 0x55, command
);
726 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
731 cfi_command(bank
, 0x30, command
);
732 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
737 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
738 bank
->sectors
[i
].is_erased
= 1;
741 cfi_command(bank
, 0xf0, command
);
742 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
747 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
748 return ERROR_FLASH_OPERATION_FAILED
;
752 cfi_command(bank
, 0xf0, command
);
753 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
756 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
758 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
760 if (bank
->target
->state
!= TARGET_HALTED
)
762 LOG_ERROR("Target not halted");
763 return ERROR_TARGET_NOT_HALTED
;
766 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
768 return ERROR_FLASH_SECTOR_INVALID
;
771 if (cfi_info
->qry
[0] != 'Q')
772 return ERROR_FLASH_BANK_NOT_PROBED
;
774 switch (cfi_info
->pri_id
)
778 return cfi_intel_erase(bank
, first
, last
);
781 return cfi_spansion_erase(bank
, first
, last
);
784 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
791 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
794 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
795 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
796 struct target
*target
= bank
->target
;
801 /* if the device supports neither legacy lock/unlock (bit 3) nor
802 * instant individual block locking (bit 5).
804 if (!(pri_ext
->feature_support
& 0x28))
805 return ERROR_FLASH_OPERATION_FAILED
;
807 cfi_intel_clear_status_register(bank
);
809 for (i
= first
; i
<= last
; i
++)
811 cfi_command(bank
, 0x60, command
);
812 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
813 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
819 cfi_command(bank
, 0x01, command
);
820 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
821 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
825 bank
->sectors
[i
].is_protected
= 1;
829 cfi_command(bank
, 0xd0, command
);
830 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
831 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
835 bank
->sectors
[i
].is_protected
= 0;
838 /* instant individual block locking doesn't require reading of the status register */
839 if (!(pri_ext
->feature_support
& 0x20))
841 /* Clear lock bits operation may take up to 1.4s */
842 cfi_intel_wait_status_busy(bank
, 1400);
846 uint8_t block_status
;
847 /* read block lock bit, to verify status */
848 cfi_command(bank
, 0x90, command
);
849 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
853 block_status
= cfi_get_u8(bank
, i
, 0x2);
855 if ((block_status
& 0x1) != set
)
857 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
858 cfi_command(bank
, 0x70, command
);
859 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
863 cfi_intel_wait_status_busy(bank
, 10);
866 return ERROR_FLASH_OPERATION_FAILED
;
876 /* if the device doesn't support individual block lock bits set/clear,
877 * all blocks have been unlocked in parallel, so we set those that should be protected
879 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
881 for (i
= 0; i
< bank
->num_sectors
; i
++)
883 if (bank
->sectors
[i
].is_protected
== 1)
885 cfi_intel_clear_status_register(bank
);
887 cfi_command(bank
, 0x60, command
);
888 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
893 cfi_command(bank
, 0x01, command
);
894 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
899 cfi_intel_wait_status_busy(bank
, 100);
904 cfi_command(bank
, 0xff, command
);
905 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
908 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
910 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
912 if (bank
->target
->state
!= TARGET_HALTED
)
914 LOG_ERROR("Target not halted");
915 return ERROR_TARGET_NOT_HALTED
;
918 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
920 return ERROR_FLASH_SECTOR_INVALID
;
923 if (cfi_info
->qry
[0] != 'Q')
924 return ERROR_FLASH_BANK_NOT_PROBED
;
926 switch (cfi_info
->pri_id
)
930 cfi_intel_protect(bank
, set
, first
, last
);
933 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
940 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
941 static void cfi_add_byte(struct flash_bank
*bank
, uint8_t *word
, uint8_t byte
)
943 /* struct target *target = bank->target; */
948 * The data to flash must not be changed in endian! We write a bytestrem in
949 * target byte order already. Only the control and status byte lane of the flash
950 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
951 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
955 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
959 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
960 word
[i
] = word
[i
+ 1];
961 word
[bank
->bus_width
- 1] = byte
;
967 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
968 word
[i
] = word
[i
- 1];
974 /* Convert code image to target endian */
975 /* FIXME create general block conversion fcts in target.c?) */
976 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
979 for (i
= 0; i
< count
; i
++)
981 target_buffer_set_u32(target
, dest
, *src
);
987 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
989 struct target
*target
= bank
->target
;
991 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
992 cfi_command(bank
, cmd
, buf
);
993 switch (bank
->bus_width
)
999 return target_buffer_get_u16(target
, buf
);
1002 return target_buffer_get_u32(target
, buf
);
1005 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1010 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1012 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1013 struct target
*target
= bank
->target
;
1014 struct reg_param reg_params
[7];
1015 struct arm_algorithm armv4_5_info
;
1016 struct working_area
*source
;
1017 uint32_t buffer_size
= 32768;
1018 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1020 /* algorithm register usage:
1021 * r0: source address (in RAM)
1022 * r1: target address (in Flash)
1024 * r3: flash write command
1025 * r4: status byte (returned to host)
1026 * r5: busy test pattern
1027 * r6: error test pattern
1030 static const uint32_t word_32_code
[] = {
1031 0xe4904004, /* loop: ldr r4, [r0], #4 */
1032 0xe5813000, /* str r3, [r1] */
1033 0xe5814000, /* str r4, [r1] */
1034 0xe5914000, /* busy: ldr r4, [r1] */
1035 0xe0047005, /* and r7, r4, r5 */
1036 0xe1570005, /* cmp r7, r5 */
1037 0x1afffffb, /* bne busy */
1038 0xe1140006, /* tst r4, r6 */
1039 0x1a000003, /* bne done */
1040 0xe2522001, /* subs r2, r2, #1 */
1041 0x0a000001, /* beq done */
1042 0xe2811004, /* add r1, r1 #4 */
1043 0xeafffff2, /* b loop */
1044 0xeafffffe /* done: b -2 */
1047 static const uint32_t word_16_code
[] = {
1048 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1049 0xe1c130b0, /* strh r3, [r1] */
1050 0xe1c140b0, /* strh r4, [r1] */
1051 0xe1d140b0, /* busy ldrh r4, [r1] */
1052 0xe0047005, /* and r7, r4, r5 */
1053 0xe1570005, /* cmp r7, r5 */
1054 0x1afffffb, /* bne busy */
1055 0xe1140006, /* tst r4, r6 */
1056 0x1a000003, /* bne done */
1057 0xe2522001, /* subs r2, r2, #1 */
1058 0x0a000001, /* beq done */
1059 0xe2811002, /* add r1, r1 #2 */
1060 0xeafffff2, /* b loop */
1061 0xeafffffe /* done: b -2 */
1064 static const uint32_t word_8_code
[] = {
1065 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1066 0xe5c13000, /* strb r3, [r1] */
1067 0xe5c14000, /* strb r4, [r1] */
1068 0xe5d14000, /* busy ldrb r4, [r1] */
1069 0xe0047005, /* and r7, r4, r5 */
1070 0xe1570005, /* cmp r7, r5 */
1071 0x1afffffb, /* bne busy */
1072 0xe1140006, /* tst r4, r6 */
1073 0x1a000003, /* bne done */
1074 0xe2522001, /* subs r2, r2, #1 */
1075 0x0a000001, /* beq done */
1076 0xe2811001, /* add r1, r1 #1 */
1077 0xeafffff2, /* b loop */
1078 0xeafffffe /* done: b -2 */
1080 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1081 const uint32_t *target_code_src
;
1082 uint32_t target_code_size
;
1083 int retval
= ERROR_OK
;
1086 cfi_intel_clear_status_register(bank
);
1088 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1089 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1090 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1092 /* If we are setting up the write_algorith, we need target_code_src */
1093 /* if not we only need target_code_size. */
1095 /* However, we don't want to create multiple code paths, so we */
1096 /* do the unecessary evaluation of target_code_src, which the */
1097 /* compiler will probably nicely optimize away if not needed */
1099 /* prepare algorithm code for target endian */
1100 switch (bank
->bus_width
)
1103 target_code_src
= word_8_code
;
1104 target_code_size
= sizeof(word_8_code
);
1107 target_code_src
= word_16_code
;
1108 target_code_size
= sizeof(word_16_code
);
1111 target_code_src
= word_32_code
;
1112 target_code_size
= sizeof(word_32_code
);
1115 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1116 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1119 /* flash write code */
1120 if (!cfi_info
->write_algorithm
)
1122 if (target_code_size
> sizeof(target_code
))
1124 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1125 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1127 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1129 /* Get memory for block write handler */
1130 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1131 if (retval
!= ERROR_OK
)
1133 LOG_WARNING("No working area available, can't do block memory writes");
1134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1137 /* write algorithm code to working area */
1138 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1139 if (retval
!= ERROR_OK
)
1141 LOG_ERROR("Unable to write block write code to target");
1146 /* Get a workspace buffer for the data to flash starting with 32k size.
1147 Half size until buffer would be smaller 256 Bytem then fail back */
1148 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1149 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1152 if (buffer_size
<= 256)
1154 LOG_WARNING("no large enough working area available, can't do block memory writes");
1155 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1160 /* setup algo registers */
1161 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1162 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1163 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1164 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1165 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1166 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1167 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1169 /* prepare command and status register patterns */
1170 write_command_val
= cfi_command_val(bank
, 0x40);
1171 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1172 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1174 LOG_INFO("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1176 /* Programming main loop */
1179 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1182 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1187 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1188 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1189 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1191 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1192 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1193 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1195 LOG_INFO("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1197 /* Execute algorithm, assume breakpoint for last instruction */
1198 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1199 cfi_info
->write_algorithm
->address
,
1200 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1201 10000, /* 10s should be enough for max. 32k of data */
1204 /* On failure try a fall back to direct word writes */
1205 if (retval
!= ERROR_OK
)
1207 cfi_intel_clear_status_register(bank
);
1208 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1209 retval
= ERROR_FLASH_OPERATION_FAILED
;
1210 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1211 /* FIXME To allow fall back or recovery, we must save the actual status
1212 somewhere, so that a higher level code can start recovery. */
1216 /* Check return value from algo code */
1217 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1220 /* read status register (outputs debug inforation) */
1221 cfi_intel_wait_status_busy(bank
, 100);
1222 cfi_intel_clear_status_register(bank
);
1223 retval
= ERROR_FLASH_OPERATION_FAILED
;
1227 buffer
+= thisrun_count
;
1228 address
+= thisrun_count
;
1229 count
-= thisrun_count
;
1232 /* free up resources */
1235 target_free_working_area(target
, source
);
1237 if (cfi_info
->write_algorithm
)
1239 target_free_working_area(target
, cfi_info
->write_algorithm
);
1240 cfi_info
->write_algorithm
= NULL
;
1243 destroy_reg_param(®_params
[0]);
1244 destroy_reg_param(®_params
[1]);
1245 destroy_reg_param(®_params
[2]);
1246 destroy_reg_param(®_params
[3]);
1247 destroy_reg_param(®_params
[4]);
1248 destroy_reg_param(®_params
[5]);
1249 destroy_reg_param(®_params
[6]);
1254 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1256 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1257 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1258 struct target
*target
= bank
->target
;
1259 struct reg_param reg_params
[10];
1260 struct arm_algorithm armv4_5_info
;
1261 struct working_area
*source
;
1262 uint32_t buffer_size
= 32768;
1264 int retval
, retvaltemp
;
1265 int exit_code
= ERROR_OK
;
1267 /* input parameters - */
1268 /* R0 = source address */
1269 /* R1 = destination address */
1270 /* R2 = number of writes */
1271 /* R3 = flash write command */
1272 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1273 /* output parameters - */
1274 /* R5 = 0x80 ok 0x00 bad */
1275 /* temp registers - */
1276 /* R6 = value read from flash to test status */
1277 /* R7 = holding register */
1278 /* unlock registers - */
1279 /* R8 = unlock1_addr */
1280 /* R9 = unlock1_cmd */
1281 /* R10 = unlock2_addr */
1282 /* R11 = unlock2_cmd */
1284 static const uint32_t word_32_code
[] = {
1285 /* 00008100 <sp_32_code>: */
1286 0xe4905004, /* ldr r5, [r0], #4 */
1287 0xe5889000, /* str r9, [r8] */
1288 0xe58ab000, /* str r11, [r10] */
1289 0xe5883000, /* str r3, [r8] */
1290 0xe5815000, /* str r5, [r1] */
1291 0xe1a00000, /* nop */
1293 /* 00008110 <sp_32_busy>: */
1294 0xe5916000, /* ldr r6, [r1] */
1295 0xe0257006, /* eor r7, r5, r6 */
1296 0xe0147007, /* ands r7, r4, r7 */
1297 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1298 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1299 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1300 0xe5916000, /* ldr r6, [r1] */
1301 0xe0257006, /* eor r7, r5, r6 */
1302 0xe0147007, /* ands r7, r4, r7 */
1303 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1304 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1305 0x1a000004, /* bne 8154 <sp_32_done> */
1307 /* 00008140 <sp_32_cont>: */
1308 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1309 0x03a05080, /* moveq r5, #128 ; 0x80 */
1310 0x0a000001, /* beq 8154 <sp_32_done> */
1311 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1312 0xeaffffe8, /* b 8100 <sp_32_code> */
1314 /* 00008154 <sp_32_done>: */
1315 0xeafffffe /* b 8154 <sp_32_done> */
1318 static const uint32_t word_16_code
[] = {
1319 /* 00008158 <sp_16_code>: */
1320 0xe0d050b2, /* ldrh r5, [r0], #2 */
1321 0xe1c890b0, /* strh r9, [r8] */
1322 0xe1cab0b0, /* strh r11, [r10] */
1323 0xe1c830b0, /* strh r3, [r8] */
1324 0xe1c150b0, /* strh r5, [r1] */
1325 0xe1a00000, /* nop (mov r0,r0) */
1327 /* 00008168 <sp_16_busy>: */
1328 0xe1d160b0, /* ldrh r6, [r1] */
1329 0xe0257006, /* eor r7, r5, r6 */
1330 0xe0147007, /* ands r7, r4, r7 */
1331 0x0a000007, /* beq 8198 <sp_16_cont> */
1332 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1333 0x0afffff9, /* beq 8168 <sp_16_busy> */
1334 0xe1d160b0, /* ldrh r6, [r1] */
1335 0xe0257006, /* eor r7, r5, r6 */
1336 0xe0147007, /* ands r7, r4, r7 */
1337 0x0a000001, /* beq 8198 <sp_16_cont> */
1338 0xe3a05000, /* mov r5, #0 ; 0x0 */
1339 0x1a000004, /* bne 81ac <sp_16_done> */
1341 /* 00008198 <sp_16_cont>: */
1342 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1343 0x03a05080, /* moveq r5, #128 ; 0x80 */
1344 0x0a000001, /* beq 81ac <sp_16_done> */
1345 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1346 0xeaffffe8, /* b 8158 <sp_16_code> */
1348 /* 000081ac <sp_16_done>: */
1349 0xeafffffe /* b 81ac <sp_16_done> */
1352 static const uint32_t word_16_code_dq7only
[] = {
1354 0xe0d050b2, /* ldrh r5, [r0], #2 */
1355 0xe1c890b0, /* strh r9, [r8] */
1356 0xe1cab0b0, /* strh r11, [r10] */
1357 0xe1c830b0, /* strh r3, [r8] */
1358 0xe1c150b0, /* strh r5, [r1] */
1359 0xe1a00000, /* nop (mov r0,r0) */
1362 0xe1d160b0, /* ldrh r6, [r1] */
1363 0xe0257006, /* eor r7, r5, r6 */
1364 0xe2177080, /* ands r7, #0x80 */
1365 0x1afffffb, /* bne 8168 <sp_16_busy> */
1367 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1368 0x03a05080, /* moveq r5, #128 ; 0x80 */
1369 0x0a000001, /* beq 81ac <sp_16_done> */
1370 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1371 0xeafffff0, /* b 8158 <sp_16_code> */
1373 /* 000081ac <sp_16_done>: */
1374 0xeafffffe /* b 81ac <sp_16_done> */
1377 static const uint32_t word_8_code
[] = {
1378 /* 000081b0 <sp_16_code_end>: */
1379 0xe4d05001, /* ldrb r5, [r0], #1 */
1380 0xe5c89000, /* strb r9, [r8] */
1381 0xe5cab000, /* strb r11, [r10] */
1382 0xe5c83000, /* strb r3, [r8] */
1383 0xe5c15000, /* strb r5, [r1] */
1384 0xe1a00000, /* nop (mov r0,r0) */
1386 /* 000081c0 <sp_8_busy>: */
1387 0xe5d16000, /* ldrb r6, [r1] */
1388 0xe0257006, /* eor r7, r5, r6 */
1389 0xe0147007, /* ands r7, r4, r7 */
1390 0x0a000007, /* beq 81f0 <sp_8_cont> */
1391 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1392 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1393 0xe5d16000, /* ldrb r6, [r1] */
1394 0xe0257006, /* eor r7, r5, r6 */
1395 0xe0147007, /* ands r7, r4, r7 */
1396 0x0a000001, /* beq 81f0 <sp_8_cont> */
1397 0xe3a05000, /* mov r5, #0 ; 0x0 */
1398 0x1a000004, /* bne 8204 <sp_8_done> */
1400 /* 000081f0 <sp_8_cont>: */
1401 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1402 0x03a05080, /* moveq r5, #128 ; 0x80 */
1403 0x0a000001, /* beq 8204 <sp_8_done> */
1404 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1405 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1407 /* 00008204 <sp_8_done>: */
1408 0xeafffffe /* b 8204 <sp_8_done> */
1411 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1412 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1413 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1415 int target_code_size
;
1416 const uint32_t *target_code_src
;
1418 switch (bank
->bus_width
)
1421 target_code_src
= word_8_code
;
1422 target_code_size
= sizeof(word_8_code
);
1425 /* Check for DQ5 support */
1426 if( cfi_info
->status_poll_mask
& (1 << 5) )
1428 target_code_src
= word_16_code
;
1429 target_code_size
= sizeof(word_16_code
);
1433 /* No DQ5 support. Use DQ7 DATA# polling only. */
1434 target_code_src
= word_16_code_dq7only
;
1435 target_code_size
= sizeof(word_16_code_dq7only
);
1439 target_code_src
= word_32_code
;
1440 target_code_size
= sizeof(word_32_code
);
1443 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1447 /* flash write code */
1448 if (!cfi_info
->write_algorithm
)
1450 uint8_t *target_code
;
1452 /* convert bus-width dependent algorithm code to correct endiannes */
1453 target_code
= malloc(target_code_size
);
1454 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1456 /* allocate working area */
1457 retval
= target_alloc_working_area(target
, target_code_size
,
1458 &cfi_info
->write_algorithm
);
1459 if (retval
!= ERROR_OK
)
1465 /* write algorithm code to working area */
1466 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1467 target_code_size
, target_code
)) != ERROR_OK
)
1475 /* the following code still assumes target code is fixed 24*4 bytes */
1477 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1480 if (buffer_size
<= 256)
1482 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1483 if (cfi_info
->write_algorithm
)
1484 target_free_working_area(target
, cfi_info
->write_algorithm
);
1486 LOG_WARNING("not enough working area available, can't do block memory writes");
1487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1491 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1492 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1493 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1494 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1495 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1496 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1497 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1498 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1499 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1500 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1504 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1506 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1508 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1509 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1510 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1511 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1512 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1513 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1514 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1515 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1516 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1518 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1519 cfi_info
->write_algorithm
->address
,
1520 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1521 10000, &armv4_5_info
);
1523 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1525 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1527 LOG_DEBUG("status: 0x%" PRIx32
, status
);
1528 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1532 buffer
+= thisrun_count
;
1533 address
+= thisrun_count
;
1534 count
-= thisrun_count
;
1537 target_free_all_working_areas(target
);
1539 destroy_reg_param(®_params
[0]);
1540 destroy_reg_param(®_params
[1]);
1541 destroy_reg_param(®_params
[2]);
1542 destroy_reg_param(®_params
[3]);
1543 destroy_reg_param(®_params
[4]);
1544 destroy_reg_param(®_params
[5]);
1545 destroy_reg_param(®_params
[6]);
1546 destroy_reg_param(®_params
[7]);
1547 destroy_reg_param(®_params
[8]);
1548 destroy_reg_param(®_params
[9]);
1553 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1556 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1557 struct target
*target
= bank
->target
;
1560 cfi_intel_clear_status_register(bank
);
1561 cfi_command(bank
, 0x40, command
);
1562 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1567 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1572 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1574 cfi_command(bank
, 0xff, command
);
1575 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1580 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1581 return ERROR_FLASH_OPERATION_FAILED
;
1587 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1590 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1591 struct target
*target
= bank
->target
;
1594 /* Calculate buffer size and boundary mask */
1595 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1596 uint32_t buffermask
= buffersize
-1;
1597 uint32_t bufferwsize
;
1599 /* Check for valid range */
1600 if (address
& buffermask
)
1602 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1603 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1604 return ERROR_FLASH_OPERATION_FAILED
;
1606 switch (bank
->chip_width
)
1608 case 4 : bufferwsize
= buffersize
/ 4; break;
1609 case 2 : bufferwsize
= buffersize
/ 2; break;
1610 case 1 : bufferwsize
= buffersize
; break;
1612 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1613 return ERROR_FLASH_OPERATION_FAILED
;
1616 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1619 /* Check for valid size */
1620 if (wordcount
> bufferwsize
)
1622 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1623 return ERROR_FLASH_OPERATION_FAILED
;
1626 /* Write to flash buffer */
1627 cfi_intel_clear_status_register(bank
);
1629 /* Initiate buffer operation _*/
1630 cfi_command(bank
, 0xE8, command
);
1631 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1635 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1637 cfi_command(bank
, 0xff, command
);
1638 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1643 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1644 return ERROR_FLASH_OPERATION_FAILED
;
1647 /* Write buffer wordcount-1 and data words */
1648 cfi_command(bank
, bufferwsize
-1, command
);
1649 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1654 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1659 /* Commit write operation */
1660 cfi_command(bank
, 0xd0, command
);
1661 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1665 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1667 cfi_command(bank
, 0xff, command
);
1668 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1673 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1674 return ERROR_FLASH_OPERATION_FAILED
;
1680 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1683 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1684 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1685 struct target
*target
= bank
->target
;
1688 cfi_command(bank
, 0xaa, command
);
1689 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1694 cfi_command(bank
, 0x55, command
);
1695 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1700 cfi_command(bank
, 0xa0, command
);
1701 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1706 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1711 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1713 cfi_command(bank
, 0xf0, command
);
1714 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1719 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1720 return ERROR_FLASH_OPERATION_FAILED
;
1726 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1729 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1730 struct target
*target
= bank
->target
;
1732 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1734 /* Calculate buffer size and boundary mask */
1735 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1736 uint32_t buffermask
= buffersize
-1;
1737 uint32_t bufferwsize
;
1739 /* Check for valid range */
1740 if (address
& buffermask
)
1742 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1743 return ERROR_FLASH_OPERATION_FAILED
;
1745 switch (bank
->chip_width
)
1747 case 4 : bufferwsize
= buffersize
/ 4; break;
1748 case 2 : bufferwsize
= buffersize
/ 2; break;
1749 case 1 : bufferwsize
= buffersize
; break;
1751 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1752 return ERROR_FLASH_OPERATION_FAILED
;
1755 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1757 /* Check for valid size */
1758 if (wordcount
> bufferwsize
)
1760 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1761 return ERROR_FLASH_OPERATION_FAILED
;
1765 cfi_command(bank
, 0xaa, command
);
1766 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1771 cfi_command(bank
, 0x55, command
);
1772 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1777 // Buffer load command
1778 cfi_command(bank
, 0x25, command
);
1779 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1784 /* Write buffer wordcount-1 and data words */
1785 cfi_command(bank
, bufferwsize
-1, command
);
1786 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1791 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1796 /* Commit write operation */
1797 cfi_command(bank
, 0x29, command
);
1798 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1803 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1805 cfi_command(bank
, 0xf0, command
);
1806 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1811 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1812 return ERROR_FLASH_OPERATION_FAILED
;
1818 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1820 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1822 switch (cfi_info
->pri_id
)
1826 return cfi_intel_write_word(bank
, word
, address
);
1829 return cfi_spansion_write_word(bank
, word
, address
);
1832 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1836 return ERROR_FLASH_OPERATION_FAILED
;
1839 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1841 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1843 switch (cfi_info
->pri_id
)
1847 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1850 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1853 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1857 return ERROR_FLASH_OPERATION_FAILED
;
1860 int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1862 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1863 struct target
*target
= bank
->target
;
1864 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1865 uint32_t write_p
, copy_p
;
1866 int align
; /* number of unaligned bytes */
1867 int blk_count
; /* number of bus_width bytes for block copy */
1868 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1872 if (bank
->target
->state
!= TARGET_HALTED
)
1874 LOG_ERROR("Target not halted");
1875 return ERROR_TARGET_NOT_HALTED
;
1878 if (offset
+ count
> bank
->size
)
1879 return ERROR_FLASH_DST_OUT_OF_BANK
;
1881 if (cfi_info
->qry
[0] != 'Q')
1882 return ERROR_FLASH_BANK_NOT_PROBED
;
1884 /* start at the first byte of the first word (bus_width size) */
1885 write_p
= address
& ~(bank
->bus_width
- 1);
1886 if ((align
= address
- write_p
) != 0)
1888 LOG_INFO("Fixup %d unaligned head bytes", align
);
1890 for (i
= 0; i
< bank
->bus_width
; i
++)
1891 current_word
[i
] = 0;
1894 /* copy bytes before the first write address */
1895 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1898 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1902 cfi_add_byte(bank
, current_word
, byte
);
1905 /* add bytes from the buffer */
1906 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1908 cfi_add_byte(bank
, current_word
, *buffer
++);
1913 /* if the buffer is already finished, copy bytes after the last write address */
1914 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1917 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1921 cfi_add_byte(bank
, current_word
, byte
);
1924 retval
= cfi_write_word(bank
, current_word
, write_p
);
1925 if (retval
!= ERROR_OK
)
1930 /* handle blocks of bus_size aligned bytes */
1931 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1932 switch (cfi_info
->pri_id
)
1934 /* try block writes (fails without working area) */
1937 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1940 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1943 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1944 retval
= ERROR_FLASH_OPERATION_FAILED
;
1947 if (retval
== ERROR_OK
)
1949 /* Increment pointers and decrease count on succesful block write */
1950 buffer
+= blk_count
;
1951 write_p
+= blk_count
;
1956 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1958 //adjust buffersize for chip width
1959 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1960 uint32_t buffermask
= buffersize
-1;
1961 uint32_t bufferwsize
;
1963 switch (bank
->chip_width
)
1965 case 4 : bufferwsize
= buffersize
/ 4; break;
1966 case 2 : bufferwsize
= buffersize
/ 2; break;
1967 case 1 : bufferwsize
= buffersize
; break;
1969 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1970 return ERROR_FLASH_OPERATION_FAILED
;
1973 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1975 /* fall back to memory writes */
1976 while (count
>= (uint32_t)bank
->bus_width
)
1979 if ((write_p
& 0xff) == 0)
1981 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
1984 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1986 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1987 if (retval
== ERROR_OK
)
1989 buffer
+= buffersize
;
1990 write_p
+= buffersize
;
1991 count
-= buffersize
;
1995 /* try the slow way? */
1998 for (i
= 0; i
< bank
->bus_width
; i
++)
1999 current_word
[i
] = 0;
2001 for (i
= 0; i
< bank
->bus_width
; i
++)
2003 cfi_add_byte(bank
, current_word
, *buffer
++);
2006 retval
= cfi_write_word(bank
, current_word
, write_p
);
2007 if (retval
!= ERROR_OK
)
2010 write_p
+= bank
->bus_width
;
2011 count
-= bank
->bus_width
;
2019 /* return to read array mode, so we can read from flash again for padding */
2020 cfi_command(bank
, 0xf0, current_word
);
2021 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2025 cfi_command(bank
, 0xff, current_word
);
2026 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2031 /* handle unaligned tail bytes */
2034 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2037 for (i
= 0; i
< bank
->bus_width
; i
++)
2038 current_word
[i
] = 0;
2040 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
2042 cfi_add_byte(bank
, current_word
, *buffer
++);
2045 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
2048 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
2052 cfi_add_byte(bank
, current_word
, byte
);
2054 retval
= cfi_write_word(bank
, current_word
, write_p
);
2055 if (retval
!= ERROR_OK
)
2059 /* return to read array mode */
2060 cfi_command(bank
, 0xf0, current_word
);
2061 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2065 cfi_command(bank
, 0xff, current_word
);
2066 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
2069 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2072 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2073 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2075 pri_ext
->_reversed_geometry
= 1;
2078 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2081 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2082 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2085 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2087 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2089 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2091 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2094 swap
= cfi_info
->erase_region_info
[i
];
2095 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2096 cfi_info
->erase_region_info
[j
] = swap
;
2101 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2103 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2104 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2105 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2107 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2108 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2112 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2114 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2115 struct target
*target
= bank
->target
;
2119 cfi_command(bank
, 0x98, command
);
2120 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, address
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2125 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2126 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2127 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2129 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2131 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2133 cfi_command(bank
, 0xf0, command
);
2134 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2138 cfi_command(bank
, 0xff, command
);
2139 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2143 LOG_ERROR("Could not probe bank: no QRY");
2144 return ERROR_FLASH_BANK_INVALID
;
2150 static int cfi_probe(struct flash_bank
*bank
)
2152 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2153 struct target
*target
= bank
->target
;
2155 int num_sectors
= 0;
2158 uint32_t unlock1
= 0x555;
2159 uint32_t unlock2
= 0x2aa;
2162 if (bank
->target
->state
!= TARGET_HALTED
)
2164 LOG_ERROR("Target not halted");
2165 return ERROR_TARGET_NOT_HALTED
;
2168 cfi_info
->probed
= 0;
2170 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2171 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2173 if (cfi_info
->jedec_probe
)
2179 /* switch to read identifier codes mode ("AUTOSELECT") */
2180 cfi_command(bank
, 0xaa, command
);
2181 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2185 cfi_command(bank
, 0x55, command
);
2186 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2190 cfi_command(bank
, 0x90, command
);
2191 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2196 if (bank
->chip_width
== 1)
2198 uint8_t manufacturer
, device_id
;
2199 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x00), &manufacturer
)) != ERROR_OK
)
2203 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x01), &device_id
)) != ERROR_OK
)
2207 cfi_info
->manufacturer
= manufacturer
;
2208 cfi_info
->device_id
= device_id
;
2210 else if (bank
->chip_width
== 2)
2212 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x00), &cfi_info
->manufacturer
)) != ERROR_OK
)
2216 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x01), &cfi_info
->device_id
)) != ERROR_OK
)
2222 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2223 /* switch back to read array mode */
2224 cfi_command(bank
, 0xf0, command
);
2225 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2229 cfi_command(bank
, 0xff, command
);
2230 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2235 /* check device/manufacturer ID for known non-CFI flashes. */
2236 cfi_fixup_non_cfi(bank
);
2238 /* query only if this is a CFI compatible flash,
2239 * otherwise the relevant info has already been filled in
2241 if (cfi_info
->not_cfi
== 0)
2245 /* enter CFI query mode
2246 * according to JEDEC Standard No. 68.01,
2247 * a single bus sequence with address = 0x55, data = 0x98 should put
2248 * the device into CFI query mode.
2250 * SST flashes clearly violate this, and we will consider them incompatbile for now
2253 retval
= cfi_query_string(bank
, 0x55);
2254 if (retval
!= ERROR_OK
)
2257 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2258 * be harmless enough:
2260 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2262 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2263 retval
= cfi_query_string(bank
, 0x555);
2265 if (retval
!= ERROR_OK
)
2268 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2269 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2270 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2271 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2273 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2275 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2276 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2277 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2278 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2279 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2280 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2281 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2282 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2283 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2284 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2285 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2286 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2288 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2289 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2290 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2291 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2292 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2293 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2294 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2295 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2296 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2297 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2298 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2300 cfi_info
->dev_size
= 1 << cfi_query_u8(bank
, 0, 0x27);
2301 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2302 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2303 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2305 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2307 if (cfi_info
->num_erase_regions
)
2309 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2310 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2312 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2313 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2315 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2316 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2321 cfi_info
->erase_region_info
= NULL
;
2324 /* We need to read the primary algorithm extended query table before calculating
2325 * the sector layout to be able to apply fixups
2327 switch (cfi_info
->pri_id
)
2329 /* Intel command set (standard and extended) */
2332 cfi_read_intel_pri_ext(bank
);
2334 /* AMD/Spansion, Atmel, ... command set */
2336 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2337 cfi_read_0002_pri_ext(bank
);
2340 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2344 /* return to read array mode
2345 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2347 cfi_command(bank
, 0xf0, command
);
2348 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2352 cfi_command(bank
, 0xff, command
);
2353 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2357 } /* end CFI case */
2359 /* apply fixups depending on the primary command set */
2360 switch (cfi_info
->pri_id
)
2362 /* Intel command set (standard and extended) */
2365 cfi_fixup(bank
, cfi_0001_fixups
);
2367 /* AMD/Spansion, Atmel, ... command set */
2369 cfi_fixup(bank
, cfi_0002_fixups
);
2372 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2376 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2378 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2381 if (cfi_info
->num_erase_regions
== 0)
2383 /* a device might have only one erase block, spanning the whole device */
2384 bank
->num_sectors
= 1;
2385 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2387 bank
->sectors
[sector
].offset
= 0x0;
2388 bank
->sectors
[sector
].size
= bank
->size
;
2389 bank
->sectors
[sector
].is_erased
= -1;
2390 bank
->sectors
[sector
].is_protected
= -1;
2394 uint32_t offset
= 0;
2396 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2398 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2401 bank
->num_sectors
= num_sectors
;
2402 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2404 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2407 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2409 bank
->sectors
[sector
].offset
= offset
;
2410 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2411 offset
+= bank
->sectors
[sector
].size
;
2412 bank
->sectors
[sector
].is_erased
= -1;
2413 bank
->sectors
[sector
].is_protected
= -1;
2417 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2419 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2420 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2424 cfi_info
->probed
= 1;
2429 static int cfi_auto_probe(struct flash_bank
*bank
)
2431 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2432 if (cfi_info
->probed
)
2434 return cfi_probe(bank
);
2438 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2441 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2442 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2443 struct target
*target
= bank
->target
;
2444 uint8_t command
[CFI_MAX_BUS_WIDTH
];
2447 /* check if block lock bits are supported on this device */
2448 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2449 return ERROR_FLASH_OPERATION_FAILED
;
2451 cfi_command(bank
, 0x90, command
);
2452 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2457 for (i
= 0; i
< bank
->num_sectors
; i
++)
2459 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2461 if (block_status
& 1)
2462 bank
->sectors
[i
].is_protected
= 1;
2464 bank
->sectors
[i
].is_protected
= 0;
2467 cfi_command(bank
, 0xff, command
);
2468 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2471 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2474 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2475 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2476 struct target
*target
= bank
->target
;
2480 cfi_command(bank
, 0xaa, command
);
2481 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2486 cfi_command(bank
, 0x55, command
);
2487 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2492 cfi_command(bank
, 0x90, command
);
2493 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2498 for (i
= 0; i
< bank
->num_sectors
; i
++)
2500 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2502 if (block_status
& 1)
2503 bank
->sectors
[i
].is_protected
= 1;
2505 bank
->sectors
[i
].is_protected
= 0;
2508 cfi_command(bank
, 0xf0, command
);
2509 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2512 static int cfi_protect_check(struct flash_bank
*bank
)
2514 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2516 if (bank
->target
->state
!= TARGET_HALTED
)
2518 LOG_ERROR("Target not halted");
2519 return ERROR_TARGET_NOT_HALTED
;
2522 if (cfi_info
->qry
[0] != 'Q')
2523 return ERROR_FLASH_BANK_NOT_PROBED
;
2525 switch (cfi_info
->pri_id
)
2529 return cfi_intel_protect_check(bank
);
2532 return cfi_spansion_protect_check(bank
);
2535 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2542 static int cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2545 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2547 if (cfi_info
->qry
[0] == (char)-1)
2549 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2553 if (cfi_info
->not_cfi
== 0)
2554 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2556 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2558 buf_size
-= printed
;
2560 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2561 cfi_info
->manufacturer
, cfi_info
->device_id
);
2563 buf_size
-= printed
;
2565 if (cfi_info
->not_cfi
== 0)
2567 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2569 buf_size
-= printed
;
2571 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2572 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2573 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2574 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2575 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2577 buf_size
-= printed
;
2579 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2580 1 << cfi_info
->word_write_timeout_typ
,
2581 1 << cfi_info
->buf_write_timeout_typ
,
2582 1 << cfi_info
->block_erase_timeout_typ
,
2583 1 << cfi_info
->chip_erase_timeout_typ
);
2585 buf_size
-= printed
;
2587 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2588 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2589 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2590 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2591 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2593 buf_size
-= printed
;
2595 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2597 cfi_info
->interface_desc
,
2598 1 << cfi_info
->max_buf_write_size
);
2600 buf_size
-= printed
;
2602 switch (cfi_info
->pri_id
)
2606 cfi_intel_info(bank
, buf
, buf_size
);
2609 cfi_spansion_info(bank
, buf
, buf_size
);
2612 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2620 struct flash_driver cfi_flash
= {
2622 .flash_bank_command
= &cfi_flash_bank_command
,
2623 .erase
= &cfi_erase
,
2624 .protect
= &cfi_protect
,
2625 .write
= &cfi_write
,
2626 .probe
= &cfi_probe
,
2627 .auto_probe
= &cfi_auto_probe
,
2628 .erase_check
= &default_flash_blank_check
,
2629 .protect_check
= &cfi_protect_check
,