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flash: erase_address now has an unlock option
[openocd/cortex.git] / src / target / arm11.c
blob36bbaba1239ebc19d8f6992312daf665f78a885b
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * Copyright (C) 2009 David Brownell *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "etm.h"
32 #include "breakpoints.h"
33 #include "arm11_dbgtap.h"
34 #include "arm_simulator.h"
35 #include <helper/time_support.h>
36 #include "target_type.h"
37 #include "algorithm.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40
41
42 #if 0
43 #define _DEBUG_INSTRUCTION_EXECUTION_
44 #endif
45
46
47 static int arm11_step(struct target *target, int current,
48 uint32_t address, int handle_breakpoints);
49
50
51 /** Check and if necessary take control of the system
52 *
53 * \param arm11 Target state variable.
54 */
55 static int arm11_check_init(struct arm11_common *arm11)
56 {
57 CHECK_RETVAL(arm11_read_DSCR(arm11));
58
59 if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
60 {
61 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
62 LOG_DEBUG("Bringing target into debug mode");
63
64 arm11->dscr |= DSCR_HALT_DBG_MODE;
65 arm11_write_DSCR(arm11, arm11->dscr);
66
67 /* add further reset initialization here */
68
69 arm11->simulate_reset_on_next_halt = true;
70
71 if (arm11->dscr & DSCR_CORE_HALTED)
72 {
73 /** \todo TODO: this needs further scrutiny because
74 * arm11_debug_entry() never gets called. (WHY NOT?)
75 * As a result we don't read the actual register states from
76 * the target.
77 */
78
79 arm11->arm.target->state = TARGET_HALTED;
80 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
81 }
82 else
83 {
84 arm11->arm.target->state = TARGET_RUNNING;
85 arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
86 }
87
88 arm11_sc7_clear_vbw(arm11);
89 }
90
91 return ERROR_OK;
92 }
93
94 /**
95 * Save processor state. This is called after a HALT instruction
96 * succeeds, and on other occasions the processor enters debug mode
97 * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
98 */
99 static int arm11_debug_entry(struct arm11_common *arm11)
100 {
101 int retval;
102
103 arm11->arm.target->state = TARGET_HALTED;
104 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
105
106 /* REVISIT entire cache should already be invalid !!! */
107 register_cache_invalidate(arm11->arm.core_cache);
108
109 /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
110
111 /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
112 arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
113 if (arm11->is_wdtr_saved)
114 {
115 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
116
117 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
118
119 struct scan_field chain5_fields[3];
120
121 arm11_setup_field(arm11, 32, NULL,
122 &arm11->saved_wdtr, chain5_fields + 0);
123 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
124 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
125
126 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
127
128 }
129
130 /* DSCR: set the Execute ARM instruction enable bit.
131 *
132 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
133 * but not to issue ITRs(?). The ARMv7 arch spec says it's required
134 * for executing instructions via ITR.
135 */
136 arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
137
138
139 /* From the spec:
140 Before executing any instruction in debug state you have to drain the write buffer.
141 This ensures that no imprecise Data Aborts can return at a later point:*/
142
143 /** \todo TODO: Test drain write buffer. */
144
145 #if 0
146 while (1)
147 {
148 /* MRC p14,0,R0,c5,c10,0 */
149 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
150
151 /* mcr 15, 0, r0, cr7, cr10, {4} */
152 arm11_run_instr_no_data1(arm11, 0xee070f9a);
153
154 uint32_t dscr = arm11_read_DSCR(arm11);
155
156 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
157
158 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
159 {
160 arm11_run_instr_no_data1(arm11, 0xe320f000);
161
162 dscr = arm11_read_DSCR(arm11);
163
164 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
165
166 break;
167 }
168 }
169 #endif
170
171 /* Save registers.
172 *
173 * NOTE: ARM1136 TRM suggests saving just R0 here now, then
174 * CPSR and PC after the rDTR stuff. We do it all at once.
175 */
176 retval = arm_dpm_read_current_registers(&arm11->dpm);
177 if (retval != ERROR_OK)
178 LOG_ERROR("DPM REG READ -- fail %d", retval);
179
180 retval = arm11_run_instr_data_prepare(arm11);
181 if (retval != ERROR_OK)
182 return retval;
183
184 /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
185 arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
186 if (arm11->is_rdtr_saved)
187 {
188 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
189 retval = arm11_run_instr_data_from_core_via_r0(arm11,
190 0xEE100E15, &arm11->saved_rdtr);
191 if (retval != ERROR_OK)
192 return retval;
193 }
194
195 /* REVISIT Now that we've saved core state, there's may also
196 * be MMU and cache state to care about ...
197 */
198
199 if (arm11->simulate_reset_on_next_halt)
200 {
201 arm11->simulate_reset_on_next_halt = false;
202
203 LOG_DEBUG("Reset c1 Control Register");
204
205 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
206
207 /* MCR p15,0,R0,c1,c0,0 */
208 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
209 if (retval != ERROR_OK)
210 return retval;
211
212 }
213
214 if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
215 uint32_t wfar;
216
217 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
218 retval = arm11_run_instr_data_from_core_via_r0(arm11,
219 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
220 &wfar);
221 if (retval != ERROR_OK)
222 return retval;
223 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
224 }
225
226
227 retval = arm11_run_instr_data_finish(arm11);
228 if (retval != ERROR_OK)
229 return retval;
230
231 return ERROR_OK;
232 }
233
234 /**
235 * Restore processor state. This is called in preparation for
236 * the RESTART function.
237 */
238 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
239 {
240 int retval;
241
242 /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
243
244 /* NOTE: the ARM1136 TRM suggests restoring all registers
245 * except R0/PC/CPSR right now. Instead, we do them all
246 * at once, just a bit later on.
247 */
248
249 /* REVISIT once we start caring about MMU and cache state,
250 * address it here ...
251 */
252
253 /* spec says clear wDTR and rDTR; we assume they are clear as
254 otherwise our programming would be sloppy */
255 {
256 CHECK_RETVAL(arm11_read_DSCR(arm11));
257
258 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
259 {
260 /*
261 The wDTR/rDTR two registers that are used to send/receive data to/from
262 the core in tandem with corresponding instruction codes that are
263 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
264 registers hold data that was written by one side (CPU or JTAG) and not
265 read out by the other side.
266 */
267 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
268 (unsigned) arm11->dscr);
269 return ERROR_FAIL;
270 }
271 }
272
273 /* maybe restore original wDTR */
274 if (arm11->is_wdtr_saved)
275 {
276 retval = arm11_run_instr_data_prepare(arm11);
277 if (retval != ERROR_OK)
278 return retval;
279
280 /* MCR p14,0,R0,c0,c5,0 */
281 retval = arm11_run_instr_data_to_core_via_r0(arm11,
282 0xee000e15, arm11->saved_wdtr);
283 if (retval != ERROR_OK)
284 return retval;
285
286 retval = arm11_run_instr_data_finish(arm11);
287 if (retval != ERROR_OK)
288 return retval;
289 }
290
291 /* restore CPSR, PC, and R0 ... after flushing any modified
292 * registers.
293 */
294 retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
295
296 retval = arm11_bpwp_flush(arm11);
297
298 register_cache_invalidate(arm11->arm.core_cache);
299
300 /* restore DSCR */
301 arm11_write_DSCR(arm11, arm11->dscr);
302
303 /* maybe restore rDTR */
304 if (arm11->is_rdtr_saved)
305 {
306 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
307
308 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
309
310 struct scan_field chain5_fields[3];
311
312 uint8_t Ready = 0; /* ignored */
313 uint8_t Valid = 0; /* ignored */
314
315 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
316 NULL, chain5_fields + 0);
317 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
318 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
319
320 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
321 }
322
323 /* now processor is ready to RESTART */
324
325 return ERROR_OK;
326 }
327
328 /* poll current target status */
329 static int arm11_poll(struct target *target)
330 {
331 int retval;
332 struct arm11_common *arm11 = target_to_arm11(target);
333
334 CHECK_RETVAL(arm11_check_init(arm11));
335
336 if (arm11->dscr & DSCR_CORE_HALTED)
337 {
338 if (target->state != TARGET_HALTED)
339 {
340 enum target_state old_state = target->state;
341
342 LOG_DEBUG("enter TARGET_HALTED");
343 retval = arm11_debug_entry(arm11);
344 if (retval != ERROR_OK)
345 return retval;
346
347 target_call_event_callbacks(target,
348 (old_state == TARGET_DEBUG_RUNNING)
349 ? TARGET_EVENT_DEBUG_HALTED
350 : TARGET_EVENT_HALTED);
351 }
352 }
353 else
354 {
355 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
356 {
357 LOG_DEBUG("enter TARGET_RUNNING");
358 target->state = TARGET_RUNNING;
359 target->debug_reason = DBG_REASON_NOTHALTED;
360 }
361 }
362
363 return ERROR_OK;
364 }
365 /* architecture specific status reply */
366 static int arm11_arch_state(struct target *target)
367 {
368 struct arm11_common *arm11 = target_to_arm11(target);
369 int retval;
370
371 retval = arm_arch_state(target);
372
373 /* REVISIT also display ARM11-specific MMU and cache status ... */
374
375 if (target->debug_reason == DBG_REASON_WATCHPOINT)
376 LOG_USER("Watchpoint triggered at PC %#08x",
377 (unsigned) arm11->dpm.wp_pc);
378
379 return retval;
380 }
381
382 /* target request support */
383 static int arm11_target_request_data(struct target *target,
384 uint32_t size, uint8_t *buffer)
385 {
386 LOG_WARNING("Not implemented: %s", __func__);
387
388 return ERROR_FAIL;
389 }
390
391 /* target execution control */
392 static int arm11_halt(struct target *target)
393 {
394 struct arm11_common *arm11 = target_to_arm11(target);
395
396 LOG_DEBUG("target->state: %s",
397 target_state_name(target));
398
399 if (target->state == TARGET_UNKNOWN)
400 {
401 arm11->simulate_reset_on_next_halt = true;
402 }
403
404 if (target->state == TARGET_HALTED)
405 {
406 LOG_DEBUG("target was already halted");
407 return ERROR_OK;
408 }
409
410 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
411
412 CHECK_RETVAL(jtag_execute_queue());
413
414 int i = 0;
415
416 while (1)
417 {
418 CHECK_RETVAL(arm11_read_DSCR(arm11));
419
420 if (arm11->dscr & DSCR_CORE_HALTED)
421 break;
422
423
424 long long then = 0;
425 if (i == 1000)
426 {
427 then = timeval_ms();
428 }
429 if (i >= 1000)
430 {
431 if ((timeval_ms()-then) > 1000)
432 {
433 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
434 return ERROR_FAIL;
435 }
436 }
437 i++;
438 }
439
440 enum target_state old_state = target->state;
441
442 arm11_debug_entry(arm11);
443
444 CHECK_RETVAL(
445 target_call_event_callbacks(target,
446 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
447
448 return ERROR_OK;
449 }
450
451 static uint32_t
452 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
453 {
454 void *value = arm11->arm.pc->value;
455
456 if (!current)
457 buf_set_u32(value, 0, 32, address);
458 else
459 address = buf_get_u32(value, 0, 32);
460
461 return address;
462 }
463
464 static int arm11_resume(struct target *target, int current,
465 uint32_t address, int handle_breakpoints, int debug_execution)
466 {
467 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
468 // current, address, handle_breakpoints, debug_execution);
469
470 struct arm11_common *arm11 = target_to_arm11(target);
471
472 LOG_DEBUG("target->state: %s",
473 target_state_name(target));
474
475
476 if (target->state != TARGET_HALTED)
477 {
478 LOG_ERROR("Target not halted");
479 return ERROR_TARGET_NOT_HALTED;
480 }
481
482 address = arm11_nextpc(arm11, current, address);
483
484 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
485
486 /* clear breakpoints/watchpoints and VCR*/
487 arm11_sc7_clear_vbw(arm11);
488
489 if (!debug_execution)
490 target_free_all_working_areas(target);
491
492 /* Should we skip over breakpoints matching the PC? */
493 if (handle_breakpoints) {
494 struct breakpoint *bp;
495
496 for (bp = target->breakpoints; bp; bp = bp->next)
497 {
498 if (bp->address == address)
499 {
500 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
501 arm11_step(target, 1, 0, 0);
502 break;
503 }
504 }
505 }
506
507 /* activate all breakpoints */
508 if (true) {
509 struct breakpoint *bp;
510 unsigned brp_num = 0;
511
512 for (bp = target->breakpoints; bp; bp = bp->next)
513 {
514 struct arm11_sc7_action brp[2];
515
516 brp[0].write = 1;
517 brp[0].address = ARM11_SC7_BVR0 + brp_num;
518 brp[0].value = bp->address;
519 brp[1].write = 1;
520 brp[1].address = ARM11_SC7_BCR0 + brp_num;
521 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
522
523 arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
524
525 LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
526 bp->address);
527
528 brp_num++;
529 }
530
531 if (arm11->vcr)
532 arm11_sc7_set_vcr(arm11, arm11->vcr);
533 }
534
535 /* activate all watchpoints and breakpoints */
536 arm11_leave_debug_state(arm11, true);
537
538 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
539
540 CHECK_RETVAL(jtag_execute_queue());
541
542 int i = 0;
543 while (1)
544 {
545 CHECK_RETVAL(arm11_read_DSCR(arm11));
546
547 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
548
549 if (arm11->dscr & DSCR_CORE_RESTARTED)
550 break;
551
552
553 long long then = 0;
554 if (i == 1000)
555 {
556 then = timeval_ms();
557 }
558 if (i >= 1000)
559 {
560 if ((timeval_ms()-then) > 1000)
561 {
562 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
563 return ERROR_FAIL;
564 }
565 }
566 i++;
567 }
568
569 target->debug_reason = DBG_REASON_NOTHALTED;
570 if (!debug_execution)
571 target->state = TARGET_RUNNING;
572 else
573 target->state = TARGET_DEBUG_RUNNING;
574 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
575
576 return ERROR_OK;
577 }
578
579 static int arm11_step(struct target *target, int current,
580 uint32_t address, int handle_breakpoints)
581 {
582 LOG_DEBUG("target->state: %s",
583 target_state_name(target));
584
585 if (target->state != TARGET_HALTED)
586 {
587 LOG_WARNING("target was not halted");
588 return ERROR_TARGET_NOT_HALTED;
589 }
590
591 struct arm11_common *arm11 = target_to_arm11(target);
592
593 address = arm11_nextpc(arm11, current, address);
594
595 LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
596
597
598 /** \todo TODO: Thumb not supported here */
599
600 uint32_t next_instruction;
601
602 CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
603
604 /* skip over BKPT */
605 if ((next_instruction & 0xFFF00070) == 0xe1200070)
606 {
607 address = arm11_nextpc(arm11, 0, address + 4);
608 LOG_DEBUG("Skipping BKPT");
609 }
610 /* skip over Wait for interrupt / Standby */
611 /* mcr 15, 0, r?, cr7, cr0, {4} */
612 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
613 {
614 address = arm11_nextpc(arm11, 0, address + 4);
615 LOG_DEBUG("Skipping WFI");
616 }
617 /* ignore B to self */
618 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
619 {
620 LOG_DEBUG("Not stepping jump to self");
621 }
622 else
623 {
624 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
625 * with this. */
626
627 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
628 * the VCR might be something worth looking into. */
629
630
631 /* Set up breakpoint for stepping */
632
633 struct arm11_sc7_action brp[2];
634
635 brp[0].write = 1;
636 brp[0].address = ARM11_SC7_BVR0;
637 brp[1].write = 1;
638 brp[1].address = ARM11_SC7_BCR0;
639
640 if (arm11->hardware_step)
641 {
642 /* Hardware single stepping ("instruction address
643 * mismatch") is used if enabled. It's not quite
644 * exactly "run one instruction"; "branch to here"
645 * loops won't break, neither will some other cases,
646 * but it's probably the best default.
647 *
648 * Hardware single stepping isn't supported on v6
649 * debug modules. ARM1176 and v7 can support it...
650 *
651 * FIXME Thumb stepping likely needs to use 0x03
652 * or 0xc0 byte masks, not 0x0f.
653 */
654 brp[0].value = address;
655 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
656 | (0 << 14) | (0 << 16) | (0 << 20)
657 | (2 << 21);
658 } else
659 {
660 /* Sets a breakpoint on the next PC, as calculated
661 * by instruction set simulation.
662 *
663 * REVISIT stepping Thumb on ARM1156 requires Thumb2
664 * support from the simulator.
665 */
666 uint32_t next_pc;
667 int retval;
668
669 retval = arm_simulate_step(target, &next_pc);
670 if (retval != ERROR_OK)
671 return retval;
672
673 brp[0].value = next_pc;
674 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
675 | (0 << 14) | (0 << 16) | (0 << 20)
676 | (0 << 21);
677 }
678
679 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
680
681 /* resume */
682
683
684 if (arm11->step_irq_enable)
685 /* this disable should be redundant ... */
686 arm11->dscr &= ~DSCR_INT_DIS;
687 else
688 arm11->dscr |= DSCR_INT_DIS;
689
690
691 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
692
693 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
694
695 CHECK_RETVAL(jtag_execute_queue());
696
697 /* wait for halt */
698 int i = 0;
699
700 while (1)
701 {
702 const uint32_t mask = DSCR_CORE_RESTARTED
703 | DSCR_CORE_HALTED;
704
705 CHECK_RETVAL(arm11_read_DSCR(arm11));
706 LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
707
708 if ((arm11->dscr & mask) == mask)
709 break;
710
711 long long then = 0;
712 if (i == 1000)
713 {
714 then = timeval_ms();
715 }
716 if (i >= 1000)
717 {
718 if ((timeval_ms()-then) > 1000)
719 {
720 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
721 return ERROR_FAIL;
722 }
723 }
724 i++;
725 }
726
727 /* clear breakpoint */
728 arm11_sc7_clear_vbw(arm11);
729
730 /* save state */
731 CHECK_RETVAL(arm11_debug_entry(arm11));
732
733 /* restore default state */
734 arm11->dscr &= ~DSCR_INT_DIS;
735
736 }
737
738 target->debug_reason = DBG_REASON_SINGLESTEP;
739
740 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
741
742 return ERROR_OK;
743 }
744
745 static int arm11_assert_reset(struct target *target)
746 {
747 struct arm11_common *arm11 = target_to_arm11(target);
748
749 /* optionally catch reset vector */
750 if (target->reset_halt && !(arm11->vcr & 1))
751 arm11_sc7_set_vcr(arm11, arm11->vcr | 1);
752
753 /* Issue some kind of warm reset. */
754 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
755 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
756 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
757 /* REVISIT handle "pulls" cases, if there's
758 * hardware that needs them to work.
759 */
760 jtag_add_reset(0, 1);
761 } else {
762 LOG_ERROR("%s: how to reset?", target_name(target));
763 return ERROR_FAIL;
764 }
765
766 /* registers are now invalid */
767 register_cache_invalidate(arm11->arm.core_cache);
768
769 target->state = TARGET_RESET;
770
771 return ERROR_OK;
772 }
773
774 /*
775 * - There is another bug in the arm11 core. (iMX31 specific again?)
776 * When you generate an access to external logic (for example DDR
777 * controller via AHB bus) and that block is not configured (perhaps
778 * it is still held in reset), that transaction will never complete.
779 * This will hang arm11 core but it will also hang JTAG controller.
780 * Nothing short of srst assertion will bring it out of this.
781 */
782
783 static int arm11_deassert_reset(struct target *target)
784 {
785 struct arm11_common *arm11 = target_to_arm11(target);
786 int retval;
787
788 /* be certain SRST is off */
789 jtag_add_reset(0, 0);
790
791 /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
792 * at least DSCR. OMAP24xx doesn't show that problem, though
793 * SRST-only reset seems to be problematic for other reasons.
794 * (Secure boot sequences being one likelihood!)
795 */
796 jtag_add_tlr();
797
798 retval = arm11_poll(target);
799
800 if (target->reset_halt) {
801 if (target->state != TARGET_HALTED) {
802 LOG_WARNING("%s: ran after reset and before halt ...",
803 target_name(target));
804 if ((retval = target_halt(target)) != ERROR_OK)
805 return retval;
806 }
807 }
808
809 /* maybe restore vector catch config */
810 if (target->reset_halt && !(arm11->vcr & 1))
811 arm11_sc7_set_vcr(arm11, arm11->vcr);
812
813 return ERROR_OK;
814 }
815
816 static int arm11_soft_reset_halt(struct target *target)
817 {
818 LOG_WARNING("Not implemented: %s", __func__);
819
820 return ERROR_FAIL;
821 }
822
823 /* target memory access
824 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
825 * count: number of items of <size>
826 *
827 * arm11_config_memrw_no_increment - in the future we may want to be able
828 * to read/write a range of data to a "port". a "port" is an action on
829 * read memory address for some peripheral.
830 */
831 static int arm11_read_memory_inner(struct target *target,
832 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
833 bool arm11_config_memrw_no_increment)
834 {
835 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
836 int retval;
837
838 if (target->state != TARGET_HALTED)
839 {
840 LOG_WARNING("target was not halted");
841 return ERROR_TARGET_NOT_HALTED;
842 }
843
844 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
845
846 struct arm11_common *arm11 = target_to_arm11(target);
847
848 retval = arm11_run_instr_data_prepare(arm11);
849 if (retval != ERROR_OK)
850 return retval;
851
852 /* MRC p14,0,r0,c0,c5,0 */
853 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
854 if (retval != ERROR_OK)
855 return retval;
856
857 switch (size)
858 {
859 case 1:
860 arm11->arm.core_cache->reg_list[1].dirty = true;
861
862 for (size_t i = 0; i < count; i++)
863 {
864 /* ldrb r1, [r0], #1 */
865 /* ldrb r1, [r0] */
866 arm11_run_instr_no_data1(arm11,
867 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
868
869 uint32_t res;
870 /* MCR p14,0,R1,c0,c5,0 */
871 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
872
873 *buffer++ = res;
874 }
875
876 break;
877
878 case 2:
879 {
880 arm11->arm.core_cache->reg_list[1].dirty = true;
881
882 for (size_t i = 0; i < count; i++)
883 {
884 /* ldrh r1, [r0], #2 */
885 arm11_run_instr_no_data1(arm11,
886 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
887
888 uint32_t res;
889
890 /* MCR p14,0,R1,c0,c5,0 */
891 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
892
893 uint16_t svalue = res;
894 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
895 }
896
897 break;
898 }
899
900 case 4:
901 {
902 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
903 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
904 uint32_t *words = (uint32_t *)buffer;
905
906 /* LDC p14,c5,[R0],#4 */
907 /* LDC p14,c5,[R0] */
908 arm11_run_instr_data_from_core(arm11, instr, words, count);
909 break;
910 }
911 }
912
913 return arm11_run_instr_data_finish(arm11);
914 }
915
916 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
917 {
918 return arm11_read_memory_inner(target, address, size, count, buffer, false);
919 }
920
921 /*
922 * no_increment - in the future we may want to be able
923 * to read/write a range of data to a "port". a "port" is an action on
924 * read memory address for some peripheral.
925 */
926 static int arm11_write_memory_inner(struct target *target,
927 uint32_t address, uint32_t size,
928 uint32_t count, uint8_t *buffer,
929 bool no_increment)
930 {
931 int retval;
932
933 if (target->state != TARGET_HALTED)
934 {
935 LOG_WARNING("target was not halted");
936 return ERROR_TARGET_NOT_HALTED;
937 }
938
939 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
940
941 struct arm11_common *arm11 = target_to_arm11(target);
942
943 retval = arm11_run_instr_data_prepare(arm11);
944 if (retval != ERROR_OK)
945 return retval;
946
947 /* load r0 with buffer address */
948 /* MRC p14,0,r0,c0,c5,0 */
949 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
950 if (retval != ERROR_OK)
951 return retval;
952
953 /* burst writes are not used for single words as those may well be
954 * reset init script writes.
955 *
956 * The other advantage is that as burst writes are default, we'll
957 * now exercise both burst and non-burst code paths with the
958 * default settings, increasing code coverage.
959 */
960 bool burst = arm11->memwrite_burst && (count > 1);
961
962 switch (size)
963 {
964 case 1:
965 {
966 arm11->arm.core_cache->reg_list[1].dirty = true;
967
968 for (size_t i = 0; i < count; i++)
969 {
970 /* load r1 from DCC with byte data */
971 /* MRC p14,0,r1,c0,c5,0 */
972 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
973 if (retval != ERROR_OK)
974 return retval;
975
976 /* write r1 to memory */
977 /* strb r1, [r0], #1 */
978 /* strb r1, [r0] */
979 retval = arm11_run_instr_no_data1(arm11,
980 !no_increment
981 ? 0xe4c01001
982 : 0xe5c01000);
983 if (retval != ERROR_OK)
984 return retval;
985 }
986
987 break;
988 }
989
990 case 2:
991 {
992 arm11->arm.core_cache->reg_list[1].dirty = true;
993
994 for (size_t i = 0; i < count; i++)
995 {
996 uint16_t value;
997 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
998
999 /* load r1 from DCC with halfword data */
1000 /* MRC p14,0,r1,c0,c5,0 */
1001 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1002 if (retval != ERROR_OK)
1003 return retval;
1004
1005 /* write r1 to memory */
1006 /* strh r1, [r0], #2 */
1007 /* strh r1, [r0] */
1008 retval = arm11_run_instr_no_data1(arm11,
1009 !no_increment
1010 ? 0xe0c010b2
1011 : 0xe1c010b0);
1012 if (retval != ERROR_OK)
1013 return retval;
1014 }
1015
1016 break;
1017 }
1018
1019 case 4: {
1020 /* stream word data through DCC directly to memory */
1021 /* increment: STC p14,c5,[R0],#4 */
1022 /* no increment: STC p14,c5,[R0]*/
1023 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1024
1025 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1026 uint32_t *words = (uint32_t*)buffer;
1027
1028 /* "burst" here just means trusting each instruction executes
1029 * fully before we run the next one: per-word roundtrips, to
1030 * check the Ready flag, are not used.
1031 */
1032 if (!burst)
1033 retval = arm11_run_instr_data_to_core(arm11,
1034 instr, words, count);
1035 else
1036 retval = arm11_run_instr_data_to_core_noack(arm11,
1037 instr, words, count);
1038 if (retval != ERROR_OK)
1039 return retval;
1040
1041 break;
1042 }
1043 }
1044
1045 /* r0 verification */
1046 if (!no_increment)
1047 {
1048 uint32_t r0;
1049
1050 /* MCR p14,0,R0,c0,c5,0 */
1051 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1052 if (retval != ERROR_OK)
1053 return retval;
1054
1055 if (address + size * count != r0)
1056 {
1057 LOG_ERROR("Data transfer failed. Expected end "
1058 "address 0x%08x, got 0x%08x",
1059 (unsigned) (address + size * count),
1060 (unsigned) r0);
1061
1062 if (burst)
1063 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1064
1065 if (arm11->memwrite_error_fatal)
1066 return ERROR_FAIL;
1067 }
1068 }
1069
1070 return arm11_run_instr_data_finish(arm11);
1071 }
1072
1073 static int arm11_write_memory(struct target *target,
1074 uint32_t address, uint32_t size,
1075 uint32_t count, uint8_t *buffer)
1076 {
1077 /* pointer increment matters only for multi-unit writes ...
1078 * not e.g. to a "reset the chip" controller.
1079 */
1080 return arm11_write_memory_inner(target, address, size,
1081 count, buffer, count == 1);
1082 }
1083
1084 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1085 static int arm11_bulk_write_memory(struct target *target,
1086 uint32_t address, uint32_t count, uint8_t *buffer)
1087 {
1088 if (target->state != TARGET_HALTED)
1089 {
1090 LOG_WARNING("target was not halted");
1091 return ERROR_TARGET_NOT_HALTED;
1092 }
1093
1094 return arm11_write_memory(target, address, 4, count, buffer);
1095 }
1096
1097 /* target break-/watchpoint control
1098 * rw: 0 = write, 1 = read, 2 = access
1099 */
1100 static int arm11_add_breakpoint(struct target *target,
1101 struct breakpoint *breakpoint)
1102 {
1103 struct arm11_common *arm11 = target_to_arm11(target);
1104
1105 #if 0
1106 if (breakpoint->type == BKPT_SOFT)
1107 {
1108 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1109 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1110 }
1111 #endif
1112
1113 if (!arm11->free_brps)
1114 {
1115 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1116 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1117 }
1118
1119 if (breakpoint->length != 4)
1120 {
1121 LOG_DEBUG("only breakpoints of four bytes length supported");
1122 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1123 }
1124
1125 arm11->free_brps--;
1126
1127 return ERROR_OK;
1128 }
1129
1130 static int arm11_remove_breakpoint(struct target *target,
1131 struct breakpoint *breakpoint)
1132 {
1133 struct arm11_common *arm11 = target_to_arm11(target);
1134
1135 arm11->free_brps++;
1136
1137 return ERROR_OK;
1138 }
1139
1140 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1141 {
1142 struct arm11_common *arm11;
1143
1144 if (target->tap == NULL)
1145 return ERROR_FAIL;
1146
1147 if (target->tap->ir_length != 5)
1148 {
1149 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1150 return ERROR_COMMAND_SYNTAX_ERROR;
1151 }
1152
1153 arm11 = calloc(1, sizeof *arm11);
1154 if (!arm11)
1155 return ERROR_FAIL;
1156
1157 arm_init_arch_info(target, &arm11->arm);
1158
1159 arm11->jtag_info.tap = target->tap;
1160 arm11->jtag_info.scann_size = 5;
1161 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1162 arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
1163 arm11->jtag_info.intest_instr = ARM11_INTEST;
1164
1165 arm11->memwrite_burst = true;
1166 arm11->memwrite_error_fatal = true;
1167
1168 return ERROR_OK;
1169 }
1170
1171 static int arm11_init_target(struct command_context *cmd_ctx,
1172 struct target *target)
1173 {
1174 /* Initialize anything we can set up without talking to the target */
1175 return ERROR_OK;
1176 }
1177
1178 /* talk to the target and set things up */
1179 static int arm11_examine(struct target *target)
1180 {
1181 int retval;
1182 char *type;
1183 struct arm11_common *arm11 = target_to_arm11(target);
1184 uint32_t didr, device_id;
1185 uint8_t implementor;
1186
1187 /* FIXME split into do-first-time and do-every-time logic ... */
1188
1189 /* check IDCODE */
1190
1191 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1192
1193 struct scan_field idcode_field;
1194
1195 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1196
1197 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
1198
1199 /* check DIDR */
1200
1201 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1202
1203 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1204
1205 struct scan_field chain0_fields[2];
1206
1207 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1208 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1209
1210 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1211
1212 CHECK_RETVAL(jtag_execute_queue());
1213
1214 /* assume the manufacturer id is ok; check the part # */
1215 switch ((device_id >> 12) & 0xFFFF)
1216 {
1217 case 0x7B36:
1218 type = "ARM1136";
1219 break;
1220 case 0x7B37:
1221 type = "ARM11 MPCore";
1222 break;
1223 case 0x7B56:
1224 type = "ARM1156";
1225 break;
1226 case 0x7B76:
1227 arm11->arm.core_type = ARM_MODE_MON;
1228 /* NOTE: could default arm11->hardware_step to true */
1229 type = "ARM1176";
1230 break;
1231 default:
1232 LOG_ERROR("unexpected ARM11 ID code");
1233 return ERROR_FAIL;
1234 }
1235 LOG_INFO("found %s", type);
1236
1237 /* unlikely this could ever fail, but ... */
1238 switch ((didr >> 16) & 0x0F) {
1239 case ARM11_DEBUG_V6:
1240 case ARM11_DEBUG_V61: /* supports security extensions */
1241 break;
1242 default:
1243 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1244 return ERROR_FAIL;
1245 }
1246
1247 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1248
1249 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1250 arm11->free_brps = arm11->brp;
1251
1252 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1253 device_id, implementor, didr);
1254
1255 /* as a side-effect this reads DSCR and thus
1256 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1257 * as suggested by the spec.
1258 */
1259
1260 retval = arm11_check_init(arm11);
1261 if (retval != ERROR_OK)
1262 return retval;
1263
1264 /* Build register cache "late", after target_init(), since we
1265 * want to know if this core supports Secure Monitor mode.
1266 */
1267 if (!target_was_examined(target))
1268 retval = arm11_dpm_init(arm11, didr);
1269
1270 /* ETM on ARM11 still uses original scanchain 6 access mode */
1271 if (arm11->arm.etm && !target_was_examined(target)) {
1272 *register_get_last_cache_p(&target->reg_cache) =
1273 etm_build_reg_cache(target, &arm11->jtag_info,
1274 arm11->arm.etm);
1275 retval = etm_setup(target);
1276 }
1277
1278 target_set_examined(target);
1279
1280 return ERROR_OK;
1281 }
1282
1283
1284 #define ARM11_BOOL_WRAPPER(name, print_name) \
1285 COMMAND_HANDLER(arm11_handle_bool_##name) \
1286 { \
1287 struct target *target = get_current_target(CMD_CTX); \
1288 struct arm11_common *arm11 = target_to_arm11(target); \
1289 \
1290 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1291 &arm11->name, print_name); \
1292 }
1293
1294 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1295 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1296 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1297 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1298
1299 /* REVISIT handle the VCR bits like other ARMs: use symbols for
1300 * input and output values.
1301 */
1302
1303 COMMAND_HANDLER(arm11_handle_vcr)
1304 {
1305 struct target *target = get_current_target(CMD_CTX);
1306 struct arm11_common *arm11 = target_to_arm11(target);
1307
1308 switch (CMD_ARGC) {
1309 case 0:
1310 break;
1311 case 1:
1312 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
1313 break;
1314 default:
1315 return ERROR_COMMAND_SYNTAX_ERROR;
1316 }
1317
1318 LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
1319 return ERROR_OK;
1320 }
1321
1322 static const struct command_registration arm11_mw_command_handlers[] = {
1323 {
1324 .name = "burst",
1325 .handler = arm11_handle_bool_memwrite_burst,
1326 .mode = COMMAND_ANY,
1327 .help = "Display or modify flag controlling potentially "
1328 "risky fast burst mode (default: enabled)",
1329 .usage = "['enable'|'disable']",
1330 },
1331 {
1332 .name = "error_fatal",
1333 .handler = arm11_handle_bool_memwrite_error_fatal,
1334 .mode = COMMAND_ANY,
1335 .help = "Display or modify flag controlling transfer "
1336 "termination on transfer errors"
1337 " (default: enabled)",
1338 .usage = "['enable'|'disable']",
1339 },
1340 COMMAND_REGISTRATION_DONE
1341 };
1342 static const struct command_registration arm11_any_command_handlers[] = {
1343 {
1344 /* "hardware_step" is only here to check if the default
1345 * simulate + breakpoint implementation is broken.
1346 * TEMPORARY! NOT DOCUMENTED! */
1347 .name = "hardware_step",
1348 .handler = arm11_handle_bool_hardware_step,
1349 .mode = COMMAND_ANY,
1350 .help = "DEBUG ONLY - Hardware single stepping"
1351 " (default: disabled)",
1352 .usage = "['enable'|'disable']",
1353 },
1354 {
1355 .name = "memwrite",
1356 .mode = COMMAND_ANY,
1357 .help = "memwrite command group",
1358 .chain = arm11_mw_command_handlers,
1359 },
1360 {
1361 .name = "step_irq_enable",
1362 .handler = arm11_handle_bool_step_irq_enable,
1363 .mode = COMMAND_ANY,
1364 .help = "Display or modify flag controlling interrupt "
1365 "enable while stepping (default: disabled)",
1366 .usage = "['enable'|'disable']",
1367 },
1368 {
1369 .name = "vcr",
1370 .handler = arm11_handle_vcr,
1371 .mode = COMMAND_ANY,
1372 .help = "Display or modify Vector Catch Register",
1373 .usage = "[value]",
1374 },
1375 COMMAND_REGISTRATION_DONE
1376 };
1377
1378 static const struct command_registration arm11_command_handlers[] = {
1379 {
1380 .chain = arm_command_handlers,
1381 },
1382 {
1383 .chain = etm_command_handlers,
1384 },
1385 {
1386 .name = "arm11",
1387 .mode = COMMAND_ANY,
1388 .help = "ARM11 command group",
1389 .chain = arm11_any_command_handlers,
1390 },
1391 COMMAND_REGISTRATION_DONE
1392 };
1393
1394 /** Holds methods for ARM11xx targets. */
1395 struct target_type arm11_target = {
1396 .name = "arm11",
1397
1398 .poll = arm11_poll,
1399 .arch_state = arm11_arch_state,
1400
1401 .target_request_data = arm11_target_request_data,
1402
1403 .halt = arm11_halt,
1404 .resume = arm11_resume,
1405 .step = arm11_step,
1406
1407 .assert_reset = arm11_assert_reset,
1408 .deassert_reset = arm11_deassert_reset,
1409 .soft_reset_halt = arm11_soft_reset_halt,
1410
1411 .get_gdb_reg_list = arm_get_gdb_reg_list,
1412
1413 .read_memory = arm11_read_memory,
1414 .write_memory = arm11_write_memory,
1415
1416 .bulk_write_memory = arm11_bulk_write_memory,
1417
1418 .checksum_memory = arm_checksum_memory,
1419 .blank_check_memory = arm_blank_check_memory,
1420
1421 .add_breakpoint = arm11_add_breakpoint,
1422 .remove_breakpoint = arm11_remove_breakpoint,
1423
1424 .run_algorithm = armv4_5_run_algorithm,
1425
1426 .commands = arm11_command_handlers,
1427 .target_create = arm11_target_create,
1428 .init_target = arm11_init_target,
1429 .examine = arm11_examine,
1430 };
Marex's Cortex A8 development branch