src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include <helper/time_support.h>
  29 #include "target_type.h"
  30 #include "register.h"
  31 #include "arm_opcodes.h"
  32
  33
  34 /*
  35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  36  * ARM DDI 0229C especially Chapter 9 about debug support.
  37  */
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static int arm720t_scan_cp15(struct target *target,
  44                 uint32_t out, uint32_t *in, int instruction, int clock)
  45 {
  46         int retval;
  47         struct arm720t_common *arm720t = target_to_arm720(target);
  48         struct arm_jtag *jtag_info;
  49         struct scan_field fields[2];
  50         uint8_t out_buf[4];
  51         uint8_t instruction_buf = instruction;
  52
  53         jtag_info = &arm720t->arm7_9_common.jtag_info;
  54
  55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  56
  57         jtag_set_end_state(TAP_DRPAUSE);
  58         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
  59         {
  60                 return retval;
  61         }
  62         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
  63         {
  64                 return retval;
  65         }
  66
  67         fields[0].num_bits = 1;
  68         fields[0].out_value = &instruction_buf;
  69         fields[0].in_value = NULL;
  70
  71         fields[1].num_bits = 32;
  72         fields[1].out_value = out_buf;
  73         fields[1].in_value = NULL;
  74
  75         if (in)
  76         {
  77                 fields[1].in_value = (uint8_t *)in;
  78                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  79                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  80         } else
  81         {
  82                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  83         }
  84
  85         if (clock)
  86                 jtag_add_runtest(0, TAP_DRPAUSE);
  87
  88 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  89         if ((retval = jtag_execute_queue()) != ERROR_OK)
  90         {
  91                 return retval;
  92         }
  93
  94         if (in)
  95                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  96         else
  97                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  98 #else
  99                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 100 #endif
 101
 102         return ERROR_OK;
 103 }
 104
 105 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 106 {
 107         /* fetch CP15 opcode */
 108         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 109         /* "DECODE" stage */
 110         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 111         /* "EXECUTE" stage (1) */
 112         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 113         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 114         /* "EXECUTE" stage (2) */
 115         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 116         /* "EXECUTE" stage (3), CDATA is read */
 117         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 118
 119         return ERROR_OK;
 120 }
 121
 122 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 123 {
 124         /* fetch CP15 opcode */
 125         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 126         /* "DECODE" stage */
 127         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 128         /* "EXECUTE" stage (1) */
 129         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 130         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 131         /* "EXECUTE" stage (2) */
 132         arm720t_scan_cp15(target, value, NULL, 0, 1);
 133         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 134
 135         return ERROR_OK;
 136 }
 137
 138 static uint32_t arm720t_get_ttb(struct target *target)
 139 {
 140         uint32_t ttb = 0x0;
 141
 142         arm720t_read_cp15(target, 0xee120f10, &ttb);
 143         jtag_execute_queue();
 144
 145         ttb &= 0xffffc000;
 146
 147         return ttb;
 148 }
 149
 150 static void arm720t_disable_mmu_caches(struct target *target,
 151                 int mmu, int d_u_cache, int i_cache)
 152 {
 153         uint32_t cp15_control;
 154
 155         /* read cp15 control register */
 156         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 157         jtag_execute_queue();
 158
 159         if (mmu)
 160                 cp15_control &= ~0x1U;
 161
 162         if (d_u_cache || i_cache)
 163                 cp15_control &= ~0x4U;
 164
 165         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 166 }
 167
 168 static void arm720t_enable_mmu_caches(struct target *target,
 169                 int mmu, int d_u_cache, int i_cache)
 170 {
 171         uint32_t cp15_control;
 172
 173         /* read cp15 control register */
 174         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 175         jtag_execute_queue();
 176
 177         if (mmu)
 178                 cp15_control |= 0x1U;
 179
 180         if (d_u_cache || i_cache)
 181                 cp15_control |= 0x4U;
 182
 183         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 184 }
 185
 186 static void arm720t_post_debug_entry(struct target *target)
 187 {
 188         struct arm720t_common *arm720t = target_to_arm720(target);
 189
 190         /* examine cp15 control reg */
 191         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 192         jtag_execute_queue();
 193         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 194
 195         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 196         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 197         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 198
 199         /* save i/d fault status and address register */
 200         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 201         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 202         jtag_execute_queue();
 203 }
 204
 205 static void arm720t_pre_restore_context(struct target *target)
 206 {
 207         struct arm720t_common *arm720t = target_to_arm720(target);
 208
 209         /* restore i/d fault status and address register */
 210         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 211         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 212 }
 213
 214 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 215                 struct arm720t_common *arm720t)
 216 {
 217         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 218                 command_print(cmd_ctx, "target is not an ARM720");
 219                 return ERROR_TARGET_INVALID;
 220         }
 221         return ERROR_OK;
 222 }
 223
 224 static int arm720t_arch_state(struct target *target)
 225 {
 226         struct arm720t_common *arm720t = target_to_arm720(target);
 227         struct arm *armv4_5;
 228
 229         static const char *state[] =
 230         {
 231                 "disabled", "enabled"
 232         };
 233
 234         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 235
 236         arm_arch_state(target);
 237         LOG_USER("MMU: %s, Cache: %s",
 238                          state[arm720t->armv4_5_mmu.mmu_enabled],
 239                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 240
 241         return ERROR_OK;
 242 }
 243
 244 static int arm720_mmu(struct target *target, int *enabled)
 245 {
 246         if (target->state != TARGET_HALTED) {
 247                 LOG_ERROR("%s: target not halted", __func__);
 248                 return ERROR_TARGET_INVALID;
 249         }
 250
 251         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 252         return ERROR_OK;
 253 }
 254
 255 static int arm720_virt2phys(struct target *target,
 256                 uint32_t virtual, uint32_t *physical)
 257 {
 258         int type;
 259         uint32_t cb;
 260         int domain;
 261         uint32_t ap;
 262         struct arm720t_common *arm720t = target_to_arm720(target);
 263
 264         uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 265         if (type == -1)
 266         {
 267                 return ret;
 268         }
 269         *physical = ret;
 270         return ERROR_OK;
 271 }
 272
 273 static int arm720t_read_memory(struct target *target,
 274                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 275 {
 276         int retval;
 277         struct arm720t_common *arm720t = target_to_arm720(target);
 278
 279         /* disable cache, but leave MMU enabled */
 280         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 281                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 282
 283         retval = arm7_9_read_memory(target, address, size, count, buffer);
 284
 285         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 286                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 287
 288         return retval;
 289 }
 290
 291 static int arm720t_read_phys_memory(struct target *target,
 292                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 293 {
 294         struct arm720t_common *arm720t = target_to_arm720(target);
 295
 296         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 297 }
 298
 299 static int arm720t_write_phys_memory(struct target *target,
 300                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 301 {
 302         struct arm720t_common *arm720t = target_to_arm720(target);
 303
 304         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 305 }
 306
 307 static int arm720t_soft_reset_halt(struct target *target)
 308 {
 309         int retval = ERROR_OK;
 310         struct arm720t_common *arm720t = target_to_arm720(target);
 311         struct reg *dbg_stat = &arm720t->arm7_9_common
 312                         .eice_cache->reg_list[EICE_DBG_STAT];
 313         struct arm *armv4_5 = &arm720t->arm7_9_common
 314                         .armv4_5_common;
 315
 316         if ((retval = target_halt(target)) != ERROR_OK)
 317         {
 318                 return retval;
 319         }
 320
 321         long long then = timeval_ms();
 322         int timeout;
 323         while (!(timeout = ((timeval_ms()-then) > 1000)))
 324         {
 325                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 326                 {
 327                         embeddedice_read_reg(dbg_stat);
 328                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 329                         {
 330                                 return retval;
 331                         }
 332                 } else
 333                 {
 334                         break;
 335                 }
 336                 if (debug_level >= 3)
 337                 {
 338                         alive_sleep(100);
 339                 } else
 340                 {
 341                         keep_alive();
 342                 }
 343         }
 344         if (timeout)
 345         {
 346                 LOG_ERROR("Failed to halt CPU after 1 sec");
 347                 return ERROR_TARGET_TIMEOUT;
 348         }
 349
 350         target->state = TARGET_HALTED;
 351
 352         /* SVC, ARM state, IRQ and FIQ disabled */
 353         uint32_t cpsr;
 354
 355         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 356         cpsr &= ~0xff;
 357         cpsr |= 0xd3;
 358         arm_set_cpsr(armv4_5, cpsr);
 359         armv4_5->cpsr->dirty = 1;
 360
 361         /* start fetching from 0x0 */
 362         buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
 363         armv4_5->pc->dirty = 1;
 364         armv4_5->pc->valid = 1;
 365
 366         arm720t_disable_mmu_caches(target, 1, 1, 1);
 367         arm720t->armv4_5_mmu.mmu_enabled = 0;
 368         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 369         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 370
 371         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 372         {
 373                 return retval;
 374         }
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 380 {
 381         return arm7tdmi_init_target(cmd_ctx, target);
 382 }
 383
 384 /* FIXME remove forward decls */
 385 static int arm720t_mrc(struct target *target, int cpnum,
 386                 uint32_t op1, uint32_t op2,
 387                 uint32_t CRn, uint32_t CRm,
 388                 uint32_t *value);
 389 static int arm720t_mcr(struct target *target, int cpnum,
 390                 uint32_t op1, uint32_t op2,
 391                 uint32_t CRn, uint32_t CRm,
 392                 uint32_t value);
 393
 394 static int arm720t_init_arch_info(struct target *target,
 395                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 396 {
 397         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 398
 399         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 400         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 401
 402         arm7tdmi_init_arch_info(target, arm7_9, tap);
 403
 404         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 405
 406         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 407         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 408
 409         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 410         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 411         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 412         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 413         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 414         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 415         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 416         arm720t->armv4_5_mmu.mmu_enabled = 0;
 417
 418         return ERROR_OK;
 419 }
 420
 421 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 422 {
 423         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 424
 425         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 426         return arm720t_init_arch_info(target, arm720t, target->tap);
 427 }
 428
 429 COMMAND_HANDLER(arm720t_handle_cp15_command)
 430 {
 431         int retval;
 432         struct target *target = get_current_target(CMD_CTX);
 433         struct arm720t_common *arm720t = target_to_arm720(target);
 434         struct arm_jtag *jtag_info;
 435
 436         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 437         if (retval != ERROR_OK)
 438                 return retval;
 439
 440         jtag_info = &arm720t->arm7_9_common.jtag_info;
 441
 442         if (target->state != TARGET_HALTED)
 443         {
 444                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 445                 return ERROR_OK;
 446         }
 447
 448         /* one or more argument, access a single register (write if second argument is given */
 449         if (CMD_ARGC >= 1)
 450         {
 451                 uint32_t opcode;
 452                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 453
 454                 if (CMD_ARGC == 1)
 455                 {
 456                         uint32_t value;
 457                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 458                         {
 459                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 460                                 return ERROR_OK;
 461                         }
 462
 463                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 464                         {
 465                                 return retval;
 466                         }
 467
 468                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 469                 }
 470                 else if (CMD_ARGC == 2)
 471                 {
 472                         uint32_t value;
 473                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 474
 475                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 476                         {
 477                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 478                                 return ERROR_OK;
 479                         }
 480                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 481                 }
 482         }
 483
 484         return ERROR_OK;
 485 }
 486
 487 static int arm720t_mrc(struct target *target, int cpnum,
 488                 uint32_t op1, uint32_t op2,
 489                 uint32_t CRn, uint32_t CRm,
 490                 uint32_t *value)
 491 {
 492         if (cpnum!=15)
 493         {
 494                 LOG_ERROR("Only cp15 is supported");
 495                 return ERROR_FAIL;
 496         }
 497
 498         /* read "to" r0 */
 499         return arm720t_read_cp15(target,
 500                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
 501                         value);
 502
 503 }
 504
 505 static int arm720t_mcr(struct target *target, int cpnum,
 506                 uint32_t op1, uint32_t op2,
 507                 uint32_t CRn, uint32_t CRm,
 508                 uint32_t value)
 509 {
 510         if (cpnum!=15)
 511         {
 512                 LOG_ERROR("Only cp15 is supported");
 513                 return ERROR_FAIL;
 514         }
 515
 516         /* write "from" r0 */
 517         return arm720t_write_cp15(target,
 518                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
 519                         value);
 520 }
 521
 522 static const struct command_registration arm720t_exec_command_handlers[] = {
 523         {
 524                 .name = "cp15",
 525                 .handler = arm720t_handle_cp15_command,
 526                 .mode = COMMAND_EXEC,
 527                 /* prefer using less error-prone "arm mcr" or "arm mrc" */
 528                 .help = "display/modify cp15 register using ARM opcode"
 529                         " (DEPRECATED)",
 530                 .usage = "instruction [value]",
 531         },
 532         COMMAND_REGISTRATION_DONE
 533 };
 534
 535 static const struct command_registration arm720t_command_handlers[] = {
 536         {
 537                 .chain = arm7_9_command_handlers,
 538         },
 539         {
 540                 .name = "arm720t",
 541                 .mode = COMMAND_ANY,
 542                 .help = "arm720t command group",
 543                 .chain = arm720t_exec_command_handlers,
 544         },
 545         COMMAND_REGISTRATION_DONE
 546 };
 547
 548 /** Holds methods for ARM720 targets. */
 549 struct target_type arm720t_target =
 550 {
 551         .name = "arm720t",
 552
 553         .poll = arm7_9_poll,
 554         .arch_state = arm720t_arch_state,
 555
 556         .halt = arm7_9_halt,
 557         .resume = arm7_9_resume,
 558         .step = arm7_9_step,
 559
 560         .assert_reset = arm7_9_assert_reset,
 561         .deassert_reset = arm7_9_deassert_reset,
 562         .soft_reset_halt = arm720t_soft_reset_halt,
 563
 564         .get_gdb_reg_list = arm_get_gdb_reg_list,
 565
 566         .read_memory = arm720t_read_memory,
 567         .write_memory = arm7_9_write_memory,
 568         .read_phys_memory = arm720t_read_phys_memory,
 569         .write_phys_memory = arm720t_write_phys_memory,
 570         .mmu = arm720_mmu,
 571         .virt2phys = arm720_virt2phys,
 572
 573         .bulk_write_memory = arm7_9_bulk_write_memory,
 574
 575         .checksum_memory = arm_checksum_memory,
 576         .blank_check_memory = arm_blank_check_memory,
 577
 578         .run_algorithm = armv4_5_run_algorithm,
 579
 580         .add_breakpoint = arm7_9_add_breakpoint,
 581         .remove_breakpoint = arm7_9_remove_breakpoint,
 582         .add_watchpoint = arm7_9_add_watchpoint,
 583         .remove_watchpoint = arm7_9_remove_watchpoint,
 584
 585         .commands = arm720t_command_handlers,
 586         .target_create = arm720t_target_create,
 587         .init_target = arm720t_init_target,
 588         .examine = arm7_9_examine,
 589         .check_reset = arm7_9_check_reset,
 590 };