1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007 by Vincent Palatin *
6 * vincent.palatin_openocd@m4x.org *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
31 /* ETM registers (JTAG protocol) */
36 ETM_TRIG_EVENT
= 0x02,
39 ETM_SYS_CONFIG
= 0x05,
40 ETM_TRACE_RESOURCE_CTRL
= 0x06,
41 ETM_TRACE_EN_CTRL2
= 0x07,
42 ETM_TRACE_EN_EVENT
= 0x08,
43 ETM_TRACE_EN_CTRL1
= 0x09,
44 /* optional FIFOFULL */
45 ETM_FIFOFULL_REGION
= 0x0a,
46 ETM_FIFOFULL_LEVEL
= 0x0b,
47 /* viewdata support */
48 ETM_VIEWDATA_EVENT
= 0x0c,
49 ETM_VIEWDATA_CTRL1
= 0x0d,
50 ETM_VIEWDATA_CTRL2
= 0x0e, /* optional */
51 ETM_VIEWDATA_CTRL3
= 0x0f,
52 /* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
53 ETM_ADDR_COMPARATOR_VALUE
= 0x10,
54 ETM_ADDR_ACCESS_TYPE
= 0x20,
55 /* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
56 ETM_DATA_COMPARATOR_VALUE
= 0x30,
57 ETM_DATA_COMPARATOR_MASK
= 0x40,
58 /* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
59 ETM_COUNTER_RELOAD_VALUE
= 0x50,
60 ETM_COUNTER_ENABLE
= 0x54,
61 ETM_COUNTER_RELOAD_EVENT
= 0x58,
62 ETM_COUNTER_VALUE
= 0x5c,
63 /* 6 sequencer event transitions */
64 ETM_SEQUENCER_EVENT
= 0x60,
65 ETM_SEQUENCER_STATE
= 0x67,
66 /* N triggered outputs */
67 ETM_EXTERNAL_OUTPUT
= 0x68,
69 ETM_CONTEXTID_COMPARATOR_VALUE
= 0x6c,
70 ETM_CONTEXTID_COMPARATOR_MASK
= 0x6f,
77 const struct etm_reg_info
*reg_info
;
78 struct arm_jtag
*jtag_info
;
81 /* Subset of ETM_CTRL bit assignments. Many of these
82 * control the configuration of trace output, which
83 * hooks up either to ETB or to an external device.
85 * NOTE that these have evolved since the ~v1.3 defns ...
89 ETM_CTRL_POWERDOWN
= (1 << 0),
90 ETM_CTRL_MONITOR_CPRT
= (1 << 1),
92 // bits 3:2 == trace type (ETMV1_TRACE_* << 2)
94 /* Port width (bits 21 and 6:4) */
97 ETM_PORT_16BIT
= 0x20,
98 ETM_PORT_24BIT
= 0x30,
99 ETM_PORT_32BIT
= 0x40,
100 ETM_PORT_48BIT
= 0x50,
101 ETM_PORT_64BIT
= 0x60,
102 ETM_PORT_1BIT
= 0x00 | (1 << 21),
103 ETM_PORT_2BIT
= 0x10 | (1 << 21),
104 ETM_PORT_WIDTH_MASK
= 0x70 | (1 << 21),
106 ETM_CTRL_FIFOFULL_STALL
= (1 << 7),
107 ETM_CTRL_BRANCH_OUTPUT
= (1 << 8),
108 ETM_CTRL_DBGRQ
= (1 << 9),
109 ETM_CTRL_ETM_PROG
= (1 << 10),
110 ETM_CTRL_ETMEN
= (1 << 11),
111 ETM_CTRL_CYCLE_ACCURATE
= (1 << 12),
113 /* Clocking modes -- up to v2.1, bit 13 */
114 ETM_PORT_FULL_CLOCK
= (0 << 13),
115 ETM_PORT_HALF_CLOCK
= (1 << 13),
116 ETM_PORT_CLOCK_MASK
= (1 << 13),
118 // bits 15:14 == context ID size used in tracing
119 // ETMV1_CONTEXTID_* << 8
121 /* Port modes -- bits 17:16, tied to clocking mode */
122 ETM_PORT_NORMAL
= (0 << 16),
123 ETM_PORT_MUXED
= (1 << 16),
124 ETM_PORT_DEMUXED
= (2 << 16),
125 ETM_PORT_MODE_MASK
= (3 << 16),
127 // bits 31:18 defined in v3.0 and later (e.g. ARM11+)
133 ETMV1_TRACE_NONE
= 0x00,
134 ETMV1_TRACE_DATA
= 0x01,
135 ETMV1_TRACE_ADDR
= 0x02,
136 ETMV1_TRACE_MASK
= 0x03,
138 ETMV1_CONTEXTID_NONE
= 0x00,
139 ETMV1_CONTEXTID_8
= 0x10,
140 ETMV1_CONTEXTID_16
= 0x20,
141 ETMV1_CONTEXTID_32
= 0x30,
142 ETMV1_CONTEXTID_MASK
= 0x30,
144 ETMV1_CYCLE_ACCURATE
= 0x100,
145 ETMV1_BRANCH_OUTPUT
= 0x200
148 /* forward-declare ETM context */
151 struct etm_capture_driver
154 const struct command_registration
*commands
;
155 int (*init
)(struct etm_context
*etm_ctx
);
156 trace_status_t (*status
)(struct etm_context
*etm_ctx
);
157 int (*read_trace
)(struct etm_context
*etm_ctx
);
158 int (*start_capture
)(struct etm_context
*etm_ctx
);
159 int (*stop_capture
)(struct etm_context
*etm_ctx
);
164 ETMV1_TRACESYNC_CYCLE
= 0x1,
165 ETMV1_TRIGGER_CYCLE
= 0x2,
168 struct etmv1_trace_data
170 uint8_t pipestat
; /* bits 0-2 pipeline status */
171 uint16_t packet
; /* packet data (4, 8 or 16 bit) */
172 int flags
; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
175 /* describe a trace context
176 * if support for ETMv2 or ETMv3 is to be implemented,
177 * this will have to be split into version independent elements
178 * and a version specific part
182 struct target
*target
; /* target this ETM is connected to */
183 struct reg_cache
*reg_cache
; /* ETM register cache */
184 struct etm_capture_driver
*capture_driver
; /* driver used to access ETM data */
185 void *capture_driver_priv
; /* capture driver private data */
186 trace_status_t capture_status
; /* current state of capture run */
187 struct etmv1_trace_data
*trace_data
; /* trace data */
188 uint32_t trace_depth
; /* number of cycles to be analyzed, 0 if no data available */
189 uint32_t control
; /* shadow of ETM_CTRL */
190 uint32_t tracemode
; /* type of info trace contains */
191 int /*arm_state*/ core_state
; /* current core state */
192 struct image
*image
; /* source for target opcodes */
193 uint32_t pipe_index
; /* current trace cycle */
194 uint32_t data_index
; /* cycle holding next data packet */
195 bool data_half
; /* port half on a 16 bit port */
196 bool pc_ok
; /* full PC has been acquired */
197 bool ptr_ok
; /* whether last_ptr is valid */
198 uint8_t bcd_vers
; /* e.g. 0x13 == ETMv1.3 */
199 uint32_t config
; /* cache of ETM_CONFIG value */
200 uint32_t id
; /* cache of ETM_ID value, or 0 */
201 uint32_t current_pc
; /* current program counter */
202 uint32_t last_branch
; /* last branch address output */
203 uint32_t last_branch_reason
; /* type of last branch encountered */
204 uint32_t last_ptr
; /* address of the last data access */
205 uint32_t last_instruction
; /* index of last executed (to calc timings) */
208 /* PIPESTAT values */
221 /* branch reason values */
224 BR_NORMAL
= 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
225 BR_ENABLE
= 0x1, /* Trace has been enabled */
226 BR_RESTART
= 0x2, /* Trace restarted after a FIFO overflow */
227 BR_NODEBUG
= 0x3, /* ARM has exited for debug state */
228 BR_PERIOD
= 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
229 BR_RSVD5
= 0x5, /* reserved */
230 BR_RSVD6
= 0x6, /* reserved */
231 BR_RSVD7
= 0x7, /* reserved */
232 } etmv1_branch_reason_t
;
234 struct reg_cache
* etm_build_reg_cache(struct target
*target
,
235 struct arm_jtag
*jtag_info
, struct etm_context
*etm_ctx
);
237 int etm_setup(struct target
*target
);
239 extern const struct command_registration etm_command_handlers
[];
241 #define ERROR_ETM_INVALID_DRIVER (-1300)
242 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
243 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
244 #define ERROR_ETM_ANALYSIS_FAILED (-1303)