Fw: [PATCH] OpenRD board configuration
[openocd/cortex.git] / src / target / armv4_5_mmu.c
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1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
24 #include "log.h"
25 #include "armv4_5_mmu.h"
28 uint32_t armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
30 char* armv4_5_mmu_page_type_names[] =
32 "section", "large page", "small page", "tiny page"
35 uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
37 uint32_t first_lvl_descriptor = 0x0;
38 uint32_t second_lvl_descriptor = 0x0;
39 uint32_t ttb = armv4_5_mmu->get_ttb(target);
41 armv4_5_mmu_read_physical(target, armv4_5_mmu,
42 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
43 4, 1, (uint8_t*)&first_lvl_descriptor);
44 first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
46 LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
48 if ((first_lvl_descriptor & 0x3) == 0)
50 *type = -1;
51 LOG_ERROR("Address translation failure");
52 return ERROR_TARGET_TRANSLATION_FAULT;
55 if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
57 *type = -1;
58 LOG_ERROR("Address translation failure");
59 return ERROR_TARGET_TRANSLATION_FAULT;
62 /* domain is always specified in bits 8-5 */
63 *domain = (first_lvl_descriptor & 0x1e0) >> 5;
65 if ((first_lvl_descriptor & 0x3) == 2)
67 /* section descriptor */
68 *type = ARMV4_5_SECTION;
69 *cb = (first_lvl_descriptor & 0xc) >> 2;
70 *ap = (first_lvl_descriptor & 0xc00) >> 10;
71 return (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
74 if ((first_lvl_descriptor & 0x3) == 1)
76 /* coarse page table */
77 armv4_5_mmu_read_physical(target, armv4_5_mmu,
78 (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
79 4, 1, (uint8_t*)&second_lvl_descriptor);
81 else if ((first_lvl_descriptor & 0x3) == 3)
83 /* fine page table */
84 armv4_5_mmu_read_physical(target, armv4_5_mmu,
85 (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
86 4, 1, (uint8_t*)&second_lvl_descriptor);
89 second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
91 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
93 if ((second_lvl_descriptor & 0x3) == 0)
95 *type = -1;
96 LOG_ERROR("Address translation failure");
97 return ERROR_TARGET_TRANSLATION_FAULT;
100 /* cacheable/bufferable is always specified in bits 3-2 */
101 *cb = (second_lvl_descriptor & 0xc) >> 2;
103 if ((second_lvl_descriptor & 0x3) == 1)
105 /* large page descriptor */
106 *type = ARMV4_5_LARGE_PAGE;
107 *ap = (second_lvl_descriptor & 0xff0) >> 4;
108 return (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
111 if ((second_lvl_descriptor & 0x3) == 2)
113 /* small page descriptor */
114 *type = ARMV4_5_SMALL_PAGE;
115 *ap = (second_lvl_descriptor & 0xff0) >> 4;
116 return (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
119 if ((second_lvl_descriptor & 0x3) == 3)
121 /* tiny page descriptor */
122 *type = ARMV4_5_TINY_PAGE;
123 *ap = (second_lvl_descriptor & 0x30) >> 4;
124 return (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
127 /* should not happen */
128 *type = -1;
129 LOG_ERROR("Address translation failure");
130 return ERROR_TARGET_TRANSLATION_FAULT;
133 int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
135 int retval;
137 if (target->state != TARGET_HALTED)
138 return ERROR_TARGET_NOT_HALTED;
140 /* disable MMU and data (or unified) cache */
141 armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
143 retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
145 /* reenable MMU / cache */
146 armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
147 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
148 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
150 return retval;
153 int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
155 int retval;
157 if (target->state != TARGET_HALTED)
158 return ERROR_TARGET_NOT_HALTED;
160 /* disable MMU and data (or unified) cache */
161 armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
163 retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
165 /* reenable MMU / cache */
166 armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
167 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
168 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
170 return retval;
173 int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
175 uint32_t va;
176 uint32_t pa;
177 int type;
178 uint32_t cb;
179 int domain;
180 uint32_t ap;
182 if (target->state != TARGET_HALTED)
184 command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command");
185 return ERROR_OK;
188 if (argc == 0)
190 command_print(cmd_ctx, "usage: virt2phys <virtual address>");
191 return ERROR_OK;
194 if (argc == 1)
196 va = strtoul(args[0], NULL, 0);
197 pa = armv4_5_mmu_translate_va(target, armv4_5_mmu, va, &type, &cb, &domain, &ap);
198 if (type == -1)
200 switch (pa)
202 case ERROR_TARGET_TRANSLATION_FAULT:
203 command_print(cmd_ctx, "no valid translation for 0x%8.8" PRIx32 "", va);
204 break;
205 default:
206 command_print(cmd_ctx, "unknown translation error");
208 return ERROR_OK;
211 command_print(cmd_ctx, "0x%8.8" PRIx32 " -> 0x%8.8" PRIx32 ", type: %s, cb: %i, domain: %d, ap: %2.2x",
212 va, pa, armv4_5_mmu_page_type_names[type], (int)cb, domain, (int)ap);
215 return ERROR_OK;
218 int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
220 int count = 1;
221 int size = 4;
222 uint32_t address = 0;
223 int i;
225 char output[128];
226 int output_len;
228 int retval;
230 uint8_t *buffer;
232 if (target->state != TARGET_HALTED)
234 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
235 return ERROR_OK;
238 if (argc < 1)
239 return ERROR_OK;
241 if (argc == 2)
242 count = strtoul(args[1], NULL, 0);
244 address = strtoul(args[0], NULL, 0);
246 switch (cmd[2])
248 case 'w':
249 size = 4;
250 break;
251 case 'h':
252 size = 2;
253 break;
254 case 'b':
255 size = 1;
256 break;
257 default:
258 return ERROR_OK;
261 buffer = calloc(count, size);
262 if ((retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK)
264 switch (retval)
266 case ERROR_TARGET_UNALIGNED_ACCESS:
267 command_print(cmd_ctx, "error: address not aligned");
268 break;
269 case ERROR_TARGET_NOT_HALTED:
270 command_print(cmd_ctx, "error: target must be halted for memory accesses");
271 break;
272 case ERROR_TARGET_DATA_ABORT:
273 command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
274 break;
275 default:
276 command_print(cmd_ctx, "error: unknown error");
280 output_len = 0;
282 for (i = 0; i < count; i++)
284 if (i%8 == 0)
285 output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8" PRIx32 ": ", address + (i*size));
287 switch (size)
289 case 4:
290 output_len += snprintf(output + output_len, 128 - output_len, "%8.8" PRIx32 " ", target_buffer_get_u32(target, &buffer[i*4]));
291 break;
292 case 2:
293 output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));
294 break;
295 case 1:
296 output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]);
297 break;
300 if ((i % 8 == 7) || (i == count - 1))
302 command_print(cmd_ctx, "%s", output);
303 output_len = 0;
307 free(buffer);
309 return ERROR_OK;
312 int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
314 uint32_t address = 0;
315 uint32_t value = 0;
316 int retval;
317 uint8_t value_buf[4];
319 if (target->state != TARGET_HALTED)
321 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
322 return ERROR_OK;
325 if (argc < 2)
326 return ERROR_OK;
328 address = strtoul(args[0], NULL, 0);
329 value = strtoul(args[1], NULL, 0);
331 switch (cmd[2])
333 case 'w':
334 target_buffer_set_u32(target, value_buf, value);
335 retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf);
336 break;
337 case 'h':
338 target_buffer_set_u16(target, value_buf, value);
339 retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf);
340 break;
341 case 'b':
342 value_buf[0] = value;
343 retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf);
344 break;
345 default:
346 return ERROR_OK;
349 switch (retval)
351 case ERROR_TARGET_UNALIGNED_ACCESS:
352 command_print(cmd_ctx, "error: address not aligned");
353 break;
354 case ERROR_TARGET_DATA_ABORT:
355 command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
356 break;
357 case ERROR_TARGET_NOT_HALTED:
358 command_print(cmd_ctx, "error: target must be halted for memory accesses");
359 break;
360 case ERROR_OK:
361 break;
362 default:
363 command_print(cmd_ctx, "error: unknown error");
366 return ERROR_OK;