1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
30 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
32 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D *
33 * Cortex-M3(tm) TRM, ARM DDI 0337G *
35 ***************************************************************************/
41 #include "arm_adi_v5.h"
42 #include "time_support.h"
46 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
47 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
48 * result checking until swjdp_end_transaction()
49 * This must be done before using or deallocating any return variables.
50 * swjdp->trans_mode == TRANS_MODE_ATOMIC
51 * All reads and writes to the AHB bus are checked for valid completion, and return values
52 * are immediatley available.
56 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
59 uint32_t tar_block_size(uint32_t address)
60 Return the largest block starting at address that does not cross a tar block size alignment boundary
62 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
64 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
67 /***************************************************************************
69 * DPACC and APACC scanchain access through JTAG-DP *
71 ***************************************************************************/
73 /* Scan out and in from target ordered uint8_t buffers */
74 int adi_jtag_dp_scan(swjdp_common_t
*swjdp
, uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
, uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
76 arm_jtag_t
*jtag_info
= swjdp
->jtag_info
;
77 scan_field_t fields
[2];
80 jtag_set_end_state(TAP_IDLE
);
81 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
83 /* Add specified number of tck clocks before accessing memory bus */
84 if ((instr
== DAP_IR_APACC
) && ((reg_addr
== AP_REG_DRW
)||((reg_addr
&0xF0) == AP_REG_BD0
))&& (swjdp
->memaccess_tck
!= 0))
85 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
87 fields
[0].tap
= jtag_info
->tap
;
88 fields
[0].num_bits
= 3;
89 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
90 fields
[0].out_value
= &out_addr_buf
;
91 fields
[0].in_value
= ack
;
93 fields
[1].tap
= jtag_info
->tap
;
94 fields
[1].num_bits
= 32;
95 fields
[1].out_value
= outvalue
;
96 fields
[1].in_value
= invalue
;
98 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
103 /* Scan out and in from host ordered uint32_t variables */
104 int adi_jtag_dp_scan_u32(swjdp_common_t
*swjdp
, uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
, uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
106 arm_jtag_t
*jtag_info
= swjdp
->jtag_info
;
107 scan_field_t fields
[2];
108 uint8_t out_value_buf
[4];
109 uint8_t out_addr_buf
;
111 jtag_set_end_state(TAP_IDLE
);
112 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
114 /* Add specified number of tck clocks before accessing memory bus */
115 if ((instr
== DAP_IR_APACC
) && ((reg_addr
== AP_REG_DRW
)||((reg_addr
&0xF0) == AP_REG_BD0
))&& (swjdp
->memaccess_tck
!= 0))
116 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
118 fields
[0].tap
= jtag_info
->tap
;
119 fields
[0].num_bits
= 3;
120 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
121 fields
[0].out_value
= &out_addr_buf
;
122 fields
[0].in_value
= ack
;
124 fields
[1].tap
= jtag_info
->tap
;
125 fields
[1].num_bits
= 32;
126 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
127 fields
[1].out_value
= out_value_buf
;
128 fields
[1].in_value
= NULL
;
132 fields
[1].in_value
= (uint8_t *)invalue
;
133 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
135 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
) invalue
);
139 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
145 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
146 int scan_inout_check(swjdp_common_t
*swjdp
, uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
, uint8_t *outvalue
, uint8_t *invalue
)
148 adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
150 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
152 adi_jtag_dp_scan(swjdp
, DAP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
155 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
156 if ((instr
== DAP_IR_APACC
) && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
158 return swjdp_transaction_endcheck(swjdp
);
164 int scan_inout_check_u32(swjdp_common_t
*swjdp
, uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
, uint32_t outvalue
, uint32_t *invalue
)
166 adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
168 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
170 adi_jtag_dp_scan_u32(swjdp
, DAP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
173 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
174 if ((instr
== DAP_IR_APACC
) && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
176 return swjdp_transaction_endcheck(swjdp
);
182 int swjdp_transaction_endcheck(swjdp_common_t
*swjdp
)
187 /* too expensive to call keep_alive() here */
190 /* Danger!!!! BROKEN!!!! */
191 scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
192 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
193 R956 introduced the check on return value here and now Michael Schwingen reports
194 that this code no longer works....
196 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
198 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
200 LOG_ERROR("BUG: Why does this fail the first time????");
202 /* Why??? second time it works??? */
205 scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
206 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
209 swjdp
->ack
= swjdp
->ack
& 0x7;
213 long long then
= timeval_ms();
214 while (swjdp
->ack
!= 2)
218 if ((timeval_ms()-then
) > 1000)
220 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
221 return ERROR_JTAG_DEVICE_ERROR
;
226 LOG_WARNING("Invalid ACK in SWJDP transaction");
227 return ERROR_JTAG_DEVICE_ERROR
;
230 scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
231 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
233 swjdp
->ack
= swjdp
->ack
& 0x7;
237 /* common code path avoids fn to timeval_ms() */
240 /* Check for STICKYERR and STICKYORUN */
241 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
243 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32
"", ctrlstat
);
244 /* Check power to debug regions */
245 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
247 ahbap_debugport_init(swjdp
);
251 uint32_t mem_ap_csw
, mem_ap_tar
;
253 /* Print information about last AHBAP access */
254 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
", ap_csw 0x%" PRIx32
", ap_tar 0x%" PRIx32
"", swjdp
->dp_select_value
, swjdp
->ap_csw_value
, swjdp
->ap_tar_value
);
255 if (ctrlstat
& SSTICKYORUN
)
256 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
258 if (ctrlstat
& SSTICKYERR
)
259 LOG_ERROR("SWJ-DP STICKY ERROR");
261 /* Clear Sticky Error Bits */
262 scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, DP_CTRL_STAT
, DPAP_WRITE
, swjdp
->dp_ctrl_stat
| SSTICKYORUN
| SSTICKYERR
, NULL
);
263 scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
264 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
267 LOG_DEBUG("swjdp: status 0x%" PRIx32
"", ctrlstat
);
269 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
270 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
271 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
273 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%" PRIx32
"", mem_ap_csw
, mem_ap_tar
);
276 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
278 return ERROR_JTAG_DEVICE_ERROR
;
284 /***************************************************************************
286 * DP and MEM-AP register access through APACC and DPACC *
288 ***************************************************************************/
290 int dap_dp_write_reg(swjdp_common_t
*swjdp
, uint32_t value
, uint8_t reg_addr
)
292 return scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, reg_addr
, DPAP_WRITE
, value
, NULL
);
295 int dap_dp_read_reg(swjdp_common_t
*swjdp
, uint32_t *value
, uint8_t reg_addr
)
297 return scan_inout_check_u32(swjdp
, DAP_IR_DPACC
, reg_addr
, DPAP_READ
, 0, value
);
300 int dap_ap_select(swjdp_common_t
*swjdp
,uint8_t apsel
)
303 select
= (apsel
<< 24) & 0xFF000000;
305 if (select
!= swjdp
->apsel
)
307 swjdp
->apsel
= select
;
308 /* Switching AP invalidates cached values */
309 swjdp
->dp_select_value
= -1;
310 swjdp
->ap_csw_value
= -1;
311 swjdp
->ap_tar_value
= -1;
317 int dap_dp_bankselect(swjdp_common_t
*swjdp
,uint32_t ap_reg
)
320 select
= (ap_reg
& 0x000000F0);
322 if (select
!= swjdp
->dp_select_value
)
324 dap_dp_write_reg(swjdp
, select
| swjdp
->apsel
, DP_SELECT
);
325 swjdp
->dp_select_value
= select
;
331 int dap_ap_write_reg(swjdp_common_t
*swjdp
, uint32_t reg_addr
, uint8_t* out_value_buf
)
333 dap_dp_bankselect(swjdp
, reg_addr
);
334 scan_inout_check(swjdp
, DAP_IR_APACC
, reg_addr
, DPAP_WRITE
, out_value_buf
, NULL
);
339 int dap_ap_read_reg(swjdp_common_t
*swjdp
, uint32_t reg_addr
, uint8_t *in_value_buf
)
341 dap_dp_bankselect(swjdp
, reg_addr
);
342 scan_inout_check(swjdp
, DAP_IR_APACC
, reg_addr
, DPAP_READ
, 0, in_value_buf
);
346 int dap_ap_write_reg_u32(swjdp_common_t
*swjdp
, uint32_t reg_addr
, uint32_t value
)
348 uint8_t out_value_buf
[4];
350 buf_set_u32(out_value_buf
, 0, 32, value
);
351 dap_dp_bankselect(swjdp
, reg_addr
);
352 scan_inout_check(swjdp
, DAP_IR_APACC
, reg_addr
, DPAP_WRITE
, out_value_buf
, NULL
);
357 int dap_ap_read_reg_u32(swjdp_common_t
*swjdp
, uint32_t reg_addr
, uint32_t *value
)
359 dap_dp_bankselect(swjdp
, reg_addr
);
360 scan_inout_check_u32(swjdp
, DAP_IR_APACC
, reg_addr
, DPAP_READ
, 0, value
);
365 /***************************************************************************
367 * AHB-AP access to memory and system registers on AHB bus *
369 ***************************************************************************/
371 int dap_setup_accessport(swjdp_common_t
*swjdp
, uint32_t csw
, uint32_t tar
)
373 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
374 if (csw
!= swjdp
->ap_csw_value
)
376 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
377 dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
378 swjdp
->ap_csw_value
= csw
;
380 if (tar
!= swjdp
->ap_tar_value
)
382 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
383 dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
384 swjdp
->ap_tar_value
= tar
;
386 if (csw
& CSW_ADDRINC_MASK
)
388 /* Do not cache TAR value when autoincrementing */
389 swjdp
->ap_tar_value
= -1;
394 /*****************************************************************************
396 * mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) *
398 * Read a uint32_t value from memory or system register *
399 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
400 * but with less overhead *
401 *****************************************************************************/
402 int mem_ap_read_u32(swjdp_common_t
*swjdp
, uint32_t address
, uint32_t *value
)
404 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
406 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
407 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
412 int mem_ap_read_atomic_u32(swjdp_common_t
*swjdp
, uint32_t address
, uint32_t *value
)
414 mem_ap_read_u32(swjdp
, address
, value
);
416 return swjdp_transaction_endcheck(swjdp
);
419 /*****************************************************************************
421 * mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) *
423 * Write a uint32_t value to memory or memory mapped register *
425 *****************************************************************************/
426 int mem_ap_write_u32(swjdp_common_t
*swjdp
, uint32_t address
, uint32_t value
)
428 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
430 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
431 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
436 int mem_ap_write_atomic_u32(swjdp_common_t
*swjdp
, uint32_t address
, uint32_t value
)
438 mem_ap_write_u32(swjdp
, address
, value
);
440 return swjdp_transaction_endcheck(swjdp
);
443 /*****************************************************************************
445 * mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) *
447 * Write a buffer in target order (little endian) *
449 *****************************************************************************/
450 int mem_ap_write_buf_u32(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
452 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
453 uint32_t adr
= address
;
454 uint8_t* pBuffer
= buffer
;
456 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
461 /* if we have an unaligned access - reorder data */
464 for (writecount
= 0; writecount
< count
; writecount
++)
468 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
470 for (i
= 0; i
< 4; i
++)
472 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
476 pBuffer
+= sizeof(uint32_t);
482 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
483 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
484 if (wcount
< blocksize
)
487 /* handle unaligned data at 4k boundary */
491 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
493 for (writecount
= 0; writecount
< blocksize
; writecount
++)
495 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
498 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
500 wcount
= wcount
- blocksize
;
501 address
= address
+ 4 * blocksize
;
502 buffer
= buffer
+ 4 * blocksize
;
511 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
512 return ERROR_JTAG_DEVICE_ERROR
;
519 int mem_ap_write_buf_packed_u16(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
521 int retval
= ERROR_OK
;
522 int wcount
, blocksize
, writecount
, i
;
524 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
532 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
533 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
535 if (wcount
< blocksize
)
538 /* handle unaligned data at 4k boundary */
542 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
543 writecount
= blocksize
;
547 nbytes
= MIN((writecount
<< 1), 4);
551 if (mem_ap_write_buf_u16(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
553 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
554 return ERROR_JTAG_DEVICE_ERROR
;
557 address
+= nbytes
>> 1;
562 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
564 for (i
= 0; i
< nbytes
; i
++)
566 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
571 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
572 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
573 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
575 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
576 return ERROR_JTAG_DEVICE_ERROR
;
580 buffer
+= nbytes
>> 1;
581 writecount
-= nbytes
>> 1;
583 } while (writecount
);
590 int mem_ap_write_buf_u16(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
592 int retval
= ERROR_OK
;
595 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
597 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
601 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
603 memcpy(&svalue
, buffer
, sizeof(uint16_t));
604 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
605 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
606 retval
= swjdp_transaction_endcheck(swjdp
);
615 int mem_ap_write_buf_packed_u8(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
617 int retval
= ERROR_OK
;
618 int wcount
, blocksize
, writecount
, i
;
620 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
628 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
629 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
631 if (wcount
< blocksize
)
634 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
635 writecount
= blocksize
;
639 nbytes
= MIN(writecount
, 4);
643 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
645 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
646 return ERROR_JTAG_DEVICE_ERROR
;
654 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
656 for (i
= 0; i
< nbytes
; i
++)
658 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
663 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
664 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
665 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
667 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
668 return ERROR_JTAG_DEVICE_ERROR
;
673 writecount
-= nbytes
;
675 } while (writecount
);
682 int mem_ap_write_buf_u8(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
684 int retval
= ERROR_OK
;
687 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
689 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
693 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
694 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
695 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
696 retval
= swjdp_transaction_endcheck(swjdp
);
705 /*********************************************************************************
707 * mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) *
709 * Read block fast in target order (little endian) into a buffer *
711 **********************************************************************************/
712 int mem_ap_read_buf_u32(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
714 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
715 uint32_t adr
= address
;
716 uint8_t* pBuffer
= buffer
;
718 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
725 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
726 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
727 if (wcount
< blocksize
)
730 /* handle unaligned data at 4k boundary */
734 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
736 /* Scan out first read */
737 adi_jtag_dp_scan(swjdp
, DAP_IR_APACC
, AP_REG_DRW
, DPAP_READ
, 0, NULL
, NULL
);
738 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
740 /* Scan out read instruction and scan in previous value */
741 adi_jtag_dp_scan(swjdp
, DAP_IR_APACC
, AP_REG_DRW
, DPAP_READ
, 0, buffer
+ 4 * readcount
, &swjdp
->ack
);
744 /* Scan in last value */
745 adi_jtag_dp_scan(swjdp
, DAP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, buffer
+ 4 * readcount
, &swjdp
->ack
);
746 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
748 wcount
= wcount
- blocksize
;
749 address
+= 4 * blocksize
;
750 buffer
+= 4 * blocksize
;
759 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
760 return ERROR_JTAG_DEVICE_ERROR
;
764 /* if we have an unaligned access - reorder data */
767 for (readcount
= 0; readcount
< count
; readcount
++)
771 memcpy(&data
, pBuffer
, sizeof(uint32_t));
773 for (i
= 0; i
< 4; i
++)
775 *((uint8_t*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
785 int mem_ap_read_buf_packed_u16(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
788 int retval
= ERROR_OK
;
789 int wcount
, blocksize
, readcount
, i
;
791 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
799 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
800 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
801 if (wcount
< blocksize
)
804 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
806 /* handle unaligned data at 4k boundary */
809 readcount
= blocksize
;
813 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
814 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
816 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
817 return ERROR_JTAG_DEVICE_ERROR
;
820 nbytes
= MIN((readcount
<< 1), 4);
822 for (i
= 0; i
< nbytes
; i
++)
824 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
829 readcount
-= (nbytes
>> 1);
837 int mem_ap_read_buf_u16(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
840 int retval
= ERROR_OK
;
843 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
845 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
849 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
850 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
851 retval
= swjdp_transaction_endcheck(swjdp
);
854 for (i
= 0; i
< 2; i
++)
856 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
863 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
864 memcpy(buffer
, &svalue
, sizeof(uint16_t));
874 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
875 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
877 * The solution is to arrange for a large out/in scan in this loop and
878 * and convert data afterwards.
880 int mem_ap_read_buf_packed_u8(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
883 int retval
= ERROR_OK
;
884 int wcount
, blocksize
, readcount
, i
;
886 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
894 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
895 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
897 if (wcount
< blocksize
)
900 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
901 readcount
= blocksize
;
905 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
906 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
908 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
909 return ERROR_JTAG_DEVICE_ERROR
;
912 nbytes
= MIN(readcount
, 4);
914 for (i
= 0; i
< nbytes
; i
++)
916 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
929 int mem_ap_read_buf_u8(swjdp_common_t
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
932 int retval
= ERROR_OK
;
935 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
937 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
941 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
942 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
943 retval
= swjdp_transaction_endcheck(swjdp
);
944 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
953 int ahbap_debugport_init(swjdp_common_t
*swjdp
)
955 uint32_t idreg
, romaddr
, dummy
;
963 swjdp
->ap_csw_value
= -1;
964 swjdp
->ap_tar_value
= -1;
965 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
966 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
967 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
968 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
970 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
972 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
973 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
974 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
977 /* Check that we have debug power domains activated */
978 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
980 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
981 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
982 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
987 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
989 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
990 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
991 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
996 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
997 /* With debug power on we can activate OVERRUN checking */
998 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
999 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1000 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1002 dap_ap_read_reg_u32(swjdp
, 0xFC, &idreg
);
1003 dap_ap_read_reg_u32(swjdp
, 0xF8, &romaddr
);
1005 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32
"", idreg
, romaddr
);
1011 char * class_description
[16] ={
1013 "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
1014 "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
1016 int dap_info_command(struct command_context_s
*cmd_ctx
, swjdp_common_t
*swjdp
, int apsel
)
1019 uint32_t dbgbase
,apid
;
1020 int romtable_present
= 0;
1024 apselold
= swjdp
->apsel
;
1025 dap_ap_select(swjdp
, apsel
);
1026 dap_ap_read_reg_u32(swjdp
, 0xF8, &dbgbase
);
1027 dap_ap_read_reg_u32(swjdp
, 0xFC, &apid
);
1028 swjdp_transaction_endcheck(swjdp
);
1029 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1030 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1031 command_print(cmd_ctx
, "ap identification register 0x%8.8" PRIx32
"", apid
);
1037 command_print(cmd_ctx
, "\tType is jtag-ap");
1040 command_print(cmd_ctx
, "\tType is mem-ap AHB");
1043 command_print(cmd_ctx
, "\tType is mem-ap APB");
1046 command_print(cmd_ctx
, "\tUnknown AP-type");
1049 command_print(cmd_ctx
, "ap debugbase 0x%8.8" PRIx32
"", dbgbase
);
1053 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1056 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1057 if (romtable_present
)
1059 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1060 uint16_t entry_offset
;
1061 /* bit 16 of apid indicates a memory access port */
1064 command_print(cmd_ctx
, "\tValid ROM table present");
1068 command_print(cmd_ctx
, "\tROM table in legacy format");
1070 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1071 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1072 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1073 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1074 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1075 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1076 swjdp_transaction_endcheck(swjdp
);
1077 command_print(cmd_ctx
, "\tCID3 0x%" PRIx32
", CID2 0x%" PRIx32
", CID1 0x%" PRIx32
" CID0, 0x%" PRIx32
,cid3
,cid2
,cid1
,cid0
);
1080 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1084 command_print(cmd_ctx
, "\tMEMTYPE system memory not present. Dedicated debug bus");
1087 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1091 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1092 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1095 uint32_t c_cid0
,c_cid1
,c_cid2
,c_cid3
,c_pid0
,c_pid1
,c_pid2
,c_pid3
,c_pid4
,component_start
;
1096 uint32_t component_base
= (uint32_t)((dbgbase
&0xFFFFF000) + (int)(romentry
&0xFFFFF000));
1097 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFE0, &c_pid0
);
1098 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFE4, &c_pid1
);
1099 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFE8, &c_pid2
);
1100 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFEC, &c_pid3
);
1101 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFD0, &c_pid4
);
1102 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFF0, &c_cid0
);
1103 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFF4, &c_cid1
);
1104 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFF8, &c_cid2
);
1105 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000) | 0xFFC, &c_cid3
);
1106 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1107 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
", pid4 0x%" PRIx32
", start address 0x%" PRIx32
"",component_base
,c_pid4
,component_start
);
1108 command_print(cmd_ctx
, "\t\tComponent cid1 0x%" PRIx32
", class is %s",c_cid1
,class_description
[(c_cid1
>> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
1109 command_print(cmd_ctx
, "\t\tCID3 0x%" PRIx32
", CID2 0x%" PRIx32
", CID1 0x%" PRIx32
", CID0, 0x%" PRIx32
"",c_cid3
,c_cid2
,c_cid1
,c_cid0
);
1110 command_print(cmd_ctx
, "\t\tPID3 0x%" PRIx32
", PID2 0x%" PRIx32
", PID1 0x%" PRIx32
", PID0, 0x%" PRIx32
"",c_pid3
,c_pid2
,c_pid1
,c_pid0
);
1111 /* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */
1116 command_print(cmd_ctx
, "\t\tComponent not present");
1118 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1121 } while (romentry
> 0);
1125 command_print(cmd_ctx
, "\tNo ROM table present");
1127 dap_ap_select(swjdp
, apselold
);
1132 int dap_baseaddr_command(struct command_context_s
*cmd_ctx
,
1133 swjdp_common_t
*swjdp
, char **args
, int argc
)
1135 uint32_t apsel
, apselsave
, baseaddr
;
1138 apsel
= swjdp
->apsel
;
1139 apselsave
= swjdp
->apsel
;
1141 apsel
= strtoul(args
[0], NULL
, 0);
1142 if (apselsave
!= apsel
)
1143 dap_ap_select(swjdp
, apsel
);
1145 dap_ap_read_reg_u32(swjdp
, 0xF8, &baseaddr
);
1146 retval
= swjdp_transaction_endcheck(swjdp
);
1147 command_print(cmd_ctx
, "0x%8.8" PRIx32
, baseaddr
);
1149 if (apselsave
!= apsel
)
1150 dap_ap_select(swjdp
, apselsave
);
1155 int dap_memaccess_command(struct command_context_s
*cmd_ctx
,
1156 swjdp_common_t
*swjdp
, char **args
, int argc
)
1158 uint32_t memaccess_tck
;
1160 memaccess_tck
= swjdp
->memaccess_tck
;
1162 memaccess_tck
= strtoul(args
[0], NULL
, 0);
1164 swjdp
->memaccess_tck
= memaccess_tck
;
1165 command_print(cmd_ctx
, "memory bus access delay set to %" PRIi32
" tck",
1166 swjdp
->memaccess_tck
);
1171 int dap_apsel_command(struct command_context_s
*cmd_ctx
,
1172 swjdp_common_t
*swjdp
, char **args
, int argc
)
1174 uint32_t apsel
, apid
;
1179 apsel
= strtoul(args
[0], NULL
, 0);
1181 dap_ap_select(swjdp
, apsel
);
1182 dap_ap_read_reg_u32(swjdp
, 0xFC, &apid
);
1183 retval
= swjdp_transaction_endcheck(swjdp
);
1184 command_print(cmd_ctx
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1190 int dap_apid_command(struct command_context_s
*cmd_ctx
,
1191 swjdp_common_t
*swjdp
, char **args
, int argc
)
1193 uint32_t apsel
, apselsave
, apid
;
1196 apsel
= swjdp
->apsel
;
1197 apselsave
= swjdp
->apsel
;
1199 apsel
= strtoul(args
[0], NULL
, 0);
1201 if (apselsave
!= apsel
)
1202 dap_ap_select(swjdp
, apsel
);
1204 dap_ap_read_reg_u32(swjdp
, 0xFC, &apid
);
1205 retval
= swjdp_transaction_endcheck(swjdp
);
1206 command_print(cmd_ctx
, "0x%8.8" PRIx32
, apid
);
1207 if (apselsave
!= apsel
)
1208 dap_ap_select(swjdp
, apselsave
);