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Fw: [PATCH] OpenRD board configuration
[openocd/cortex.git] / src / target / arm9tdmi.c
blob8ebb91de39a18cebe32871222e14513814d7474c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Hongtao Zheng *
9 * hontor@126.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "arm9tdmi.h"
31 #include "target_type.h"
32
33
34 /*
35 * NOTE: this holds code that's used with multiple ARM9 processors:
36 * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
37 * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
38 * - ARM9EJS (ARMv5TEJ) ... in ARM926 core
39 *
40 * In short, the file name is a misnomer ... it is NOT specific to
41 * that first generation ARM9 processor, or cores using it.
42 */
43
44 #if 0
45 #define _DEBUG_INSTRUCTION_EXECUTION_
46 #endif
47
48 /* forward declarations */
49 static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp);
50 static int arm9tdmi_quit(void);
51
52 target_type_t arm9tdmi_target =
53 {
54 .name = "arm9tdmi",
55
56 .poll = arm7_9_poll,
57 .arch_state = armv4_5_arch_state,
58
59 .target_request_data = arm7_9_target_request_data,
60
61 .halt = arm7_9_halt,
62 .resume = arm7_9_resume,
63 .step = arm7_9_step,
64
65 .assert_reset = arm7_9_assert_reset,
66 .deassert_reset = arm7_9_deassert_reset,
67 .soft_reset_halt = arm7_9_soft_reset_halt,
68
69 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
70
71 .read_memory = arm7_9_read_memory,
72 .write_memory = arm7_9_write_memory,
73 .bulk_write_memory = arm7_9_bulk_write_memory,
74 .checksum_memory = arm7_9_checksum_memory,
75 .blank_check_memory = arm7_9_blank_check_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm9tdmi_register_commands,
85 .target_create = arm9tdmi_target_create,
86 .init_target = arm9tdmi_init_target,
87 .examine = arm9tdmi_examine,
88 .quit = arm9tdmi_quit
89 };
90
91 static arm9tdmi_vector_t arm9tdmi_vectors[] =
92 {
93 {"reset", ARM9TDMI_RESET_VECTOR},
94 {"undef", ARM9TDMI_UNDEF_VECTOR},
95 {"swi", ARM9TDMI_SWI_VECTOR},
96 {"pabt", ARM9TDMI_PABT_VECTOR},
97 {"dabt", ARM9TDMI_DABT_VECTOR},
98 {"reserved", ARM9TDMI_RESERVED_VECTOR},
99 {"irq", ARM9TDMI_IRQ_VECTOR},
100 {"fiq", ARM9TDMI_FIQ_VECTOR},
101 {0, 0},
102 };
103
104 int arm9tdmi_examine_debug_reason(target_t *target)
105 {
106 int retval = ERROR_OK;
107 /* get pointers to arch-specific information */
108 armv4_5_common_t *armv4_5 = target->arch_info;
109 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
110
111 /* only check the debug reason if we don't know it already */
112 if ((target->debug_reason != DBG_REASON_DBGRQ)
113 && (target->debug_reason != DBG_REASON_SINGLESTEP))
114 {
115 scan_field_t fields[3];
116 uint8_t databus[4];
117 uint8_t instructionbus[4];
118 uint8_t debug_reason;
119
120 jtag_set_end_state(TAP_DRPAUSE);
121
122 fields[0].tap = arm7_9->jtag_info.tap;
123 fields[0].num_bits = 32;
124 fields[0].out_value = NULL;
125 fields[0].in_value = databus;
126
127 fields[1].tap = arm7_9->jtag_info.tap;
128 fields[1].num_bits = 3;
129 fields[1].out_value = NULL;
130 fields[1].in_value = &debug_reason;
131
132 fields[2].tap = arm7_9->jtag_info.tap;
133 fields[2].num_bits = 32;
134 fields[2].out_value = NULL;
135 fields[2].in_value = instructionbus;
136
137 if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
138 {
139 return retval;
140 }
141 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
142
143 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
144 if ((retval = jtag_execute_queue()) != ERROR_OK)
145 {
146 return retval;
147 }
148
149 fields[0].in_value = NULL;
150 fields[0].out_value = databus;
151 fields[1].in_value = NULL;
152 fields[1].out_value = &debug_reason;
153 fields[2].in_value = NULL;
154 fields[2].out_value = instructionbus;
155
156 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
157
158 if (debug_reason & 0x4)
159 if (debug_reason & 0x2)
160 target->debug_reason = DBG_REASON_WPTANDBKPT;
161 else
162 target->debug_reason = DBG_REASON_WATCHPOINT;
163 else
164 target->debug_reason = DBG_REASON_BREAKPOINT;
165 }
166
167 return ERROR_OK;
168 }
169
170 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
171 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
172 {
173 int retval = ERROR_OK;
174 scan_field_t fields[3];
175 uint8_t out_buf[4];
176 uint8_t instr_buf[4];
177 uint8_t sysspeed_buf = 0x0;
178
179 /* prepare buffer */
180 buf_set_u32(out_buf, 0, 32, out);
181
182 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
183
184 if (sysspeed)
185 buf_set_u32(&sysspeed_buf, 2, 1, 1);
186
187 jtag_set_end_state(TAP_DRPAUSE);
188 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
189 {
190 return retval;
191 }
192
193 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
194
195 fields[0].tap = jtag_info->tap;
196 fields[0].num_bits = 32;
197 fields[0].out_value = out_buf;
198 fields[0].in_value = NULL;
199
200 fields[1].tap = jtag_info->tap;
201 fields[1].num_bits = 3;
202 fields[1].out_value = &sysspeed_buf;
203 fields[1].in_value = NULL;
204
205 fields[2].tap = jtag_info->tap;
206 fields[2].num_bits = 32;
207 fields[2].out_value = instr_buf;
208 fields[2].in_value = NULL;
209
210 if (in)
211 {
212 fields[0].in_value = (uint8_t *)in;
213 jtag_add_dr_scan(3, fields, jtag_get_end_state());
214
215 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
216 }
217 else
218 {
219 jtag_add_dr_scan(3, fields, jtag_get_end_state());
220 }
221
222 jtag_add_runtest(0, jtag_get_end_state());
223
224 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
225 {
226 if ((retval = jtag_execute_queue()) != ERROR_OK)
227 {
228 return retval;
229 }
230
231 if (in)
232 {
233 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
234 }
235 else
236 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
237 }
238 #endif
239
240 return ERROR_OK;
241 }
242
243 /* just read data (instruction and data-out = don't care) */
244 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
245 {
246 int retval = ERROR_OK;;
247 scan_field_t fields[3];
248
249 jtag_set_end_state(TAP_DRPAUSE);
250 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
251 {
252 return retval;
253 }
254
255 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
256
257 fields[0].tap = jtag_info->tap;
258 fields[0].num_bits = 32;
259 fields[0].out_value = NULL;
260 fields[0].in_value = (uint8_t *)in;
261
262 fields[1].tap = jtag_info->tap;
263 fields[1].num_bits = 3;
264 fields[1].out_value = NULL;
265 fields[1].in_value = NULL;
266
267 fields[2].tap = jtag_info->tap;
268 fields[2].num_bits = 32;
269 fields[2].out_value = NULL;
270 fields[2].in_value = NULL;
271
272 jtag_add_dr_scan(3, fields, jtag_get_end_state());
273
274 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
275
276 jtag_add_runtest(0, jtag_get_end_state());
277
278 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
279 {
280 if ((retval = jtag_execute_queue()) != ERROR_OK)
281 {
282 return retval;
283 }
284
285 if (in)
286 {
287 LOG_DEBUG("in: 0x%8.8x", *in);
288 }
289 else
290 {
291 LOG_ERROR("BUG: called with in == NULL");
292 }
293 }
294 #endif
295
296 return ERROR_OK;
297 }
298
299 extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
300
301 static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
302 {
303 uint8_t *in = (uint8_t *)arg;
304 arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
305 return ERROR_OK;
306 }
307
308 /* clock the target, and read the databus
309 * the *in pointer points to a buffer where elements of 'size' bytes
310 * are stored in big (be == 1) or little (be == 0) endianness
311 */
312 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
313 {
314 int retval = ERROR_OK;
315 scan_field_t fields[3];
316
317 jtag_set_end_state(TAP_DRPAUSE);
318 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
319 {
320 return retval;
321 }
322
323 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
324
325 fields[0].tap = jtag_info->tap;
326 fields[0].num_bits = 32;
327 fields[0].out_value = NULL;
328 jtag_alloc_in_value32(&fields[0]);
329
330 fields[1].tap = jtag_info->tap;
331 fields[1].num_bits = 3;
332 fields[1].out_value = NULL;
333 fields[1].in_value = NULL;
334
335 fields[2].tap = jtag_info->tap;
336 fields[2].num_bits = 32;
337 fields[2].out_value = NULL;
338 fields[2].in_value = NULL;
339
340 jtag_add_dr_scan(3, fields, jtag_get_end_state());
341
342 jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
343
344 jtag_add_runtest(0, jtag_get_end_state());
345
346 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
347 {
348 if ((retval = jtag_execute_queue()) != ERROR_OK)
349 {
350 return retval;
351 }
352
353 if (in)
354 {
355 LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
356 }
357 else
358 {
359 LOG_ERROR("BUG: called with in == NULL");
360 }
361 }
362 #endif
363
364 return ERROR_OK;
365 }
366
367 static void arm9tdmi_change_to_arm(target_t *target,
368 uint32_t *r0, uint32_t *pc)
369 {
370 int retval = ERROR_OK;
371 /* get pointers to arch-specific information */
372 armv4_5_common_t *armv4_5 = target->arch_info;
373 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
374 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
375
376 /* save r0 before using it and put system in ARM state
377 * to allow common handling of ARM and THUMB debugging */
378
379 /* fetch STR r0, [r0] */
380 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
381 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
382 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
383 /* STR r0, [r0] in Memory */
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
385
386 /* MOV r0, r15 fetched, STR in Decode */
387 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
388 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
390 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
392 /* nothing fetched, STR r0, [r0] in Memory */
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
394
395 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
396 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
397 /* LDR in Decode */
398 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
399 /* LDR in Execute */
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
401 /* LDR in Memory (to account for interlock) */
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
403
404 /* fetch BX */
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
406 /* NOP fetched, BX in Decode, MOV in Execute */
407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
408 /* NOP fetched, BX in Execute (1) */
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
410
411 if ((retval = jtag_execute_queue()) != ERROR_OK)
412 {
413 return;
414 }
415
416 /* fix program counter:
417 * MOV r0, r15 was the 5th instruction (+8)
418 * reading PC in Thumb state gives address of instruction + 4
419 */
420 *pc -= 0xc;
421 }
422
423 void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
424 {
425 int i;
426 /* get pointers to arch-specific information */
427 armv4_5_common_t *armv4_5 = target->arch_info;
428 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
429 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
430
431 /* STMIA r0-15, [r0] at debug speed
432 * register values will start to appear on 4th DCLK
433 */
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
435
436 /* fetch NOP, STM in DECODE stage */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
438 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
440
441 for (i = 0; i <= 15; i++)
442 {
443 if (mask & (1 << i))
444 /* nothing fetched, STM in MEMORY (i'th cycle) */
445 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
446 }
447 }
448
449 static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
450 uint32_t mask, void* buffer, int size)
451 {
452 int i;
453 /* get pointers to arch-specific information */
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
456 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
457 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
458 uint32_t *buf_u32 = buffer;
459 uint16_t *buf_u16 = buffer;
460 uint8_t *buf_u8 = buffer;
461
462 /* STMIA r0-15, [r0] at debug speed
463 * register values will start to appear on 4th DCLK
464 */
465 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
466
467 /* fetch NOP, STM in DECODE stage */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
469 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
470 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
471
472 for (i = 0; i <= 15; i++)
473 {
474 if (mask & (1 << i))
475 /* nothing fetched, STM in MEMORY (i'th cycle) */
476 switch (size)
477 {
478 case 4:
479 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
480 break;
481 case 2:
482 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
483 break;
484 case 1:
485 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
486 break;
487 }
488 }
489 }
490
491 static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
492 {
493 /* get pointers to arch-specific information */
494 armv4_5_common_t *armv4_5 = target->arch_info;
495 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
496 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
497
498 /* MRS r0, cpsr */
499 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
504
505 /* STR r0, [r15] */
506 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
507 /* fetch NOP, STR in DECODE stage */
508 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
509 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
510 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
511 /* nothing fetched, STR in MEMORY */
512 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
513 }
514
515 static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
516 {
517 /* get pointers to arch-specific information */
518 armv4_5_common_t *armv4_5 = target->arch_info;
519 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
520 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
521
522 LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
523
524 /* MSR1 fetched */
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
526 /* MSR2 fetched, MSR1 in DECODE */
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
528 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
530 /* nothing fetched, MSR1 in EXECUTE (2) */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 /* nothing fetched, MSR1 in EXECUTE (3) */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
536 /* nothing fetched, MSR2 in EXECUTE (2) */
537 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
538 /* nothing fetched, MSR2 in EXECUTE (3) */
539 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
540 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
541 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
542 /* nothing fetched, MSR3 in EXECUTE (2) */
543 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
544 /* nothing fetched, MSR3 in EXECUTE (3) */
545 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
546 /* NOP fetched, MSR4 in EXECUTE (1) */
547 /* last MSR writes flags, which takes only one cycle */
548 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
549 }
550
551 static void arm9tdmi_write_xpsr_im8(target_t *target,
552 uint8_t xpsr_im, int rot, int spsr)
553 {
554 /* get pointers to arch-specific information */
555 armv4_5_common_t *armv4_5 = target->arch_info;
556 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
557 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
558
559 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
560
561 /* MSR fetched */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
563 /* NOP fetched, MSR in DECODE */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* NOP fetched, MSR in EXECUTE (1) */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567
568 /* rot == 4 writes flags, which takes only one cycle */
569 if (rot != 4)
570 {
571 /* nothing fetched, MSR in EXECUTE (2) */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* nothing fetched, MSR in EXECUTE (3) */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
575 }
576 }
577
578 void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
579 {
580 int i;
581 /* get pointers to arch-specific information */
582 armv4_5_common_t *armv4_5 = target->arch_info;
583 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
584 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
585
586 /* LDMIA r0-15, [r0] at debug speed
587 * register values will start to appear on 4th DCLK
588 */
589 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
590
591 /* fetch NOP, LDM in DECODE stage */
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
593 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
595
596 for (i = 0; i <= 15; i++)
597 {
598 if (mask & (1 << i))
599 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
600 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
601 }
602 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
603 }
604
605 void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
606 {
607 /* get pointers to arch-specific information */
608 armv4_5_common_t *armv4_5 = target->arch_info;
609 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
610 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
611
612 /* put system-speed load-multiple into the pipeline */
613 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
614 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
615 }
616
617 void arm9tdmi_load_hword_reg(target_t *target, int num)
618 {
619 /* get pointers to arch-specific information */
620 armv4_5_common_t *armv4_5 = target->arch_info;
621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
622 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
623
624 /* put system-speed load half-word into the pipeline */
625 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
627 }
628
629 void arm9tdmi_load_byte_reg(target_t *target, int num)
630 {
631 /* get pointers to arch-specific information */
632 armv4_5_common_t *armv4_5 = target->arch_info;
633 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
634 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
635
636 /* put system-speed load byte into the pipeline */
637 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
639 }
640
641 void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
642 {
643 /* get pointers to arch-specific information */
644 armv4_5_common_t *armv4_5 = target->arch_info;
645 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
646 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
647
648 /* put system-speed store-multiple into the pipeline */
649 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
650 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
651 }
652
653 void arm9tdmi_store_hword_reg(target_t *target, int num)
654 {
655 /* get pointers to arch-specific information */
656 armv4_5_common_t *armv4_5 = target->arch_info;
657 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
658 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
659
660 /* put system-speed store half-word into the pipeline */
661 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
662 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
663 }
664
665 void arm9tdmi_store_byte_reg(target_t *target, int num)
666 {
667 /* get pointers to arch-specific information */
668 armv4_5_common_t *armv4_5 = target->arch_info;
669 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
670 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
671
672 /* put system-speed store byte into the pipeline */
673 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
674 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
675 }
676
677 static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
678 {
679 /* get pointers to arch-specific information */
680 armv4_5_common_t *armv4_5 = target->arch_info;
681 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
682 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
683
684 /* LDMIA r0-15, [r0] at debug speed
685 * register values will start to appear on 4th DCLK
686 */
687 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
688
689 /* fetch NOP, LDM in DECODE stage */
690 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
691 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
692 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
693 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
694 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
695 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
696 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
697 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
698 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
699 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
700 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
701 }
702
703 void arm9tdmi_branch_resume(target_t *target)
704 {
705 /* get pointers to arch-specific information */
706 armv4_5_common_t *armv4_5 = target->arch_info;
707 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
708 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
709
710 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
711 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
712 }
713
714 static void arm9tdmi_branch_resume_thumb(target_t *target)
715 {
716 LOG_DEBUG("-");
717
718 /* get pointers to arch-specific information */
719 armv4_5_common_t *armv4_5 = target->arch_info;
720 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
721 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
722 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
723
724 /* LDMIA r0-15, [r0] at debug speed
725 * register values will start to appear on 4th DCLK
726 */
727 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
728
729 /* fetch NOP, LDM in DECODE stage */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
731 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
733 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
735 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
737
738 /* Branch and eXchange */
739 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
740
741 embeddedice_read_reg(dbg_stat);
742
743 /* fetch NOP, BX in DECODE stage */
744 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
745
746 embeddedice_read_reg(dbg_stat);
747
748 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
749 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
750
751 /* target is now in Thumb state */
752 embeddedice_read_reg(dbg_stat);
753
754 /* load r0 value, MOV_IM in Decode*/
755 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
756 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
757 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
758 /* fetch NOP, LDR in Execute */
759 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
760 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
761 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
762 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
763 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
764
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
767
768 embeddedice_read_reg(dbg_stat);
769
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
772 }
773
774 void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
775 {
776 /* get pointers to arch-specific information */
777 armv4_5_common_t *armv4_5 = target->arch_info;
778 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
779
780 if (arm7_9->has_single_step)
781 {
782 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
783 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
784 }
785 else
786 {
787 arm7_9_enable_eice_step(target, next_pc);
788 }
789 }
790
791 void arm9tdmi_disable_single_step(target_t *target)
792 {
793 /* get pointers to arch-specific information */
794 armv4_5_common_t *armv4_5 = target->arch_info;
795 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
796
797 if (arm7_9->has_single_step)
798 {
799 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
800 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
801 }
802 else
803 {
804 arm7_9_disable_eice_step(target);
805 }
806 }
807
808 static void arm9tdmi_build_reg_cache(target_t *target)
809 {
810 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
811 /* get pointers to arch-specific information */
812 armv4_5_common_t *armv4_5 = target->arch_info;
813
814 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
815 armv4_5->core_cache = (*cache_p);
816 }
817
818 int arm9tdmi_examine(struct target_s *target)
819 {
820 /* get pointers to arch-specific information */
821 int retval;
822 armv4_5_common_t *armv4_5 = target->arch_info;
823 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
824 if (!target_was_examined(target))
825 {
826 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
827 reg_cache_t *t;
828 /* one extra register (vector catch) */
829 t = embeddedice_build_reg_cache(target, arm7_9);
830 if (t == NULL)
831 return ERROR_FAIL;
832 (*cache_p) = t;
833 arm7_9->eice_cache = (*cache_p);
834
835 if (arm7_9->etm_ctx)
836 {
837 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
838 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
839 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
840 }
841 target_set_examined(target);
842 }
843 if ((retval = embeddedice_setup(target)) != ERROR_OK)
844 return retval;
845 if ((retval = arm7_9_setup(target)) != ERROR_OK)
846 return retval;
847 if (arm7_9->etm_ctx)
848 {
849 if ((retval = etm_setup(target)) != ERROR_OK)
850 return retval;
851 }
852 return ERROR_OK;
853 }
854
855 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
856 {
857
858 arm9tdmi_build_reg_cache(target);
859
860 return ERROR_OK;
861 }
862
863 static int arm9tdmi_quit(void)
864 {
865 return ERROR_OK;
866 }
867
868 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
869 {
870 armv4_5_common_t *armv4_5;
871 arm7_9_common_t *arm7_9;
872
873 arm7_9 = &arm9tdmi->arm7_9_common;
874 armv4_5 = &arm7_9->armv4_5_common;
875
876 /* prepare JTAG information for the new target */
877 arm7_9->jtag_info.tap = tap;
878 arm7_9->jtag_info.scann_size = 5;
879
880 /* register arch-specific functions */
881 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
882 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
883 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
884 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
885 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
886
887 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
888 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
889 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
890
891 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
892 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
893 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
894
895 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
896 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
897 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
898
899 arm7_9->write_pc = arm9tdmi_write_pc;
900 arm7_9->branch_resume = arm9tdmi_branch_resume;
901 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
902
903 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
904 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
905
906 arm7_9->pre_debug_entry = NULL;
907 arm7_9->post_debug_entry = NULL;
908
909 arm7_9->pre_restore_context = NULL;
910 arm7_9->post_restore_context = NULL;
911
912 /* initialize arch-specific breakpoint handling */
913 arm7_9->arm_bkpt = 0xdeeedeee;
914 arm7_9->thumb_bkpt = 0xdeee;
915
916 arm7_9->dbgreq_adjust_pc = 3;
917 arm7_9->arch_info = arm9tdmi;
918
919 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
920 arm9tdmi->arch_info = NULL;
921
922 arm7_9_init_arch_info(target, arm7_9);
923
924 /* override use of DBGRQ, this is safe on ARM9TDMI */
925 arm7_9->use_dbgrq = 1;
926
927 /* all ARM9s have the vector catch register */
928 arm7_9->has_vector_catch = 1;
929
930 return ERROR_OK;
931 }
932
933 static int arm9tdmi_get_arch_pointers(target_t *target,
934 armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p,
935 arm9tdmi_common_t **arm9tdmi_p)
936 {
937 armv4_5_common_t *armv4_5 = target->arch_info;
938 arm7_9_common_t *arm7_9;
939 arm9tdmi_common_t *arm9tdmi;
940
941 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
942 {
943 return -1;
944 }
945
946 arm7_9 = armv4_5->arch_info;
947 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
948 {
949 return -1;
950 }
951
952 arm9tdmi = arm7_9->arch_info;
953 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
954 {
955 return -1;
956 }
957
958 *armv4_5_p = armv4_5;
959 *arm7_9_p = arm7_9;
960 *arm9tdmi_p = arm9tdmi;
961
962 return ERROR_OK;
963 }
964
965 static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
966 {
967 arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
968
969 arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
970 arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
971
972 return ERROR_OK;
973 }
974
975 static int handle_arm9tdmi_catch_vectors_command(
976 struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
977 {
978 target_t *target = get_current_target(cmd_ctx);
979 armv4_5_common_t *armv4_5;
980 arm7_9_common_t *arm7_9;
981 arm9tdmi_common_t *arm9tdmi;
982 reg_t *vector_catch;
983 uint32_t vector_catch_value;
984 int i, j;
985
986 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
987 {
988 command_print(cmd_ctx, "current target isn't an ARM9 based target");
989 return ERROR_OK;
990 }
991
992 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
993
994 /* read the vector catch register if necessary */
995 if (!vector_catch->valid)
996 embeddedice_read_reg(vector_catch);
997
998 /* get the current setting */
999 vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
1000
1001 if (argc > 0)
1002 {
1003 vector_catch_value = 0x0;
1004 if (strcmp(args[0], "all") == 0)
1005 {
1006 vector_catch_value = 0xdf;
1007 }
1008 else if (strcmp(args[0], "none") == 0)
1009 {
1010 /* do nothing */
1011 }
1012 else
1013 {
1014 for (i = 0; i < argc; i++)
1015 {
1016 /* go through list of vectors */
1017 for (j = 0; arm9tdmi_vectors[j].name; j++)
1018 {
1019 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1020 {
1021 vector_catch_value |= arm9tdmi_vectors[j].value;
1022 break;
1023 }
1024 }
1025
1026 /* complain if vector wasn't found */
1027 if (!arm9tdmi_vectors[j].name)
1028 {
1029 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1030
1031 /* reread current setting */
1032 vector_catch_value = buf_get_u32(
1033 vector_catch->value,
1034 0, 8);
1035
1036 break;
1037 }
1038 }
1039 }
1040
1041 /* store new settings */
1042 buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
1043 embeddedice_store_reg(vector_catch);
1044 }
1045
1046 /* output current settings (skip RESERVED vector) */
1047 for (i = 0; i < 8; i++)
1048 {
1049 if (i != 5)
1050 {
1051 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1052 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1053 }
1054 }
1055
1056 return ERROR_OK;
1057 }
1058
1059 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1060 {
1061 int retval;
1062 command_t *arm9tdmi_cmd;
1063
1064 retval = arm7_9_register_commands(cmd_ctx);
1065 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi",
1066 NULL, COMMAND_ANY,
1067 "arm9tdmi specific commands");
1068 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
1069 handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
1070 "catch arm9 vectors ['all'|'none'|'<vec1 vec2 ...>']");
1071
1072 return retval;
1073 }
1074
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