1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
34 typedef enum armv4_5_mode
36 ARMV4_5_MODE_USR
= 16,
37 ARMV4_5_MODE_FIQ
= 17,
38 ARMV4_5_MODE_IRQ
= 18,
39 ARMV4_5_MODE_SVC
= 19,
40 ARMV4_5_MODE_ABT
= 23,
41 ARMV4_5_MODE_UND
= 27,
42 ARMV4_5_MODE_SYS
= 31,
46 extern char** armv4_5_mode_strings
;
48 typedef enum armv4_5_state
52 ARMV4_5_STATE_JAZELLE
,
55 extern char* armv4_5_state_strings
[];
57 extern int armv4_5_core_reg_map
[7][17];
59 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
60 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
61 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
62 cache->reg_list[armv4_5_core_reg_map[mode][num]]
64 /* offsets into armv4_5 core register cache */
68 ARMV4_5_SPSR_FIQ
= 32,
69 ARMV4_5_SPSR_IRQ
= 33,
70 ARMV4_5_SPSR_SVC
= 34,
71 ARMV4_5_SPSR_ABT
= 35,
75 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
77 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
78 #define armv4_5_common_s arm
81 * Represents a generic ARM core, with standard application registers.
83 * There are sixteen application registers (including PC, SP, LR) and a PSR.
84 * Cortex-M series cores do not support as many core states or shadowed
85 * registers as traditional ARM cores, and only support Thumb2 instructions.
90 reg_cache_t
*core_cache
;
92 int /* armv4_5_mode */ core_mode
;
93 enum armv4_5_state core_state
;
95 /** Flag reporting unavailability of the BKPT instruction. */
98 /** Handle for the Embedded Trace Module, if one is present. */
101 int (*full_context
)(struct target_s
*target
);
102 int (*read_core_reg
)(struct target_s
*target
,
103 int num
, enum armv4_5_mode mode
);
104 int (*write_core_reg
)(struct target_s
*target
,
105 int num
, enum armv4_5_mode mode
, uint32_t value
);
109 #define target_to_armv4_5 target_to_arm
111 /** Convert target handle to generic ARM target state handle. */
112 static inline struct arm
*target_to_arm(struct target_s
*target
)
114 return target
->arch_info
;
117 static inline bool is_arm(struct arm
*arm
)
119 return arm
&& arm
->common_magic
== ARMV4_5_COMMON_MAGIC
;
122 typedef struct armv4_5_algorithm_s
126 enum armv4_5_mode core_mode
;
127 enum armv4_5_state core_state
;
128 } armv4_5_algorithm_t
;
130 typedef struct armv4_5_core_reg_s
133 enum armv4_5_mode mode
;
135 armv4_5_common_t
*armv4_5_common
;
136 } armv4_5_core_reg_t
;
138 reg_cache_t
* armv4_5_build_reg_cache(target_t
*target
,
139 armv4_5_common_t
*armv4_5_common
);
141 /* map psr mode bits to linear number */
142 static __inline
int armv4_5_mode_to_number(enum armv4_5_mode mode
)
146 case ARMV4_5_MODE_USR
: return 0; break;
147 case ARMV4_5_MODE_FIQ
: return 1; break;
148 case ARMV4_5_MODE_IRQ
: return 2; break;
149 case ARMV4_5_MODE_SVC
: return 3; break;
150 case ARMV4_5_MODE_ABT
: return 4; break;
151 case ARMV4_5_MODE_UND
: return 5; break;
152 case ARMV4_5_MODE_SYS
: return 6; break;
153 case ARMV4_5_MODE_ANY
: return 0; break; /* map MODE_ANY to user mode */
155 LOG_ERROR("invalid mode value encountered %d", mode
);
160 /* map linear number to mode bits */
161 static __inline
enum armv4_5_mode
armv4_5_number_to_mode(int number
)
165 case 0: return ARMV4_5_MODE_USR
; break;
166 case 1: return ARMV4_5_MODE_FIQ
; break;
167 case 2: return ARMV4_5_MODE_IRQ
; break;
168 case 3: return ARMV4_5_MODE_SVC
; break;
169 case 4: return ARMV4_5_MODE_ABT
; break;
170 case 5: return ARMV4_5_MODE_UND
; break;
171 case 6: return ARMV4_5_MODE_SYS
; break;
173 LOG_ERROR("mode index out of bounds %d", number
);
174 return ARMV4_5_MODE_ANY
;
178 int armv4_5_arch_state(struct target_s
*target
);
179 int armv4_5_get_gdb_reg_list(target_t
*target
,
180 reg_t
**reg_list
[], int *reg_list_size
);
182 int armv4_5_register_commands(struct command_context_s
*cmd_ctx
);
183 int armv4_5_init_arch_info(target_t
*target
, armv4_5_common_t
*armv4_5
);
185 int armv4_5_run_algorithm(struct target_s
*target
,
186 int num_mem_params
, struct mem_param
*mem_params
,
187 int num_reg_params
, struct reg_param
*reg_params
,
188 uint32_t entry_point
, uint32_t exit_point
,
189 int timeout_ms
, void *arch_info
);
191 int armv4_5_invalidate_core_regs(target_t
*target
);
193 /* ARM mode instructions
196 /* Store multiple increment after
198 * List: for each bit in list: store register
199 * S: in priviledged mode: store user-mode registers
200 * W = 1: update the base register. W = 0: leave the base register untouched
202 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
204 /* Load multiple increment after
206 * List: for each bit in list: store register
207 * S: in priviledged mode: store user-mode registers
208 * W = 1: update the base register. W = 0: leave the base register untouched
210 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
213 #define ARMV4_5_NOP (0xe1a08008)
215 /* Move PSR to general purpose register
216 * R = 1: SPSR R = 0: CPSR
217 * Rn: target register
219 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
222 * Rd: register to store
225 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
228 * Rd: register to load
231 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
233 /* Move general purpose register to PSR
234 * R = 1: SPSR R = 0: CPSR
236 * 1: control field 2: extension field 4: status field 8: flags field
237 * Rm: source register
239 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
240 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
242 /* Load Register Halfword Immediate Post-Index
243 * Rd: register to load
246 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
248 /* Load Register Byte Immediate Post-Index
249 * Rd: register to load
252 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
254 /* Store register Halfword Immediate Post-Index
255 * Rd: register to store
258 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
260 /* Store register Byte Immediate Post-Index
261 * Rd: register to store
264 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
267 * Im: Branch target (left-shifted by 2 bits, added to PC)
268 * L: 1: branch and link 0: branch only
270 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
272 /* Branch and exchange (ARM state)
273 * Rm: register holding branch target address
275 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
277 /* Move to ARM register from coprocessor
278 * CP: Coprocessor number
279 * op1: Coprocessor opcode
280 * Rd: destination register
281 * CRn: first coprocessor operand
282 * CRm: second coprocessor operand
283 * op2: Second coprocessor opcode
285 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
287 /* Move to coprocessor from ARM register
288 * CP: Coprocessor number
289 * op1: Coprocessor opcode
290 * Rd: destination register
291 * CRn: first coprocessor operand
292 * CRm: second coprocessor operand
293 * op2: Second coprocessor opcode
295 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
297 /* Breakpoint instruction (ARMv5)
298 * Im: 16-bit immediate
300 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
303 /* Thumb mode instructions
306 /* Store register (Thumb mode)
307 * Rd: source register
310 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
312 /* Load register (Thumb state)
313 * Rd: destination register
316 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
318 /* Load multiple (Thumb state)
320 * List: for each bit in list: store register
322 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
324 /* Load register with PC relative addressing
325 * Rd: register to load
327 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
329 /* Move hi register (Thumb mode)
330 * Rd: destination register
331 * Rm: source register
333 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
335 /* No operation (Thumb mode)
337 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
339 /* Move immediate to register (Thumb state)
340 * Rd: destination register
341 * Im: 8-bit immediate value
343 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
345 /* Branch and Exchange
346 * Rm: register containing branch target
348 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
350 /* Branch (Thumb state)
353 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
355 /* Breakpoint instruction (ARMv5) (Thumb state)
356 * Im: 8-bit immediate
358 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
360 /* build basic mrc/mcr opcode */
362 static inline uint32_t mrc_opcode(int cpnum
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
)
375 #endif /* ARMV4_5_H */