Add EfikaMX smarttop board support
[openocd/cortex.git] / src / target / dsp563xx.h
blobf8070fa7e8f6c79c2423e9d6ba02c54a3ad59a7e
1 /***************************************************************************
2 * Copyright (C) 2009 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef DSP563XX_H
21 #define DSP563XX_H
23 #include <jtag/jtag.h>
25 #define DSP563XX_NUMCOREREGS 44
27 struct mcu_jtag
29 struct jtag_tap *tap;
32 struct dsp563xx_pipeline_context
34 /* PIL Register */
35 uint32_t once_opilr;
36 /* PDB Register */
37 uint32_t once_opdbr;
40 struct dsp563xx_common
42 struct mcu_jtag jtag_info;
43 struct reg_cache *core_cache;
44 uint32_t core_regs[DSP563XX_NUMCOREREGS];
46 struct dsp563xx_pipeline_context pipeline_context;
48 /* register cache to processor synchronization */
49 int (*read_core_reg) (struct target * target, int num);
50 int (*write_core_reg) (struct target * target, int num);
53 struct dsp563xx_core_reg
55 uint32_t num;
56 char *name;
57 uint32_t size;
58 uint32_t r_cmd;
59 uint32_t w_cmd;
60 struct target *target;
61 struct dsp563xx_common *dsp563xx_common;
64 static inline struct dsp563xx_common *target_to_dsp563xx(struct target *target)
66 return target->arch_info;
69 int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
70 int dr_len, int rti);
71 int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
72 int dr_len, int rti);
74 int dsp563xx_execute_queue(void);
76 #endif /* DSP563XX_H */