src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 /**
  27  * @file
  28  * This defines formats and data structures used to talk to ADIv5 entities.
  29  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  30  * resources accessed through a MEM-AP.
  31  */
  32
  33 #include "arm_jtag.h"
  34
  35 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  36 #define JTAG_DP_ABORT           0x8
  37 #define JTAG_DP_DPACC           0xA
  38 #define JTAG_DP_APACC           0xB
  39 #define JTAG_DP_IDCODE          0xE
  40
  41 /* three-bit ACK values for DPACC and APACC reads */
  42 #define JTAG_ACK_OK_FAULT       0x2
  43 #define JTAG_ACK_WAIT           0x1
  44
  45 #define DPAP_WRITE              0
  46 #define DPAP_READ               1
  47
  48 /* A[3:0] for DP registers (for JTAG, stored in DPACC) */
  49 #define DP_ZERO                 0
  50 #define DP_CTRL_STAT    0x4
  51 #define DP_SELECT               0x8
  52 #define DP_RDBUFF               0xC
  53
  54 /* Fields of the DP's CTRL/STAT register */
  55 #define CORUNDETECT             (1 << 0)
  56 #define SSTICKYORUN             (1 << 1)
  57 /* 3:2 - transaction mode (e.g. pushed compare) */
  58 #define SSTICKYERR              (1 << 5)
  59 #define READOK                  (1 << 6)
  60 #define WDATAERR                (1 << 7)
  61 /* 11:8 - mask lanes for pushed compare or verify ops */
  62 /* 21:12 - transaction counter */
  63 #define CDBGRSTREQ              (1 << 26)
  64 #define CDBGRSTACK              (1 << 27)
  65 #define CDBGPWRUPREQ    (1 << 28)
  66 #define CDBGPWRUPACK    (1 << 29)
  67 #define CSYSPWRUPREQ    (1 << 30)
  68 #define CSYSPWRUPACK    (1 << 31)
  69
  70 /* MEM-AP register addresses */
  71 /* TODO: rename as MEM_AP_REG_* */
  72 #define AP_REG_CSW              0x00
  73 #define AP_REG_TAR              0x04
  74 #define AP_REG_DRW              0x0C
  75 #define AP_REG_BD0              0x10
  76 #define AP_REG_BD1              0x14
  77 #define AP_REG_BD2              0x18
  78 #define AP_REG_BD3              0x1C
  79 #define AP_REG_CFG              0xF4            /* big endian? */
  80 #define AP_REG_BASE             0xF8
  81
  82 /* Generic AP register address */
  83 #define AP_REG_IDR              0xFC
  84
  85 /* Fields of the MEM-AP's CSW register */
  86 #define CSW_8BIT                0
  87 #define CSW_16BIT               1
  88 #define CSW_32BIT               2
  89 #define CSW_ADDRINC_MASK        (3 << 4)
  90 #define CSW_ADDRINC_OFF         0
  91 #define CSW_ADDRINC_SINGLE      (1 << 4)
  92 #define CSW_ADDRINC_PACKED      (2 << 4)
  93 #define CSW_DEVICE_EN           (1 << 6)
  94 #define CSW_TRIN_PROG           (1 << 7)
  95 #define CSW_SPIDEN                      (1 << 23)
  96 /* 30:24 - implementation-defined! */
  97 #define CSW_HPROT                       (1 << 25)               /* ? */
  98 #define CSW_MASTER_DEBUG        (1 << 29)               /* ? */
  99 #define CSW_DBGSWENABLE         (1 << 31)
 100
 101 /* transaction mode */
 102 #define TRANS_MODE_NONE                 0
 103 /* Transaction waits for previous to complete */
 104 #define TRANS_MODE_ATOMIC               1
 105 /* Freerunning transactions with delays and overrun checking */
 106 #define TRANS_MODE_COMPOSITE    2
 107
 108 /**
 109  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 110  * A DAP has two types of component:  one Debug Port (DP), which is a
 111  * transport agent; and at least one Access Port (AP), controlling
 112  * resource access.  Most common is a MEM-AP, for memory access.
 113  *
 114  * @todo Rename "swjdp_common" as "dap".  Use of SWJ-DP is optional!
 115  */
 116 struct swjdp_common
 117 {
 118         struct arm_jtag *jtag_info;
 119         /* Control config */
 120         uint32_t dp_ctrl_stat;
 121         /* Support for several AP's in one DAP */
 122         uint32_t apsel;
 123         /* Register select cache */
 124         uint32_t dp_select_value;
 125         uint32_t ap_csw_value;
 126         uint32_t ap_tar_value;
 127         /* information about current pending SWjDP-AHBAP transaction */
 128         uint8_t  trans_mode;
 129         uint8_t  trans_rw;
 130         uint8_t  ack;
 131         /* extra tck clocks for memory bus access */
 132         uint32_t        memaccess_tck;
 133         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 134         uint32_t tar_autoincr_block;
 135
 136 };
 137
 138 /* Accessor function for currently selected DAP-AP number */
 139 static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 140 {
 141         return (uint8_t)(swjdp ->apsel >> 24);
 142 }
 143
 144 /* Queued transactions -- use with care */
 145 int dap_setup_accessport(struct swjdp_common *swjdp,
 146                 uint32_t csw, uint32_t tar);
 147 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel);
 148 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 149                 uint32_t addr, uint32_t value);
 150 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 151                 uint32_t addr, uint32_t *value);
 152
 153 /* Queued transactions must be completed with swjdp_transaction_endcheck() */
 154 int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
 155
 156 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
 157 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
 158 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
 159
 160 /* MEM-AP memory mapped bus transfers, single registers, complete transactions */
 161 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
 162                 uint32_t address, uint32_t *value);
 163 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
 164                 uint32_t address, uint32_t value);
 165
 166 /* MEM-AP memory mapped bus block transfers */
 167 int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
 168                 uint8_t *buffer, int count, uint32_t address);
 169 int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
 170                 uint8_t *buffer, int count, uint32_t address);
 171 int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
 172                 uint8_t *buffer, int count, uint32_t address);
 173
 174 int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
 175                 uint8_t *buffer, int count, uint32_t address);
 176 int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
 177                 uint8_t *buffer, int count, uint32_t address);
 178 int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
 179                 uint8_t *buffer, int count, uint32_t address);
 180
 181 /* Initialisation of the debug system, power domains and registers */
 182 int ahbap_debugport_init(struct swjdp_common *swjdp);
 183
 184
 185 /* Commands for user dap access */
 186 int dap_info_command(struct command_context *cmd_ctx,
 187                 struct swjdp_common *swjdp, int apsel);
 188
 189 #define DAP_COMMAND_HANDLER(name) \
 190                 COMMAND_HELPER(name, struct swjdp_common *swjdp)
 191 DAP_COMMAND_HANDLER(dap_baseaddr_command);
 192 DAP_COMMAND_HANDLER(dap_memaccess_command);
 193 DAP_COMMAND_HANDLER(dap_apsel_command);
 194 DAP_COMMAND_HANDLER(dap_apid_command);
 195
 196 #endif