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zy1000.cfg: gdb connect will fail first time without gdb-attach
[openocd/cortex.git] / src / target / etm.c
blob4f4bf9a43066c2523dd90996a93d5d66d1afd599
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_CTRL_DBGRQ
450 & ~ETM_PORT_CLOCK_MASK)
451 | etm_ctx->control;
452
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
455
456 etm_ctx->control = etm_ctrl_value;
457
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 return retval;
460
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
463 */
464
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
466 {
467 LOG_ERROR("ETM capture driver initialization failed");
468 return retval;
469 }
470 return ERROR_OK;
471 }
472
473 static int etm_get_reg(struct reg *reg)
474 {
475 int retval;
476
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
478 {
479 LOG_ERROR("BUG: error scheduling etm register read");
480 return retval;
481 }
482
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
484 {
485 LOG_ERROR("register read failed");
486 return retval;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
494 {
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
499
500 if (etm_reg->reg_info->mode == WO) {
501 LOG_ERROR("BUG: can't read write-only register %s", r->name);
502 return ERROR_INVALID_ARGUMENTS;
503 }
504
505 LOG_DEBUG("%s (%u)", r->name, reg_addr);
506
507 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
508 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
509
510 fields[0].num_bits = 32;
511 fields[0].out_value = reg->value;
512 fields[0].in_value = NULL;
513 fields[0].check_value = NULL;
514 fields[0].check_mask = NULL;
515
516 fields[1].num_bits = 7;
517 uint8_t temp1;
518 fields[1].out_value = &temp1;
519 buf_set_u32(&temp1, 0, 7, reg_addr);
520 fields[1].in_value = NULL;
521 fields[1].check_value = NULL;
522 fields[1].check_mask = NULL;
523
524 fields[2].num_bits = 1;
525 uint8_t temp2;
526 fields[2].out_value = &temp2;
527 buf_set_u32(&temp2, 0, 1, 0);
528 fields[2].in_value = NULL;
529 fields[2].check_value = NULL;
530 fields[2].check_mask = NULL;
531
532 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
533
534 fields[0].in_value = reg->value;
535 fields[0].check_value = check_value;
536 fields[0].check_mask = check_mask;
537
538 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
539
540 return ERROR_OK;
541 }
542
543 static int etm_set_reg(struct reg *reg, uint32_t value)
544 {
545 int retval;
546
547 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
548 {
549 LOG_ERROR("BUG: error scheduling etm register write");
550 return retval;
551 }
552
553 buf_set_u32(reg->value, 0, reg->size, value);
554 reg->valid = 1;
555 reg->dirty = 0;
556
557 return ERROR_OK;
558 }
559
560 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
561 {
562 int retval;
563
564 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
565
566 if ((retval = jtag_execute_queue()) != ERROR_OK)
567 {
568 LOG_ERROR("register write failed");
569 return retval;
570 }
571 return ERROR_OK;
572 }
573
574 static int etm_write_reg(struct reg *reg, uint32_t value)
575 {
576 struct etm_reg *etm_reg = reg->arch_info;
577 const struct etm_reg_info *r = etm_reg->reg_info;
578 uint8_t reg_addr = r->addr & 0x7f;
579 struct scan_field fields[3];
580
581 if (etm_reg->reg_info->mode == RO) {
582 LOG_ERROR("BUG: can't write read--only register %s", r->name);
583 return ERROR_INVALID_ARGUMENTS;
584 }
585
586 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
587
588 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
589 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
590
591 fields[0].num_bits = 32;
592 uint8_t tmp1[4];
593 fields[0].out_value = tmp1;
594 buf_set_u32(tmp1, 0, 32, value);
595 fields[0].in_value = NULL;
596
597 fields[1].num_bits = 7;
598 uint8_t tmp2;
599 fields[1].out_value = &tmp2;
600 buf_set_u32(&tmp2, 0, 7, reg_addr);
601 fields[1].in_value = NULL;
602
603 fields[2].num_bits = 1;
604 uint8_t tmp3;
605 fields[2].out_value = &tmp3;
606 buf_set_u32(&tmp3, 0, 1, 1);
607 fields[2].in_value = NULL;
608
609 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
610
611 return ERROR_OK;
612 }
613
614
615 /* ETM trace analysis functionality */
616
617 static struct etm_capture_driver *etm_capture_drivers[] =
618 {
619 &etb_capture_driver,
620 &etm_dummy_capture_driver,
621 #if BUILD_OOCD_TRACE == 1
622 &oocd_trace_capture_driver,
623 #endif
624 NULL
625 };
626
627 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
628 {
629 int i;
630 int section = -1;
631 size_t size_read;
632 uint32_t opcode;
633 int retval;
634
635 if (!ctx->image)
636 return ERROR_TRACE_IMAGE_UNAVAILABLE;
637
638 /* search for the section the current instruction belongs to */
639 for (i = 0; i < ctx->image->num_sections; i++)
640 {
641 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
642 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
643 {
644 section = i;
645 break;
646 }
647 }
648
649 if (section == -1)
650 {
651 /* current instruction couldn't be found in the image */
652 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
653 }
654
655 if (ctx->core_state == ARM_STATE_ARM)
656 {
657 uint8_t buf[4];
658 if ((retval = image_read_section(ctx->image, section,
659 ctx->current_pc - ctx->image->sections[section].base_address,
660 4, buf, &size_read)) != ERROR_OK)
661 {
662 LOG_ERROR("error while reading instruction: %i", retval);
663 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
664 }
665 opcode = target_buffer_get_u32(ctx->target, buf);
666 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
667 }
668 else if (ctx->core_state == ARM_STATE_THUMB)
669 {
670 uint8_t buf[2];
671 if ((retval = image_read_section(ctx->image, section,
672 ctx->current_pc - ctx->image->sections[section].base_address,
673 2, buf, &size_read)) != ERROR_OK)
674 {
675 LOG_ERROR("error while reading instruction: %i", retval);
676 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
677 }
678 opcode = target_buffer_get_u16(ctx->target, buf);
679 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
680 }
681 else if (ctx->core_state == ARM_STATE_JAZELLE)
682 {
683 LOG_ERROR("BUG: tracing of jazelle code not supported");
684 return ERROR_FAIL;
685 }
686 else
687 {
688 LOG_ERROR("BUG: unknown core state encountered");
689 return ERROR_FAIL;
690 }
691
692 return ERROR_OK;
693 }
694
695 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
696 {
697 while (ctx->data_index < ctx->trace_depth)
698 {
699 /* if the caller specified an address packet offset, skip until the
700 * we reach the n-th cycle marked with tracesync */
701 if (apo > 0)
702 {
703 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
704 apo--;
705
706 if (apo > 0)
707 {
708 ctx->data_index++;
709 ctx->data_half = 0;
710 }
711 continue;
712 }
713
714 /* no tracedata output during a TD cycle
715 * or in a trigger cycle */
716 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
717 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
718 {
719 ctx->data_index++;
720 ctx->data_half = 0;
721 continue;
722 }
723
724 /* FIXME there are more port widths than these... */
725 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
726 {
727 if (ctx->data_half == 0)
728 {
729 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
730 ctx->data_half = 1;
731 }
732 else
733 {
734 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
735 ctx->data_half = 0;
736 ctx->data_index++;
737 }
738 }
739 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
740 {
741 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
742 ctx->data_index++;
743 }
744 else
745 {
746 /* on a 4-bit port, a packet will be output during two consecutive cycles */
747 if (ctx->data_index > (ctx->trace_depth - 2))
748 return -1;
749
750 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
751 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
752 ctx->data_index += 2;
753 }
754
755 return 0;
756 }
757
758 return -1;
759 }
760
761 static int etmv1_branch_address(struct etm_context *ctx)
762 {
763 int retval;
764 uint8_t packet;
765 int shift = 0;
766 int apo;
767 uint32_t i;
768
769 /* quit analysis if less than two cycles are left in the trace
770 * because we can't extract the APO */
771 if (ctx->data_index > (ctx->trace_depth - 2))
772 return -1;
773
774 /* a BE could be output during an APO cycle, skip the current
775 * and continue with the new one */
776 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
777 return 1;
778 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
779 return 2;
780
781 /* address packet offset encoded in the next two cycles' pipestat bits */
782 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
783 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
784
785 /* count number of tracesync cycles between current pipe_index and data_index
786 * i.e. the number of tracesyncs that data_index already passed by
787 * to subtract them from the APO */
788 for (i = ctx->pipe_index; i < ctx->data_index; i++)
789 {
790 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
791 apo--;
792 }
793
794 /* extract up to four 7-bit packets */
795 do {
796 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
797 return -1;
798 ctx->last_branch &= ~(0x7f << shift);
799 ctx->last_branch |= (packet & 0x7f) << shift;
800 shift += 7;
801 } while ((packet & 0x80) && (shift < 28));
802
803 /* one last packet holding 4 bits of the address, plus the branch reason code */
804 if ((shift == 28) && (packet & 0x80))
805 {
806 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
807 return -1;
808 ctx->last_branch &= 0x0fffffff;
809 ctx->last_branch |= (packet & 0x0f) << 28;
810 ctx->last_branch_reason = (packet & 0x70) >> 4;
811 shift += 4;
812 }
813 else
814 {
815 ctx->last_branch_reason = 0;
816 }
817
818 if (shift == 32)
819 {
820 ctx->pc_ok = 1;
821 }
822
823 /* if a full address was output, we might have branched into Jazelle state */
824 if ((shift == 32) && (packet & 0x80))
825 {
826 ctx->core_state = ARM_STATE_JAZELLE;
827 }
828 else
829 {
830 /* if we didn't branch into Jazelle state, the current processor state is
831 * encoded in bit 0 of the branch target address */
832 if (ctx->last_branch & 0x1)
833 {
834 ctx->core_state = ARM_STATE_THUMB;
835 ctx->last_branch &= ~0x1;
836 }
837 else
838 {
839 ctx->core_state = ARM_STATE_ARM;
840 ctx->last_branch &= ~0x3;
841 }
842 }
843
844 return 0;
845 }
846
847 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
848 {
849 int j;
850 uint8_t buf[4];
851 int retval;
852
853 for (j = 0; j < size; j++)
854 {
855 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
856 return -1;
857 }
858
859 if (size == 8)
860 {
861 LOG_ERROR("TODO: add support for 64-bit values");
862 return -1;
863 }
864 else if (size == 4)
865 *data = target_buffer_get_u32(ctx->target, buf);
866 else if (size == 2)
867 *data = target_buffer_get_u16(ctx->target, buf);
868 else if (size == 1)
869 *data = buf[0];
870 else
871 return -1;
872
873 return 0;
874 }
875
876 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
877 {
878 int retval;
879 struct arm_instruction instruction;
880
881 /* read the trace data if it wasn't read already */
882 if (ctx->trace_depth == 0)
883 ctx->capture_driver->read_trace(ctx);
884
885 /* start at the beginning of the captured trace */
886 ctx->pipe_index = 0;
887 ctx->data_index = 0;
888 ctx->data_half = 0;
889
890 /* neither the PC nor the data pointer are valid */
891 ctx->pc_ok = 0;
892 ctx->ptr_ok = 0;
893
894 while (ctx->pipe_index < ctx->trace_depth)
895 {
896 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
897 uint32_t next_pc = ctx->current_pc;
898 uint32_t old_data_index = ctx->data_index;
899 uint32_t old_data_half = ctx->data_half;
900 uint32_t old_index = ctx->pipe_index;
901 uint32_t last_instruction = ctx->last_instruction;
902 uint32_t cycles = 0;
903 int current_pc_ok = ctx->pc_ok;
904
905 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
906 {
907 command_print(cmd_ctx, "--- trigger ---");
908 }
909
910 /* instructions execute in IE/D or BE/D cycles */
911 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
912 ctx->last_instruction = ctx->pipe_index;
913
914 /* if we don't have a valid pc skip until we reach an indirect branch */
915 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
916 {
917 ctx->pipe_index++;
918 continue;
919 }
920
921 /* any indirect branch could have interrupted instruction flow
922 * - the branch reason code could indicate a trace discontinuity
923 * - a branch to the exception vectors indicates an exception
924 */
925 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
926 {
927 /* backup current data index, to be able to consume the branch address
928 * before examining data address and values
929 */
930 old_data_index = ctx->data_index;
931 old_data_half = ctx->data_half;
932
933 ctx->last_instruction = ctx->pipe_index;
934
935 if ((retval = etmv1_branch_address(ctx)) != 0)
936 {
937 /* negative return value from etmv1_branch_address means we ran out of packets,
938 * quit analysing the trace */
939 if (retval < 0)
940 break;
941
942 /* a positive return values means the current branch was abandoned,
943 * and a new branch was encountered in cycle ctx->pipe_index + retval;
944 */
945 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
946 ctx->pipe_index += retval;
947 continue;
948 }
949
950 /* skip over APO cycles */
951 ctx->pipe_index += 2;
952
953 switch (ctx->last_branch_reason)
954 {
955 case 0x0: /* normal PC change */
956 next_pc = ctx->last_branch;
957 break;
958 case 0x1: /* tracing enabled */
959 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
960 ctx->current_pc = ctx->last_branch;
961 ctx->pipe_index++;
962 continue;
963 break;
964 case 0x2: /* trace restarted after FIFO overflow */
965 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
966 ctx->current_pc = ctx->last_branch;
967 ctx->pipe_index++;
968 continue;
969 break;
970 case 0x3: /* exit from debug state */
971 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
972 ctx->current_pc = ctx->last_branch;
973 ctx->pipe_index++;
974 continue;
975 break;
976 case 0x4: /* periodic synchronization point */
977 next_pc = ctx->last_branch;
978 /* if we had no valid PC prior to this synchronization point,
979 * we have to move on with the next trace cycle
980 */
981 if (!current_pc_ok)
982 {
983 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
984 ctx->current_pc = next_pc;
985 ctx->pipe_index++;
986 continue;
987 }
988 break;
989 default: /* reserved */
990 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
991 return ERROR_FAIL;
992 }
993
994 /* if we got here the branch was a normal PC change
995 * (or a periodic synchronization point, which means the same for that matter)
996 * if we didn't accquire a complete PC continue with the next cycle
997 */
998 if (!ctx->pc_ok)
999 continue;
1000
1001 /* indirect branch to the exception vector means an exception occured */
1002 if ((ctx->last_branch <= 0x20)
1003 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1004 {
1005 if ((ctx->last_branch & 0xff) == 0x10)
1006 {
1007 command_print(cmd_ctx, "data abort");
1008 }
1009 else
1010 {
1011 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1012 ctx->current_pc = ctx->last_branch;
1013 ctx->pipe_index++;
1014 continue;
1015 }
1016 }
1017 }
1018
1019 /* an instruction was executed (or not, depending on the condition flags)
1020 * retrieve it from the image for displaying */
1021 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1022 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1023 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1024 {
1025 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1026 {
1027 /* can't continue tracing with no image available */
1028 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1029 {
1030 return retval;
1031 }
1032 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1033 {
1034 /* TODO: handle incomplete images
1035 * for now we just quit the analsysis*/
1036 return retval;
1037 }
1038 }
1039
1040 cycles = old_index - last_instruction;
1041 }
1042
1043 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1044 {
1045 uint32_t new_data_index = ctx->data_index;
1046 uint32_t new_data_half = ctx->data_half;
1047
1048 /* in case of a branch with data, the branch target address was consumed before
1049 * we temporarily go back to the saved data index */
1050 if (pipestat == STAT_BD)
1051 {
1052 ctx->data_index = old_data_index;
1053 ctx->data_half = old_data_half;
1054 }
1055
1056 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1057 {
1058 uint8_t packet;
1059 int shift = 0;
1060
1061 do {
1062 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1063 return ERROR_ETM_ANALYSIS_FAILED;
1064 ctx->last_ptr &= ~(0x7f << shift);
1065 ctx->last_ptr |= (packet & 0x7f) << shift;
1066 shift += 7;
1067 } while ((packet & 0x80) && (shift < 32));
1068
1069 if (shift >= 32)
1070 ctx->ptr_ok = 1;
1071
1072 if (ctx->ptr_ok)
1073 {
1074 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1075 }
1076 }
1077
1078 if (ctx->control & ETM_CTRL_TRACE_DATA)
1079 {
1080 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1081 {
1082 int i;
1083 for (i = 0; i < 16; i++)
1084 {
1085 if (instruction.info.load_store_multiple.register_list & (1 << i))
1086 {
1087 uint32_t data;
1088 if (etmv1_data(ctx, 4, &data) != 0)
1089 return ERROR_ETM_ANALYSIS_FAILED;
1090 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1091 }
1092 }
1093 }
1094 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1095 {
1096 uint32_t data;
1097 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1098 return ERROR_ETM_ANALYSIS_FAILED;
1099 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1100 }
1101 }
1102
1103 /* restore data index after consuming BD address and data */
1104 if (pipestat == STAT_BD)
1105 {
1106 ctx->data_index = new_data_index;
1107 ctx->data_half = new_data_half;
1108 }
1109 }
1110
1111 /* adjust PC */
1112 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1113 {
1114 if (((instruction.type == ARM_B) ||
1115 (instruction.type == ARM_BL) ||
1116 (instruction.type == ARM_BLX)) &&
1117 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1118 {
1119 next_pc = instruction.info.b_bl_bx_blx.target_address;
1120 }
1121 else
1122 {
1123 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1124 }
1125 }
1126 else if (pipestat == STAT_IN)
1127 {
1128 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1129 }
1130
1131 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1132 {
1133 char cycles_text[32] = "";
1134
1135 /* if the trace was captured with cycle accurate tracing enabled,
1136 * output the number of cycles since the last executed instruction
1137 */
1138 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1139 {
1140 snprintf(cycles_text, 32, " (%i %s)",
1141 (int)cycles,
1142 (cycles == 1) ? "cycle" : "cycles");
1143 }
1144
1145 command_print(cmd_ctx, "%s%s%s",
1146 instruction.text,
1147 (pipestat == STAT_IN) ? " (not executed)" : "",
1148 cycles_text);
1149
1150 ctx->current_pc = next_pc;
1151
1152 /* packets for an instruction don't start on or before the preceding
1153 * functional pipestat (i.e. other than WT or TD)
1154 */
1155 if (ctx->data_index <= ctx->pipe_index)
1156 {
1157 ctx->data_index = ctx->pipe_index + 1;
1158 ctx->data_half = 0;
1159 }
1160 }
1161
1162 ctx->pipe_index += 1;
1163 }
1164
1165 return ERROR_OK;
1166 }
1167
1168 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1169 uint32_t *mode)
1170 {
1171 uint32_t tracemode;
1172
1173 /* what parts of data access are traced? */
1174 if (strcmp(CMD_ARGV[0], "none") == 0)
1175 tracemode = 0;
1176 else if (strcmp(CMD_ARGV[0], "data") == 0)
1177 tracemode = ETM_CTRL_TRACE_DATA;
1178 else if (strcmp(CMD_ARGV[0], "address") == 0)
1179 tracemode = ETM_CTRL_TRACE_ADDR;
1180 else if (strcmp(CMD_ARGV[0], "all") == 0)
1181 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1182 else
1183 {
1184 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1185 return ERROR_INVALID_ARGUMENTS;
1186 }
1187
1188 uint8_t context_id;
1189 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1190 switch (context_id)
1191 {
1192 case 0:
1193 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1194 break;
1195 case 8:
1196 tracemode |= ETM_CTRL_CONTEXTID_8;
1197 break;
1198 case 16:
1199 tracemode |= ETM_CTRL_CONTEXTID_16;
1200 break;
1201 case 32:
1202 tracemode |= ETM_CTRL_CONTEXTID_32;
1203 break;
1204 default:
1205 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1206 return ERROR_INVALID_ARGUMENTS;
1207 }
1208
1209 bool etmv1_cycle_accurate;
1210 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1211 if (etmv1_cycle_accurate)
1212 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1213
1214 bool etmv1_branch_output;
1215 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1216 if (etmv1_branch_output)
1217 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1218
1219 /* IGNORED:
1220 * - CPRT tracing (coprocessor register transfers)
1221 * - debug request (causes debug entry on trigger)
1222 * - stall on FIFOFULL (preventing tracedata lossage)
1223 */
1224 *mode = tracemode;
1225
1226 return ERROR_OK;
1227 }
1228
1229 COMMAND_HANDLER(handle_etm_tracemode_command)
1230 {
1231 struct target *target = get_current_target(CMD_CTX);
1232 struct arm *arm = target_to_arm(target);
1233 struct etm_context *etm;
1234
1235 if (!is_arm(arm)) {
1236 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1237 return ERROR_FAIL;
1238 }
1239
1240 etm = arm->etm;
1241 if (!etm) {
1242 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1243 return ERROR_FAIL;
1244 }
1245
1246 uint32_t tracemode = etm->control;
1247
1248 switch (CMD_ARGC)
1249 {
1250 case 0:
1251 break;
1252 case 4:
1253 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1254 &tracemode);
1255 break;
1256 default:
1257 command_print(CMD_CTX, "usage: tracemode "
1258 "('none'|'data'|'address'|'all') "
1259 "context_id_bits "
1260 "('enable'|'disable') "
1261 "('enable'|'disable')"
1262 );
1263 return ERROR_FAIL;
1264 }
1265
1266 /**
1267 * todo: fail if parameters were invalid for this hardware,
1268 * or couldn't be written; display actual hardware state...
1269 */
1270
1271 command_print(CMD_CTX, "current tracemode configuration:");
1272
1273 switch (tracemode & ETM_CTRL_TRACE_MASK)
1274 {
1275 default:
1276 command_print(CMD_CTX, "data tracing: none");
1277 break;
1278 case ETM_CTRL_TRACE_DATA:
1279 command_print(CMD_CTX, "data tracing: data only");
1280 break;
1281 case ETM_CTRL_TRACE_ADDR:
1282 command_print(CMD_CTX, "data tracing: address only");
1283 break;
1284 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1285 command_print(CMD_CTX, "data tracing: address and data");
1286 break;
1287 }
1288
1289 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1290 {
1291 case ETM_CTRL_CONTEXTID_NONE:
1292 command_print(CMD_CTX, "contextid tracing: none");
1293 break;
1294 case ETM_CTRL_CONTEXTID_8:
1295 command_print(CMD_CTX, "contextid tracing: 8 bit");
1296 break;
1297 case ETM_CTRL_CONTEXTID_16:
1298 command_print(CMD_CTX, "contextid tracing: 16 bit");
1299 break;
1300 case ETM_CTRL_CONTEXTID_32:
1301 command_print(CMD_CTX, "contextid tracing: 32 bit");
1302 break;
1303 }
1304
1305 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1306 {
1307 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1308 }
1309 else
1310 {
1311 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1312 }
1313
1314 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1315 {
1316 command_print(CMD_CTX, "full branch address output enabled");
1317 }
1318 else
1319 {
1320 command_print(CMD_CTX, "full branch address output disabled");
1321 }
1322
1323 #define TRACEMODE_MASK ( \
1324 ETM_CTRL_CONTEXTID_MASK \
1325 | ETM_CTRL_BRANCH_OUTPUT \
1326 | ETM_CTRL_CYCLE_ACCURATE \
1327 | ETM_CTRL_TRACE_MASK \
1328 )
1329
1330 /* only update ETM_CTRL register if tracemode changed */
1331 if ((etm->control & TRACEMODE_MASK) != tracemode)
1332 {
1333 struct reg *etm_ctrl_reg;
1334
1335 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1336 if (!etm_ctrl_reg)
1337 return ERROR_FAIL;
1338
1339 etm->control &= ~TRACEMODE_MASK;
1340 etm->control |= tracemode & TRACEMODE_MASK;
1341
1342 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1343 etm_store_reg(etm_ctrl_reg);
1344
1345 /* invalidate old trace data */
1346 etm->capture_status = TRACE_IDLE;
1347 if (etm->trace_depth > 0)
1348 {
1349 free(etm->trace_data);
1350 etm->trace_data = NULL;
1351 }
1352 etm->trace_depth = 0;
1353 }
1354
1355 #undef TRACEMODE_MASK
1356
1357 return ERROR_OK;
1358 }
1359
1360 COMMAND_HANDLER(handle_etm_config_command)
1361 {
1362 struct target *target;
1363 struct arm *arm;
1364 uint32_t portmode = 0x0;
1365 struct etm_context *etm_ctx;
1366 int i;
1367
1368 if (CMD_ARGC != 5)
1369 return ERROR_COMMAND_SYNTAX_ERROR;
1370
1371 target = get_target(CMD_ARGV[0]);
1372 if (!target)
1373 {
1374 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1375 return ERROR_FAIL;
1376 }
1377
1378 arm = target_to_arm(target);
1379 if (!is_arm(arm)) {
1380 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1381 target_name(target),
1382 target_type_name(target));
1383 return ERROR_FAIL;
1384 }
1385
1386 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1387 * version we'll be using!! -- so we can't know how to validate
1388 * params yet. "etm config" should likely be *AFTER* hookup...
1389 *
1390 * - Many more widths might be supported ... and we can easily
1391 * check whether our setting "took".
1392 *
1393 * - The "clock" and "mode" bits are interpreted differently.
1394 * See ARM IHI 0014O table 2-17 for the old behavior, and
1395 * table 2-18 for the new. With ETB it's best to specify
1396 * "normal full" ...
1397 */
1398 uint8_t port_width;
1399 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1400 switch (port_width)
1401 {
1402 /* before ETMv3.0 */
1403 case 4:
1404 portmode |= ETM_PORT_4BIT;
1405 break;
1406 case 8:
1407 portmode |= ETM_PORT_8BIT;
1408 break;
1409 case 16:
1410 portmode |= ETM_PORT_16BIT;
1411 break;
1412 /* ETMv3.0 and later*/
1413 case 24:
1414 portmode |= ETM_PORT_24BIT;
1415 break;
1416 case 32:
1417 portmode |= ETM_PORT_32BIT;
1418 break;
1419 case 48:
1420 portmode |= ETM_PORT_48BIT;
1421 break;
1422 case 64:
1423 portmode |= ETM_PORT_64BIT;
1424 break;
1425 case 1:
1426 portmode |= ETM_PORT_1BIT;
1427 break;
1428 case 2:
1429 portmode |= ETM_PORT_2BIT;
1430 break;
1431 default:
1432 command_print(CMD_CTX,
1433 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1434 return ERROR_FAIL;
1435 }
1436
1437 if (strcmp("normal", CMD_ARGV[2]) == 0)
1438 {
1439 portmode |= ETM_PORT_NORMAL;
1440 }
1441 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1442 {
1443 portmode |= ETM_PORT_MUXED;
1444 }
1445 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1446 {
1447 portmode |= ETM_PORT_DEMUXED;
1448 }
1449 else
1450 {
1451 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1452 return ERROR_FAIL;
1453 }
1454
1455 if (strcmp("half", CMD_ARGV[3]) == 0)
1456 {
1457 portmode |= ETM_PORT_HALF_CLOCK;
1458 }
1459 else if (strcmp("full", CMD_ARGV[3]) == 0)
1460 {
1461 portmode |= ETM_PORT_FULL_CLOCK;
1462 }
1463 else
1464 {
1465 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1466 return ERROR_FAIL;
1467 }
1468
1469 etm_ctx = calloc(1, sizeof(struct etm_context));
1470 if (!etm_ctx) {
1471 LOG_DEBUG("out of memory");
1472 return ERROR_FAIL;
1473 }
1474
1475 for (i = 0; etm_capture_drivers[i]; i++)
1476 {
1477 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1478 {
1479 int retval = register_commands(CMD_CTX, NULL,
1480 etm_capture_drivers[i]->commands);
1481 if (ERROR_OK != retval)
1482 {
1483 free(etm_ctx);
1484 return retval;
1485 }
1486
1487 etm_ctx->capture_driver = etm_capture_drivers[i];
1488
1489 break;
1490 }
1491 }
1492
1493 if (!etm_capture_drivers[i])
1494 {
1495 /* no supported capture driver found, don't register an ETM */
1496 free(etm_ctx);
1497 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1498 return ERROR_FAIL;
1499 }
1500
1501 etm_ctx->target = target;
1502 etm_ctx->trace_data = NULL;
1503 etm_ctx->control = portmode;
1504 etm_ctx->core_state = ARM_STATE_ARM;
1505
1506 arm->etm = etm_ctx;
1507
1508 return etm_register_user_commands(CMD_CTX);
1509 }
1510
1511 COMMAND_HANDLER(handle_etm_info_command)
1512 {
1513 struct target *target;
1514 struct arm *arm;
1515 struct etm_context *etm;
1516 struct reg *etm_sys_config_reg;
1517 int max_port_size;
1518 uint32_t config;
1519
1520 target = get_current_target(CMD_CTX);
1521 arm = target_to_arm(target);
1522 if (!is_arm(arm))
1523 {
1524 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1525 return ERROR_FAIL;
1526 }
1527
1528 etm = arm->etm;
1529 if (!etm)
1530 {
1531 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1532 return ERROR_FAIL;
1533 }
1534
1535 command_print(CMD_CTX, "ETM v%d.%d",
1536 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1537 command_print(CMD_CTX, "pairs of address comparators: %i",
1538 (int) (etm->config >> 0) & 0x0f);
1539 command_print(CMD_CTX, "data comparators: %i",
1540 (int) (etm->config >> 4) & 0x0f);
1541 command_print(CMD_CTX, "memory map decoders: %i",
1542 (int) (etm->config >> 8) & 0x1f);
1543 command_print(CMD_CTX, "number of counters: %i",
1544 (int) (etm->config >> 13) & 0x07);
1545 command_print(CMD_CTX, "sequencer %spresent",
1546 (int) (etm->config & (1 << 16)) ? "" : "not ");
1547 command_print(CMD_CTX, "number of ext. inputs: %i",
1548 (int) (etm->config >> 17) & 0x07);
1549 command_print(CMD_CTX, "number of ext. outputs: %i",
1550 (int) (etm->config >> 20) & 0x07);
1551 command_print(CMD_CTX, "FIFO full %spresent",
1552 (int) (etm->config & (1 << 23)) ? "" : "not ");
1553 if (etm->bcd_vers < 0x20)
1554 command_print(CMD_CTX, "protocol version: %i",
1555 (int) (etm->config >> 28) & 0x07);
1556 else {
1557 command_print(CMD_CTX,
1558 "coprocessor and memory access %ssupported",
1559 (etm->config & (1 << 26)) ? "" : "not ");
1560 command_print(CMD_CTX, "trace start/stop %spresent",
1561 (etm->config & (1 << 26)) ? "" : "not ");
1562 command_print(CMD_CTX, "number of context comparators: %i",
1563 (int) (etm->config >> 24) & 0x03);
1564 }
1565
1566 /* SYS_CONFIG isn't present before ETMv1.2 */
1567 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1568 if (!etm_sys_config_reg)
1569 return ERROR_OK;
1570
1571 etm_get_reg(etm_sys_config_reg);
1572 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1573
1574 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1575
1576 max_port_size = config & 0x7;
1577 if (etm->bcd_vers >= 0x30)
1578 max_port_size |= (config >> 6) & 0x08;
1579 switch (max_port_size)
1580 {
1581 /* before ETMv3.0 */
1582 case 0:
1583 max_port_size = 4;
1584 break;
1585 case 1:
1586 max_port_size = 8;
1587 break;
1588 case 2:
1589 max_port_size = 16;
1590 break;
1591 /* ETMv3.0 and later*/
1592 case 3:
1593 max_port_size = 24;
1594 break;
1595 case 4:
1596 max_port_size = 32;
1597 break;
1598 case 5:
1599 max_port_size = 48;
1600 break;
1601 case 6:
1602 max_port_size = 64;
1603 break;
1604 case 8:
1605 max_port_size = 1;
1606 break;
1607 case 9:
1608 max_port_size = 2;
1609 break;
1610 default:
1611 LOG_ERROR("Illegal max_port_size");
1612 return ERROR_FAIL;
1613 }
1614 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1615
1616 if (etm->bcd_vers < 0x30) {
1617 command_print(CMD_CTX, "half-rate clocking %ssupported",
1618 (config & (1 << 3)) ? "" : "not ");
1619 command_print(CMD_CTX, "full-rate clocking %ssupported",
1620 (config & (1 << 4)) ? "" : "not ");
1621 command_print(CMD_CTX, "normal trace format %ssupported",
1622 (config & (1 << 5)) ? "" : "not ");
1623 command_print(CMD_CTX, "multiplex trace format %ssupported",
1624 (config & (1 << 6)) ? "" : "not ");
1625 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1626 (config & (1 << 7)) ? "" : "not ");
1627 } else {
1628 /* REVISIT show which size and format are selected ... */
1629 command_print(CMD_CTX, "current port size %ssupported",
1630 (config & (1 << 10)) ? "" : "not ");
1631 command_print(CMD_CTX, "current trace format %ssupported",
1632 (config & (1 << 11)) ? "" : "not ");
1633 }
1634 if (etm->bcd_vers >= 0x21)
1635 command_print(CMD_CTX, "fetch comparisons %ssupported",
1636 (config & (1 << 17)) ? "not " : "");
1637 command_print(CMD_CTX, "FIFO full %ssupported",
1638 (config & (1 << 8)) ? "" : "not ");
1639
1640 return ERROR_OK;
1641 }
1642
1643 COMMAND_HANDLER(handle_etm_status_command)
1644 {
1645 struct target *target;
1646 struct arm *arm;
1647 struct etm_context *etm;
1648 trace_status_t trace_status;
1649
1650 target = get_current_target(CMD_CTX);
1651 arm = target_to_arm(target);
1652 if (!is_arm(arm))
1653 {
1654 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1655 return ERROR_FAIL;
1656 }
1657
1658 etm = arm->etm;
1659 if (!etm)
1660 {
1661 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1662 return ERROR_FAIL;
1663 }
1664
1665 /* ETM status */
1666 if (etm->bcd_vers >= 0x11) {
1667 struct reg *reg;
1668
1669 reg = etm_reg_lookup(etm, ETM_STATUS);
1670 if (!reg)
1671 return ERROR_FAIL;
1672 if (etm_get_reg(reg) == ERROR_OK) {
1673 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1674
1675 command_print(CMD_CTX, "etm: %s%s%s%s",
1676 /* bit(1) == progbit */
1677 (etm->bcd_vers >= 0x12)
1678 ? ((s & (1 << 1))
1679 ? "disabled" : "enabled")
1680 : "?",
1681 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1682 ? " triggered" : "",
1683 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1684 ? " start/stop" : "",
1685 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1686 ? " untraced-overflow" : "");
1687 } /* else ignore and try showing trace port status */
1688 }
1689
1690 /* Trace Port Driver status */
1691 trace_status = etm->capture_driver->status(etm);
1692 if (trace_status == TRACE_IDLE)
1693 {
1694 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1695 }
1696 else
1697 {
1698 static char *completed = " completed";
1699 static char *running = " is running";
1700 static char *overflowed = ", overflowed";
1701 static char *triggered = ", triggered";
1702
1703 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1704 etm->capture_driver->name,
1705 (trace_status & TRACE_RUNNING) ? running : completed,
1706 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1707 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1708
1709 if (etm->trace_depth > 0)
1710 {
1711 command_print(CMD_CTX, "%i frames of trace data read",
1712 (int)(etm->trace_depth));
1713 }
1714 }
1715
1716 return ERROR_OK;
1717 }
1718
1719 COMMAND_HANDLER(handle_etm_image_command)
1720 {
1721 struct target *target;
1722 struct arm *arm;
1723 struct etm_context *etm_ctx;
1724
1725 if (CMD_ARGC < 1)
1726 {
1727 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1728 return ERROR_FAIL;
1729 }
1730
1731 target = get_current_target(CMD_CTX);
1732 arm = target_to_arm(target);
1733 if (!is_arm(arm))
1734 {
1735 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1736 return ERROR_FAIL;
1737 }
1738
1739 etm_ctx = arm->etm;
1740 if (!etm_ctx)
1741 {
1742 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1743 return ERROR_FAIL;
1744 }
1745
1746 if (etm_ctx->image)
1747 {
1748 image_close(etm_ctx->image);
1749 free(etm_ctx->image);
1750 command_print(CMD_CTX, "previously loaded image found and closed");
1751 }
1752
1753 etm_ctx->image = malloc(sizeof(struct image));
1754 etm_ctx->image->base_address_set = 0;
1755 etm_ctx->image->start_address_set = 0;
1756
1757 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1758 if (CMD_ARGC >= 2)
1759 {
1760 etm_ctx->image->base_address_set = 1;
1761 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1762 }
1763 else
1764 {
1765 etm_ctx->image->base_address_set = 0;
1766 }
1767
1768 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1769 {
1770 free(etm_ctx->image);
1771 etm_ctx->image = NULL;
1772 return ERROR_FAIL;
1773 }
1774
1775 return ERROR_OK;
1776 }
1777
1778 COMMAND_HANDLER(handle_etm_dump_command)
1779 {
1780 struct fileio file;
1781 struct target *target;
1782 struct arm *arm;
1783 struct etm_context *etm_ctx;
1784 uint32_t i;
1785
1786 if (CMD_ARGC != 1)
1787 {
1788 command_print(CMD_CTX, "usage: etm dump <file>");
1789 return ERROR_FAIL;
1790 }
1791
1792 target = get_current_target(CMD_CTX);
1793 arm = target_to_arm(target);
1794 if (!is_arm(arm))
1795 {
1796 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1797 return ERROR_FAIL;
1798 }
1799
1800 etm_ctx = arm->etm;
1801 if (!etm_ctx)
1802 {
1803 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1804 return ERROR_FAIL;
1805 }
1806
1807 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1808 {
1809 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1810 return ERROR_OK;
1811 }
1812
1813 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1814 {
1815 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1816 command_print(CMD_CTX, "trace capture not completed");
1817 return ERROR_FAIL;
1818 }
1819
1820 /* read the trace data if it wasn't read already */
1821 if (etm_ctx->trace_depth == 0)
1822 etm_ctx->capture_driver->read_trace(etm_ctx);
1823
1824 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1825 {
1826 return ERROR_FAIL;
1827 }
1828
1829 fileio_write_u32(&file, etm_ctx->capture_status);
1830 fileio_write_u32(&file, etm_ctx->control);
1831 fileio_write_u32(&file, etm_ctx->trace_depth);
1832
1833 for (i = 0; i < etm_ctx->trace_depth; i++)
1834 {
1835 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1836 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1837 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1838 }
1839
1840 fileio_close(&file);
1841
1842 return ERROR_OK;
1843 }
1844
1845 COMMAND_HANDLER(handle_etm_load_command)
1846 {
1847 struct fileio file;
1848 struct target *target;
1849 struct arm *arm;
1850 struct etm_context *etm_ctx;
1851 uint32_t i;
1852
1853 if (CMD_ARGC != 1)
1854 {
1855 command_print(CMD_CTX, "usage: etm load <file>");
1856 return ERROR_FAIL;
1857 }
1858
1859 target = get_current_target(CMD_CTX);
1860 arm = target_to_arm(target);
1861 if (!is_arm(arm))
1862 {
1863 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1864 return ERROR_FAIL;
1865 }
1866
1867 etm_ctx = arm->etm;
1868 if (!etm_ctx)
1869 {
1870 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1871 return ERROR_FAIL;
1872 }
1873
1874 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1875 {
1876 command_print(CMD_CTX, "trace capture running, stop first");
1877 return ERROR_FAIL;
1878 }
1879
1880 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1881 {
1882 return ERROR_FAIL;
1883 }
1884
1885 if (file.size % 4)
1886 {
1887 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1888 fileio_close(&file);
1889 return ERROR_FAIL;
1890 }
1891
1892 if (etm_ctx->trace_depth > 0)
1893 {
1894 free(etm_ctx->trace_data);
1895 etm_ctx->trace_data = NULL;
1896 }
1897
1898 {
1899 uint32_t tmp;
1900 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1901 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1902 fileio_read_u32(&file, &etm_ctx->trace_depth);
1903 }
1904 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1905 if (etm_ctx->trace_data == NULL)
1906 {
1907 command_print(CMD_CTX, "not enough memory to perform operation");
1908 fileio_close(&file);
1909 return ERROR_FAIL;
1910 }
1911
1912 for (i = 0; i < etm_ctx->trace_depth; i++)
1913 {
1914 uint32_t pipestat, packet, flags;
1915 fileio_read_u32(&file, &pipestat);
1916 fileio_read_u32(&file, &packet);
1917 fileio_read_u32(&file, &flags);
1918 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1919 etm_ctx->trace_data[i].packet = packet & 0xffff;
1920 etm_ctx->trace_data[i].flags = flags;
1921 }
1922
1923 fileio_close(&file);
1924
1925 return ERROR_OK;
1926 }
1927
1928 COMMAND_HANDLER(handle_etm_start_command)
1929 {
1930 struct target *target;
1931 struct arm *arm;
1932 struct etm_context *etm_ctx;
1933 struct reg *etm_ctrl_reg;
1934
1935 target = get_current_target(CMD_CTX);
1936 arm = target_to_arm(target);
1937 if (!is_arm(arm))
1938 {
1939 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1940 return ERROR_FAIL;
1941 }
1942
1943 etm_ctx = arm->etm;
1944 if (!etm_ctx)
1945 {
1946 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1947 return ERROR_FAIL;
1948 }
1949
1950 /* invalidate old tracing data */
1951 etm_ctx->capture_status = TRACE_IDLE;
1952 if (etm_ctx->trace_depth > 0)
1953 {
1954 free(etm_ctx->trace_data);
1955 etm_ctx->trace_data = NULL;
1956 }
1957 etm_ctx->trace_depth = 0;
1958
1959 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1960 if (!etm_ctrl_reg)
1961 return ERROR_FAIL;
1962
1963 etm_get_reg(etm_ctrl_reg);
1964
1965 /* Clear programming bit (10), set port selection bit (11) */
1966 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1967
1968 etm_store_reg(etm_ctrl_reg);
1969 jtag_execute_queue();
1970
1971 etm_ctx->capture_driver->start_capture(etm_ctx);
1972
1973 return ERROR_OK;
1974 }
1975
1976 COMMAND_HANDLER(handle_etm_stop_command)
1977 {
1978 struct target *target;
1979 struct arm *arm;
1980 struct etm_context *etm_ctx;
1981 struct reg *etm_ctrl_reg;
1982
1983 target = get_current_target(CMD_CTX);
1984 arm = target_to_arm(target);
1985 if (!is_arm(arm))
1986 {
1987 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1988 return ERROR_FAIL;
1989 }
1990
1991 etm_ctx = arm->etm;
1992 if (!etm_ctx)
1993 {
1994 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1995 return ERROR_FAIL;
1996 }
1997
1998 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1999 if (!etm_ctrl_reg)
2000 return ERROR_FAIL;
2001
2002 etm_get_reg(etm_ctrl_reg);
2003
2004 /* Set programming bit (10), clear port selection bit (11) */
2005 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2006
2007 etm_store_reg(etm_ctrl_reg);
2008 jtag_execute_queue();
2009
2010 etm_ctx->capture_driver->stop_capture(etm_ctx);
2011
2012 return ERROR_OK;
2013 }
2014
2015 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2016 {
2017 struct target *target;
2018 struct arm *arm;
2019 struct etm_context *etm;
2020
2021 target = get_current_target(CMD_CTX);
2022 arm = target_to_arm(target);
2023 if (!is_arm(arm))
2024 {
2025 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2026 target_name(target));
2027 return ERROR_FAIL;
2028 }
2029
2030 etm = arm->etm;
2031 if (!etm)
2032 {
2033 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2034 target_name(target));
2035 return ERROR_FAIL;
2036 }
2037
2038 if (CMD_ARGC == 1) {
2039 struct reg *etm_ctrl_reg;
2040 bool dbgrq;
2041
2042 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2043 if (!etm_ctrl_reg)
2044 return ERROR_FAIL;
2045
2046 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2047 if (dbgrq)
2048 etm->control |= ETM_CTRL_DBGRQ;
2049 else
2050 etm->control &= ~ETM_CTRL_DBGRQ;
2051
2052 /* etm->control will be written to hardware
2053 * the next time an "etm start" is issued.
2054 */
2055 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2056 }
2057
2058 command_print(CMD_CTX, "ETM: %s debug halt",
2059 (etm->control & ETM_CTRL_DBGRQ)
2060 ? "triggers"
2061 : "does not trigger");
2062 return ERROR_OK;
2063 }
2064
2065 COMMAND_HANDLER(handle_etm_analyze_command)
2066 {
2067 struct target *target;
2068 struct arm *arm;
2069 struct etm_context *etm_ctx;
2070 int retval;
2071
2072 target = get_current_target(CMD_CTX);
2073 arm = target_to_arm(target);
2074 if (!is_arm(arm))
2075 {
2076 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2077 return ERROR_FAIL;
2078 }
2079
2080 etm_ctx = arm->etm;
2081 if (!etm_ctx)
2082 {
2083 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2084 return ERROR_FAIL;
2085 }
2086
2087 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2088 {
2089 switch (retval)
2090 {
2091 case ERROR_ETM_ANALYSIS_FAILED:
2092 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2093 break;
2094 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2095 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2096 break;
2097 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2098 command_print(CMD_CTX, "no image available for trace analysis");
2099 break;
2100 default:
2101 command_print(CMD_CTX, "unknown error: %i", retval);
2102 }
2103 }
2104
2105 return retval;
2106 }
2107
2108 static const struct command_registration etm_config_command_handlers[] = {
2109 {
2110 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2111 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2112 *
2113 * Also, these parameters don't match ETM v3+ modules...
2114 */
2115 .name = "config",
2116 .handler = handle_etm_config_command,
2117 .mode = COMMAND_CONFIG,
2118 .help = "Set up ETM output port.",
2119 .usage = "target port_width port_mode clocking capture_driver",
2120 },
2121 COMMAND_REGISTRATION_DONE
2122 };
2123 const struct command_registration etm_command_handlers[] = {
2124 {
2125 .name = "etm",
2126 .mode = COMMAND_ANY,
2127 .help = "Emebdded Trace Macrocell command group",
2128 .chain = etm_config_command_handlers,
2129 },
2130 COMMAND_REGISTRATION_DONE
2131 };
2132
2133 static const struct command_registration etm_exec_command_handlers[] = {
2134 {
2135 .name = "tracemode",
2136 .handler = handle_etm_tracemode_command,
2137 .mode = COMMAND_EXEC,
2138 .help = "configure/display trace mode",
2139 .usage = "('none'|'data'|'address'|'all') "
2140 "context_id_bits "
2141 "['enable'|'disable'] "
2142 "['enable'|'disable']",
2143 },
2144 {
2145 .name = "info",
2146 .handler = handle_etm_info_command,
2147 .mode = COMMAND_EXEC,
2148 .help = "display info about the current target's ETM",
2149 },
2150 {
2151 .name = "status",
2152 .handler = handle_etm_status_command,
2153 .mode = COMMAND_EXEC,
2154 .help = "display current target's ETM status",
2155 },
2156 {
2157 .name = "start",
2158 .handler = handle_etm_start_command,
2159 .mode = COMMAND_EXEC,
2160 .help = "start ETM trace collection",
2161 },
2162 {
2163 .name = "stop",
2164 .handler = handle_etm_stop_command,
2165 .mode = COMMAND_EXEC,
2166 .help = "stop ETM trace collection",
2167 },
2168 {
2169 .name = "trigger_debug",
2170 .handler = handle_etm_trigger_debug_command,
2171 .mode = COMMAND_EXEC,
2172 .help = "enable/disable debug entry on trigger",
2173 .usage = "['enable'|'disable']",
2174 },
2175 {
2176 .name = "analyze",
2177 .handler = handle_etm_analyze_command,
2178 .mode = COMMAND_EXEC,
2179 .help = "analyze collected ETM trace",
2180 },
2181 {
2182 .name = "image",
2183 .handler = handle_etm_image_command,
2184 .mode = COMMAND_EXEC,
2185 .help = "load image from file with optional offset",
2186 .usage = "filename [offset]",
2187 },
2188 {
2189 .name = "dump",
2190 .handler = handle_etm_dump_command,
2191 .mode = COMMAND_EXEC,
2192 .help = "dump captured trace data to file",
2193 .usage = "filename",
2194 },
2195 {
2196 .name = "load",
2197 .handler = handle_etm_load_command,
2198 .mode = COMMAND_EXEC,
2199 .help = "load trace data for analysis <file>",
2200 },
2201 COMMAND_REGISTRATION_DONE
2202 };
2203
2204 static int etm_register_user_commands(struct command_context *cmd_ctx)
2205 {
2206 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2207 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2208 }
Marex's Cortex A8 development branch