1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
30 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
32 #define NEW(type, variable, items) \
33 type * variable = calloc(1, sizeof(type) * items)
35 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
36 /* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
38 #if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
44 #define ARM11_REGCACHE_MODEREGS 0
45 #define ARM11_REGCACHE_FREGS 0
47 #define ARM11_REGCACHE_COUNT (20 + \
48 23 * ARM11_REGCACHE_MODEREGS + \
49 9 * ARM11_REGCACHE_FREGS)
51 #define ARM11_TAP_DEFAULT TAP_INVALID
54 #define CHECK_RETVAL(action) \
56 int __retval = (action); \
58 if (__retval != ERROR_OK) \
60 LOG_DEBUG("error while calling \"" # action "\""); \
67 struct arm11_register_history
73 enum arm11_debug_version
75 ARM11_DEBUG_V6
= 0x01,
76 ARM11_DEBUG_V61
= 0x02,
77 ARM11_DEBUG_V7
= 0x03,
78 ARM11_DEBUG_V7_CP14
= 0x04,
83 target_t
* target
; /**< Reference back to the owner */
85 /** \name Processor type detection */
88 uint32_t device_id
; /**< IDCODE readout */
89 uint32_t didr
; /**< DIDR readout (debug capabilities) */
90 uint8_t implementor
; /**< DIDR Implementor readout */
92 size_t brp
; /**< Number of Breakpoint Register Pairs from DIDR */
93 size_t wrp
; /**< Number of Watchpoint Register Pairs from DIDR */
95 enum arm11_debug_version
96 debug_version
; /**< ARM debug architecture from DIDR */
99 uint32_t last_dscr
; /**< Last retrieved DSCR value;
100 Use only for debug message generation */
102 bool simulate_reset_on_next_halt
; /**< Perform cleanups of the ARM state on next halt */
104 /** \name Shadow registers to save processor state */
107 reg_t
* reg_list
; /**< target register list */
108 uint32_t reg_values
[ARM11_REGCACHE_COUNT
]; /**< data for registers */
112 struct arm11_register_history
113 reg_history
[ARM11_REGCACHE_COUNT
]; /**< register state before last resume */
115 size_t free_brps
; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
116 size_t free_wrps
; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
119 struct reg_cache
*core_cache
;
124 * ARM11 DBGTAP instructions
126 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
128 enum arm11_instructions
132 ARM11_RESTART
= 0x04,
142 ARM11_DSCR_CORE_HALTED
= 1 << 0,
143 ARM11_DSCR_CORE_RESTARTED
= 1 << 1,
145 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
= 0x0F << 2,
146 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
= 0x00 << 2,
147 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
= 0x01 << 2,
148 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
= 0x02 << 2,
149 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
= 0x03 << 2,
150 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
= 0x04 << 2,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
= 0x05 << 2,
153 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT
= 1 << 6,
154 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
= 1 << 7,
155 ARM11_DSCR_INTERRUPTS_DISABLE
= 1 << 11,
156 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
= 1 << 13,
157 ARM11_DSCR_MODE_SELECT
= 1 << 14,
158 ARM11_DSCR_WDTR_FULL
= 1 << 29,
159 ARM11_DSCR_RDTR_FULL
= 1 << 30,
164 ARM11_CPSR_T
= 1 << 5,
165 ARM11_CPSR_J
= 1 << 24,
176 ARM11_SC7_WCR0
= 112,
179 struct arm11_reg_state
185 int arm11_register_commands(struct command_context_s
*cmd_ctx
);
187 int arm11_read_etm(struct arm11_common
* arm11
, uint8_t address
, uint32_t *value
);
188 int arm11_write_etm(struct arm11_common
* arm11
, uint8_t address
, uint32_t value
);