src/flash/ocl/at91sam7x/samregs.h

   1 /*
   2  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the copyright holders nor the names of
  14  *    contributors may be used to endorse or promote products derived
  15  *    from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
  21  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * For additional information see http://www.ethernut.de/
  31  */
  32
  33
  34 #ifndef samregsH
  35 #define samregsH
  36
  37
  38 /*
  39  * Register definitions below copied from NutOS
  40  */
  41
  42 #define DBGU_BASE       0xFFFFF200      /*!< \brief DBGU base address. */
  43
  44 #define DBGU_CIDR_OFF           0x00000040      /*!< \brief DBGU chip ID register offset. */
  45 #define DBGU_CIDR   (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
  46
  47
  48 #define MC_BASE         0xFFFFFF00      /*!< \brief Memory controller base. */
  49
  50 #define MC_FMR_OFF              0x00000060      /*!< \brief MC flash mode register offset. */
  51 #define MC_FMR      (MC_BASE + MC_FMR_OFF)      /*!< \brief MC flash mode register address. */
  52 #define MC_FRDY                 0x00000001      /*!< \brief Flash ready. */
  53 #define MC_LOCKE                0x00000004      /*!< \brief Lock error. */
  54 #define MC_PROGE                0x00000008      /*!< \brief Programming error. */
  55 #define MC_NEBP                 0x00000080      /*!< \brief No erase before programming. */
  56 #define MC_FWS_MASK             0x00000300      /*!< \brief Flash wait state mask. */
  57 #define MC_FWS_1R2W             0x00000000      /*!< \brief 1 cycle for read, 2 for write operations. */
  58 #define MC_FWS_2R3W             0x00000100      /*!< \brief 2 cycles for read, 3 for write operations. */
  59 #define MC_FWS_3R4W             0x00000200      /*!< \brief 3 cycles for read, 4 for write operations. */
  60 #define MC_FWS_4R4W             0x00000300      /*!< \brief 4 cycles for read and write operations. */
  61 #define MC_FMCN_MASK            0x00FF0000      /*!< \brief Flash microsecond cycle number mask. */
  62
  63 #define MC_FCR_OFF              0x00000064      /*!< \brief MC flash command register offset. */
  64 #define MC_FCR      (MC_BASE + MC_FCR_OFF)      /*!< \brief MC flash command register address. */
  65 #define MC_FCMD_MASK            0x0000000F      /*!< \brief Flash command mask. */
  66 #define MC_FCMD_NOP             0x00000000      /*!< \brief No command. */
  67 #define MC_FCMD_WP              0x00000001      /*!< \brief Write page. */
  68 #define MC_FCMD_SLB             0x00000002      /*!< \brief Set lock bit. */
  69 #define MC_FCMD_WPL             0x00000003      /*!< \brief Write page and lock. */
  70 #define MC_FCMD_CLB             0x00000004      /*!< \brief Clear lock bit. */
  71 #define MC_FCMD_EA              0x00000008      /*!< \brief Erase all. */
  72 #define MC_FCMD_SGPB            0x0000000B      /*!< \brief Set general purpose NVM bit. */
  73 #define MC_FCMD_CGPB            0x0000000D      /*!< \brief Clear general purpose NVM bit. */
  74 #define MC_FCMD_SSB             0x0000000F      /*!< \brief Set security bit. */
  75 #define MC_PAGEN_MASK           0x0003FF00      /*!< \brief Page number mask. */
  76 #define MC_KEY                  0x5A000000      /*!< \brief Writing protect key. */
  77
  78 #define MC_FSR_OFF              0x00000068      /*!< \brief MC flash status register offset. */
  79 #define MC_FSR      (MC_BASE + MC_FSR_OFF)      /*!< \brief MC flash status register address. */
  80 #define MC_SECURITY             0x00000010      /*!< \brief Security bit status. */
  81
  82
  83 #endif