src/flash/ocl/at91sam7x/crt.s

   1 /****************************************************************************
   2 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
   3 *
   4 *  Redistribution and use in source and binary forms, with or without
   5 *  modification, are permitted provided that the following conditions
   6 *  are met:
   7 *
   8 *  1. Redistributions of source code must retain the above copyright
   9 *     notice, this list of conditions and the following disclaimer.
  10 *  2. Redistributions in binary form must reproduce the above copyright
  11 *     notice, this list of conditions and the following disclaimer in the
  12 *     documentation and/or other materials provided with the distribution.
  13 *  3. Neither the name of the author nor the names of its contributors may
  14 *     be used to endorse or promote products derived from this software
  15 *     without specific prior written permission.
  16 *
  17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20 *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21 *  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25 *  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26 *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27 *  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28 *  SUCH DAMAGE.
  29 *
  30 ****************************************************************************
  31 *
  32 *  History:
  33 *
  34 *  18.12.06  mifi   First Version
  35 *                   The hardware initialization is based on the startup file
  36 *                   crtat91sam7x256_rom.S from NutOS 4.2.1.
  37 *                   Therefore partial copyright by egnite Software GmbH.
  38 ****************************************************************************/
  39
  40 /*
  41  * Some defines for the program status registers
  42  */
  43    ARM_MODE_USER  = 0x10      /* Normal User Mode                             */
  44    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
  45    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
  46    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
  47    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
  48    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
  49    ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
  50    ARM_MODE_MASK  = 0x1F
  51
  52    I_BIT          = 0x80      /* disable IRQ when I bit is set */
  53    F_BIT          = 0x40      /* disable IRQ when I bit is set */
  54
  55 /*
  56  * Register Base Address
  57  */
  58    AIC_BASE         = 0xFFFFF000
  59    AIC_EOICR_OFF    = 0x130
  60    AIC_IDCR_OFF     = 0x124
  61
  62    RSTC_MR          = 0xFFFFFD08
  63    RSTC_KEY         = 0xA5000000
  64    RSTC_URSTEN      = 0x00000001
  65
  66    WDT_BASE         = 0xFFFFFD40
  67    WDT_MR_OFF       = 0x00000004
  68    WDT_WDDIS        = 0x00008000
  69
  70    MC_BASE          = 0xFFFFFF00
  71    MC_FMR_OFF       = 0x00000060
  72    MC_FWS_1FWS      = 0x00480100
  73
  74    .section .vectors,"ax"
  75    .code 32
  76
  77 /****************************************************************************/
  78 /*               Vector table and reset entry                               */
  79 /****************************************************************************/
  80 _vectors:
  81    ldr pc, ResetAddr    /* Reset                 */
  82    ldr pc, UndefAddr    /* Undefined instruction */
  83    ldr pc, SWIAddr      /* Software interrupt    */
  84    ldr pc, PAbortAddr   /* Prefetch abort        */
  85    ldr pc, DAbortAddr   /* Data abort            */
  86    ldr pc, ReservedAddr /* Reserved              */
  87    ldr pc, IRQAddr      /* IRQ interrupt         */
  88    ldr pc, FIQAddr      /* FIQ interrupt         */
  89
  90
  91 ResetAddr:     .word ResetHandler
  92 UndefAddr:     .word UndefHandler
  93 SWIAddr:       .word SWIHandler
  94 PAbortAddr:    .word PAbortHandler
  95 DAbortAddr:    .word DAbortHandler
  96 ReservedAddr:  .word 0
  97 IRQAddr:       .word IRQHandler
  98 FIQAddr:       .word FIQHandler
  99
 100    .ltorg
 101
 102    .section .init, "ax"
 103    .code 32
 104
 105    .global ResetHandler
 106    .global ExitFunction
 107    .extern main
 108 /****************************************************************************/
 109 /*                           Reset handler                                  */
 110 /****************************************************************************/
 111 ResetHandler:
 112    /*
 113     * The watchdog is enabled after processor reset. Disable it.
 114     */
 115    ldr   r1, =WDT_BASE
 116    ldr   r0, =WDT_WDDIS
 117    str   r0, [r1, #WDT_MR_OFF]
 118
 119
 120    /*
 121     * Enable user reset: assertion length programmed to 1ms
 122     */
 123    ldr   r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
 124    ldr   r1, =RSTC_MR
 125    str   r0, [r1, #0]
 126
 127
 128    /*
 129     * Use 2 cycles for flash access.
 130     */
 131    ldr   r1, =MC_BASE
 132    ldr   r0, =MC_FWS_1FWS
 133    str   r0, [r1, #MC_FMR_OFF]
 134
 135
 136    /*
 137     * Disable all interrupts. Useful for debugging w/o target reset.
 138     */
 139    ldr   r1, =AIC_BASE
 140    mvn   r0, #0
 141    str   r0, [r1, #AIC_EOICR_OFF]
 142    str   r0, [r1, #AIC_IDCR_OFF]
 143
 144
 145    /*
 146     * Setup a stack for each mode
 147     */
 148    msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
 149    ldr   sp, =__stack_und_end
 150
 151    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
 152    ldr   sp, =__stack_abt_end
 153
 154    msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
 155    ldr   sp, =__stack_fiq_end
 156
 157    msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
 158    ldr   sp, =__stack_irq_end
 159
 160    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
 161    ldr   sp, =__stack_svc_end
 162
 163
 164    /*
 165     * Clear .bss section
 166     */
 167    ldr   r1, =__bss_start
 168    ldr   r2, =__bss_end
 169    ldr   r3, =0
 170 bss_clear_loop:
 171    cmp   r1, r2
 172    strne r3, [r1], #+4
 173    bne   bss_clear_loop
 174
 175
 176    /*
 177     * Jump to main
 178     */
 179    mrs   r0, cpsr
 180    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
 181    msr   cpsr, r0
 182
 183    mov   r0, #0 /* No arguments */
 184    mov   r1, #0 /* No arguments */
 185    ldr   r2, =main
 186    mov   lr, pc
 187    bx    r2     /* And jump... */
 188
 189 ExitFunction:
 190    nop
 191    nop
 192    nop
 193    b ExitFunction
 194
 195
 196 /****************************************************************************/
 197 /*                         Default interrupt handler                        */
 198 /****************************************************************************/
 199
 200 UndefHandler:
 201    b UndefHandler
 202
 203 SWIHandler:
 204    b SWIHandler
 205
 206 PAbortHandler:
 207    b PAbortHandler
 208
 209 DAbortHandler:
 210    b DAbortHandler
 211
 212 IRQHandler:
 213    b IRQHandler
 214
 215 FIQHandler:
 216    b FIQHandler
 217
 218    .weak ExitFunction
 219    .weak UndefHandler, PAbortHandler, DAbortHandler
 220    .weak IRQHandler, FIQHandler
 221
 222    .ltorg
 223 /*** EOF ***/