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flash: less bogus errors
[openocd/cortex.git] / src / flash / nor / cfi.c
blob99676529ba3958c15a09cb21c33e0d2ce74cdd35
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include "cfi.h"
28 #include "non_cfi.h"
29 #include <target/arm.h>
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32
33
34 #define CFI_MAX_BUS_WIDTH 4
35 #define CFI_MAX_CHIP_WIDTH 4
36
37 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
38 #define CFI_MAX_INTEL_CODESIZE 256
39
40 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
41 {
42 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
43 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
44 };
45
46 /* CFI fixups foward declarations */
47 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
48 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
49 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
50
51 /* fixup after reading cmdset 0002 primary query table */
52 static const struct cfi_fixup cfi_0002_fixups[] = {
53 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
54 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
55 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
59 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
63 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
64 {0, 0, NULL, NULL}
65 };
66
67 /* fixup after reading cmdset 0001 primary query table */
68 static const struct cfi_fixup cfi_0001_fixups[] = {
69 {0, 0, NULL, NULL}
70 };
71
72 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
73 {
74 struct cfi_flash_bank *cfi_info = bank->driver_priv;
75 const struct cfi_fixup *f;
76
77 for (f = fixups; f->fixup; f++)
78 {
79 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
80 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
81 {
82 f->fixup(bank, f->param);
83 }
84 }
85 }
86
87 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
88 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
89 {
90 struct cfi_flash_bank *cfi_info = bank->driver_priv;
91
92 if (cfi_info->x16_as_x8) offset *= 2;
93
94 /* while the sector list isn't built, only accesses to sector 0 work */
95 if (sector == 0)
96 return bank->base + offset * bank->bus_width;
97 else
98 {
99 if (!bank->sectors)
100 {
101 LOG_ERROR("BUG: sector list not yet built");
102 exit(-1);
103 }
104 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
105 }
106
107 }
108
109 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
110 {
111 int i;
112
113 /* clear whole buffer, to ensure bits that exceed the bus_width
114 * are set to zero
115 */
116 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
117 cmd_buf[i] = 0;
118
119 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
120 {
121 for (i = bank->bus_width; i > 0; i--)
122 {
123 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
124 }
125 }
126 else
127 {
128 for (i = 1; i <= bank->bus_width; i++)
129 {
130 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
131 }
132 }
133 }
134
135 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
136 {
137 uint8_t command[CFI_MAX_BUS_WIDTH];
138
139 cfi_command(bank, cmd, command);
140 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
141 }
142
143 /* read unsigned 8-bit value from the bank
144 * flash banks are expected to be made of similar chips
145 * the query result should be the same for all
146 */
147 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
148 {
149 struct target *target = bank->target;
150 uint8_t data[CFI_MAX_BUS_WIDTH];
151
152 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
153
154 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
155 return data[0];
156 else
157 return data[bank->bus_width - 1];
158 }
159
160 /* read unsigned 8-bit value from the bank
161 * in case of a bank made of multiple chips,
162 * the individual values are ORed
163 */
164 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
165 {
166 struct target *target = bank->target;
167 uint8_t data[CFI_MAX_BUS_WIDTH];
168 int i;
169
170 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
171
172 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
173 {
174 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
175 data[0] |= data[i];
176
177 return data[0];
178 }
179 else
180 {
181 uint8_t value = 0;
182 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
183 value |= data[bank->bus_width - 1 - i];
184
185 return value;
186 }
187 }
188
189 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
190 {
191 struct target *target = bank->target;
192 struct cfi_flash_bank *cfi_info = bank->driver_priv;
193 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
194
195 if (cfi_info->x16_as_x8)
196 {
197 uint8_t i;
198 for (i = 0;i < 2;i++)
199 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
200 &data[i*bank->bus_width]);
201 }
202 else
203 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
204
205 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
206 return data[0] | data[bank->bus_width] << 8;
207 else
208 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
209 }
210
211 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
212 {
213 struct target *target = bank->target;
214 struct cfi_flash_bank *cfi_info = bank->driver_priv;
215 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
216
217 if (cfi_info->x16_as_x8)
218 {
219 uint8_t i;
220 for (i = 0;i < 4;i++)
221 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
222 &data[i*bank->bus_width]);
223 }
224 else
225 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
226
227 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
228 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
229 else
230 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
231 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
232 }
233
234 static void cfi_intel_clear_status_register(struct flash_bank *bank)
235 {
236 struct target *target = bank->target;
237
238 if (target->state != TARGET_HALTED)
239 {
240 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
241 exit(-1);
242 }
243
244 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
245 }
246
247 static uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
248 {
249 uint8_t status;
250
251 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
252 {
253 LOG_DEBUG("status: 0x%x", status);
254 alive_sleep(1);
255 }
256
257 /* mask out bit 0 (reserved) */
258 status = status & 0xfe;
259
260 LOG_DEBUG("status: 0x%x", status);
261
262 if ((status & 0x80) != 0x80)
263 {
264 LOG_ERROR("timeout while waiting for WSM to become ready");
265 }
266 else if (status != 0x80)
267 {
268 LOG_ERROR("status register: 0x%x", status);
269 if (status & 0x2)
270 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
271 if (status & 0x4)
272 LOG_ERROR("Program suspended");
273 if (status & 0x8)
274 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
275 if (status & 0x10)
276 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
277 if (status & 0x20)
278 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
279 if (status & 0x40)
280 LOG_ERROR("Block Erase Suspended");
281
282 cfi_intel_clear_status_register(bank);
283 }
284
285 return status;
286 }
287
288 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
289 {
290 uint8_t status, oldstatus;
291 struct cfi_flash_bank *cfi_info = bank->driver_priv;
292
293 oldstatus = cfi_get_u8(bank, 0, 0x0);
294
295 do {
296 status = cfi_get_u8(bank, 0, 0x0);
297 if ((status ^ oldstatus) & 0x40) {
298 if (status & cfi_info->status_poll_mask & 0x20) {
299 oldstatus = cfi_get_u8(bank, 0, 0x0);
300 status = cfi_get_u8(bank, 0, 0x0);
301 if ((status ^ oldstatus) & 0x40) {
302 LOG_ERROR("dq5 timeout, status: 0x%x", status);
303 return(ERROR_FLASH_OPERATION_FAILED);
304 } else {
305 LOG_DEBUG("status: 0x%x", status);
306 return(ERROR_OK);
307 }
308 }
309 } else { /* no toggle: finished, OK */
310 LOG_DEBUG("status: 0x%x", status);
311 return(ERROR_OK);
312 }
313
314 oldstatus = status;
315 alive_sleep(1);
316 } while (timeout-- > 0);
317
318 LOG_ERROR("timeout, status: 0x%x", status);
319
320 return(ERROR_FLASH_BUSY);
321 }
322
323 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
324 {
325 int retval;
326 struct cfi_flash_bank *cfi_info = bank->driver_priv;
327 struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
328
329 cfi_info->pri_ext = pri_ext;
330
331 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
332 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
333 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
334
335 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
336 {
337 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
338 {
339 return retval;
340 }
341 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
342 {
343 return retval;
344 }
345 LOG_ERROR("Could not read bank flash bank information");
346 return ERROR_FLASH_BANK_INVALID;
347 }
348
349 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
350 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
351
352 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
353
354 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
355 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
356 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
357
358 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
359 pri_ext->feature_support,
360 pri_ext->suspend_cmd_support,
361 pri_ext->blk_status_reg_mask);
362
363 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
364 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
365
366 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
367 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
368 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
369
370 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
371 if (pri_ext->num_protection_fields != 1)
372 {
373 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
374 }
375
376 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
377 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
378 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
379
380 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
381
382 return ERROR_OK;
383 }
384
385 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
386 {
387 int retval;
388 struct cfi_flash_bank *cfi_info = bank->driver_priv;
389 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
390
391 cfi_info->pri_ext = pri_ext;
392
393 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
394 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
395 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
396
397 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
398 {
399 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
400 {
401 return retval;
402 }
403 LOG_ERROR("Could not read spansion bank information");
404 return ERROR_FLASH_BANK_INVALID;
405 }
406
407 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
408 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
409
410 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
411
412 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
413 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
414 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
415 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
416 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
417 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
418 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
419 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
420 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
421 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
422 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
423
424 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
425 pri_ext->EraseSuspend, pri_ext->BlkProt);
426
427 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
428 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
429
430 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
431
432
433 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
434 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
435 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
436
437 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
438
439 /* default values for implementation specific workarounds */
440 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
441 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
442 pri_ext->_reversed_geometry = 0;
443
444 return ERROR_OK;
445 }
446
447 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
448 {
449 int retval;
450 struct cfi_atmel_pri_ext atmel_pri_ext;
451 struct cfi_flash_bank *cfi_info = bank->driver_priv;
452 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
453
454 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
455 * but a different primary extended query table.
456 * We read the atmel table, and prepare a valid AMD/Spansion query table.
457 */
458
459 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
460
461 cfi_info->pri_ext = pri_ext;
462
463 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
464 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
465 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
466
467 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
468 {
469 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
470 {
471 return retval;
472 }
473 LOG_ERROR("Could not read atmel bank information");
474 return ERROR_FLASH_BANK_INVALID;
475 }
476
477 pri_ext->pri[0] = atmel_pri_ext.pri[0];
478 pri_ext->pri[1] = atmel_pri_ext.pri[1];
479 pri_ext->pri[2] = atmel_pri_ext.pri[2];
480
481 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
482 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
483
484 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
485
486 pri_ext->major_version = atmel_pri_ext.major_version;
487 pri_ext->minor_version = atmel_pri_ext.minor_version;
488
489 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
490 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
491 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
492 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
493
494 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
495 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
496
497 if (atmel_pri_ext.features & 0x02)
498 pri_ext->EraseSuspend = 2;
499
500 if (atmel_pri_ext.bottom_boot)
501 pri_ext->TopBottom = 2;
502 else
503 pri_ext->TopBottom = 3;
504
505 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
506 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
507
508 return ERROR_OK;
509 }
510
511 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
512 {
513 struct cfi_flash_bank *cfi_info = bank->driver_priv;
514
515 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
516 {
517 return cfi_read_atmel_pri_ext(bank);
518 }
519 else
520 {
521 return cfi_read_spansion_pri_ext(bank);
522 }
523 }
524
525 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
526 {
527 int printed;
528 struct cfi_flash_bank *cfi_info = bank->driver_priv;
529 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
530
531 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
532 buf += printed;
533 buf_size -= printed;
534
535 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
536 pri_ext->pri[1], pri_ext->pri[2],
537 pri_ext->major_version, pri_ext->minor_version);
538 buf += printed;
539 buf_size -= printed;
540
541 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
542 (pri_ext->SiliconRevision) >> 2,
543 (pri_ext->SiliconRevision) & 0x03);
544 buf += printed;
545 buf_size -= printed;
546
547 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
548 pri_ext->EraseSuspend,
549 pri_ext->BlkProt);
550 buf += printed;
551 buf_size -= printed;
552
553 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
554 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
555 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
556
557 return ERROR_OK;
558 }
559
560 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
561 {
562 int printed;
563 struct cfi_flash_bank *cfi_info = bank->driver_priv;
564 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
565
566 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
567 buf += printed;
568 buf_size -= printed;
569
570 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
571 buf += printed;
572 buf_size -= printed;
573
574 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
575 buf += printed;
576 buf_size -= printed;
577
578 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
579 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
580 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
581 buf += printed;
582 buf_size -= printed;
583
584 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
585
586 return ERROR_OK;
587 }
588
589 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
590 */
591 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
592 {
593 struct cfi_flash_bank *cfi_info;
594
595 if (CMD_ARGC < 6)
596 {
597 LOG_WARNING("incomplete flash_bank cfi configuration");
598 return ERROR_FLASH_BANK_INVALID;
599 }
600
601 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
602 || (bank->bus_width > CFI_MAX_BUS_WIDTH))
603 {
604 LOG_ERROR("chip and bus width have to specified in bytes");
605 return ERROR_FLASH_BANK_INVALID;
606 }
607
608 cfi_info = malloc(sizeof(struct cfi_flash_bank));
609 cfi_info->probed = 0;
610 bank->driver_priv = cfi_info;
611
612 cfi_info->write_algorithm = NULL;
613
614 cfi_info->x16_as_x8 = 0;
615 cfi_info->jedec_probe = 0;
616 cfi_info->not_cfi = 0;
617
618 for (unsigned i = 6; i < CMD_ARGC; i++)
619 {
620 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
621 {
622 cfi_info->x16_as_x8 = 1;
623 }
624 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
625 {
626 cfi_info->jedec_probe = 1;
627 }
628 }
629
630 cfi_info->write_algorithm = NULL;
631
632 /* bank wasn't probed yet */
633 cfi_info->qry[0] = -1;
634
635 return ERROR_OK;
636 }
637
638 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
639 {
640 int retval;
641 struct cfi_flash_bank *cfi_info = bank->driver_priv;
642 int i;
643
644 cfi_intel_clear_status_register(bank);
645
646 for (i = first; i <= last; i++)
647 {
648 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
649 {
650 return retval;
651 }
652
653 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
654 {
655 return retval;
656 }
657
658 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
659 bank->sectors[i].is_erased = 1;
660 else
661 {
662 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
663 {
664 return retval;
665 }
666
667 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
668 return ERROR_FLASH_OPERATION_FAILED;
669 }
670 }
671
672 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
673 }
674
675 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
676 {
677 int retval;
678 struct cfi_flash_bank *cfi_info = bank->driver_priv;
679 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
680 int i;
681
682 for (i = first; i <= last; i++)
683 {
684 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
685 {
686 return retval;
687 }
688
689 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
690 {
691 return retval;
692 }
693
694 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
695 {
696 return retval;
697 }
698
699 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
700 {
701 return retval;
702 }
703
704 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
705 {
706 return retval;
707 }
708
709 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
710 {
711 return retval;
712 }
713
714 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
715 bank->sectors[i].is_erased = 1;
716 else
717 {
718 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
719 {
720 return retval;
721 }
722
723 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
724 return ERROR_FLASH_OPERATION_FAILED;
725 }
726 }
727
728 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
729 }
730
731 static int cfi_erase(struct flash_bank *bank, int first, int last)
732 {
733 struct cfi_flash_bank *cfi_info = bank->driver_priv;
734
735 if (bank->target->state != TARGET_HALTED)
736 {
737 LOG_ERROR("Target not halted");
738 return ERROR_TARGET_NOT_HALTED;
739 }
740
741 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
742 {
743 return ERROR_FLASH_SECTOR_INVALID;
744 }
745
746 if (cfi_info->qry[0] != 'Q')
747 return ERROR_FLASH_BANK_NOT_PROBED;
748
749 switch (cfi_info->pri_id)
750 {
751 case 1:
752 case 3:
753 return cfi_intel_erase(bank, first, last);
754 break;
755 case 2:
756 return cfi_spansion_erase(bank, first, last);
757 break;
758 default:
759 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
760 break;
761 }
762
763 return ERROR_OK;
764 }
765
766 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
767 {
768 int retval;
769 struct cfi_flash_bank *cfi_info = bank->driver_priv;
770 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
771 struct target *target = bank->target; /* FIXME: to be removed */
772 uint8_t command[CFI_MAX_BUS_WIDTH]; /* FIXME: to be removed */
773 int retry = 0;
774 int i;
775
776 /* if the device supports neither legacy lock/unlock (bit 3) nor
777 * instant individual block locking (bit 5).
778 */
779 if (!(pri_ext->feature_support & 0x28))
780 return ERROR_FLASH_OPERATION_FAILED;
781
782 cfi_intel_clear_status_register(bank);
783
784 for (i = first; i <= last; i++)
785 {
786 cfi_command(bank, 0x60, command); /* FIXME: to be removed */
787 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
788 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
789 {
790 return retval;
791 }
792 if (set)
793 {
794 cfi_command(bank, 0x01, command); /* FIXME: to be removed */
795 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
796 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
797 {
798 return retval;
799 }
800 bank->sectors[i].is_protected = 1;
801 }
802 else
803 {
804 cfi_command(bank, 0xd0, command); /* FIXME: to be removed */
805 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
806 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
807 {
808 return retval;
809 }
810 bank->sectors[i].is_protected = 0;
811 }
812
813 /* instant individual block locking doesn't require reading of the status register */
814 if (!(pri_ext->feature_support & 0x20))
815 {
816 /* Clear lock bits operation may take up to 1.4s */
817 cfi_intel_wait_status_busy(bank, 1400);
818 }
819 else
820 {
821 uint8_t block_status;
822 /* read block lock bit, to verify status */
823 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
824 {
825 return retval;
826 }
827 block_status = cfi_get_u8(bank, i, 0x2);
828
829 if ((block_status & 0x1) != set)
830 {
831 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
832 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
833 {
834 return retval;
835 }
836 cfi_intel_wait_status_busy(bank, 10);
837
838 if (retry > 10)
839 return ERROR_FLASH_OPERATION_FAILED;
840 else
841 {
842 i--;
843 retry++;
844 }
845 }
846 }
847 }
848
849 /* if the device doesn't support individual block lock bits set/clear,
850 * all blocks have been unlocked in parallel, so we set those that should be protected
851 */
852 if ((!set) && (!(pri_ext->feature_support & 0x20)))
853 {
854 for (i = 0; i < bank->num_sectors; i++)
855 {
856 if (bank->sectors[i].is_protected == 1)
857 {
858 cfi_intel_clear_status_register(bank);
859
860 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
861 {
862 return retval;
863 }
864
865 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
866 {
867 return retval;
868 }
869
870 cfi_intel_wait_status_busy(bank, 100);
871 }
872 }
873 }
874
875 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
876 }
877
878 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
879 {
880 struct cfi_flash_bank *cfi_info = bank->driver_priv;
881
882 if (bank->target->state != TARGET_HALTED)
883 {
884 LOG_ERROR("Target not halted");
885 return ERROR_TARGET_NOT_HALTED;
886 }
887
888 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
889 {
890 return ERROR_FLASH_SECTOR_INVALID;
891 }
892
893 if (cfi_info->qry[0] != 'Q')
894 return ERROR_FLASH_BANK_NOT_PROBED;
895
896 switch (cfi_info->pri_id)
897 {
898 case 1:
899 case 3:
900 cfi_intel_protect(bank, set, first, last);
901 break;
902 default:
903 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
904 break;
905 }
906
907 return ERROR_OK;
908 }
909
910 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
911 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
912 {
913 /* struct target *target = bank->target; */
914
915 int i;
916
917 /* NOTE:
918 * The data to flash must not be changed in endian! We write a bytestrem in
919 * target byte order already. Only the control and status byte lane of the flash
920 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
921 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
922 */
923
924 #if 0
925 if (target->endianness == TARGET_LITTLE_ENDIAN)
926 {
927 #endif
928 /* shift bytes */
929 for (i = 0; i < bank->bus_width - 1; i++)
930 word[i] = word[i + 1];
931 word[bank->bus_width - 1] = byte;
932 #if 0
933 }
934 else
935 {
936 /* shift bytes */
937 for (i = bank->bus_width - 1; i > 0; i--)
938 word[i] = word[i - 1];
939 word[0] = byte;
940 }
941 #endif
942 }
943
944 /* Convert code image to target endian */
945 /* FIXME create general block conversion fcts in target.c?) */
946 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
947 {
948 uint32_t i;
949 for (i = 0; i< count; i++)
950 {
951 target_buffer_set_u32(target, dest, *src);
952 dest += 4;
953 src++;
954 }
955 }
956
957 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
958 {
959 struct target *target = bank->target;
960
961 uint8_t buf[CFI_MAX_BUS_WIDTH];
962 cfi_command(bank, cmd, buf);
963 switch (bank->bus_width)
964 {
965 case 1 :
966 return buf[0];
967 break;
968 case 2 :
969 return target_buffer_get_u16(target, buf);
970 break;
971 case 4 :
972 return target_buffer_get_u32(target, buf);
973 break;
974 default :
975 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
976 return 0;
977 }
978 }
979
980 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
981 {
982 struct cfi_flash_bank *cfi_info = bank->driver_priv;
983 struct target *target = bank->target;
984 struct reg_param reg_params[7];
985 struct arm_algorithm armv4_5_info;
986 struct working_area *source;
987 uint32_t buffer_size = 32768;
988 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
989
990 /* algorithm register usage:
991 * r0: source address (in RAM)
992 * r1: target address (in Flash)
993 * r2: count
994 * r3: flash write command
995 * r4: status byte (returned to host)
996 * r5: busy test pattern
997 * r6: error test pattern
998 */
999
1000 static const uint32_t word_32_code[] = {
1001 0xe4904004, /* loop: ldr r4, [r0], #4 */
1002 0xe5813000, /* str r3, [r1] */
1003 0xe5814000, /* str r4, [r1] */
1004 0xe5914000, /* busy: ldr r4, [r1] */
1005 0xe0047005, /* and r7, r4, r5 */
1006 0xe1570005, /* cmp r7, r5 */
1007 0x1afffffb, /* bne busy */
1008 0xe1140006, /* tst r4, r6 */
1009 0x1a000003, /* bne done */
1010 0xe2522001, /* subs r2, r2, #1 */
1011 0x0a000001, /* beq done */
1012 0xe2811004, /* add r1, r1 #4 */
1013 0xeafffff2, /* b loop */
1014 0xeafffffe /* done: b -2 */
1015 };
1016
1017 static const uint32_t word_16_code[] = {
1018 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1019 0xe1c130b0, /* strh r3, [r1] */
1020 0xe1c140b0, /* strh r4, [r1] */
1021 0xe1d140b0, /* busy ldrh r4, [r1] */
1022 0xe0047005, /* and r7, r4, r5 */
1023 0xe1570005, /* cmp r7, r5 */
1024 0x1afffffb, /* bne busy */
1025 0xe1140006, /* tst r4, r6 */
1026 0x1a000003, /* bne done */
1027 0xe2522001, /* subs r2, r2, #1 */
1028 0x0a000001, /* beq done */
1029 0xe2811002, /* add r1, r1 #2 */
1030 0xeafffff2, /* b loop */
1031 0xeafffffe /* done: b -2 */
1032 };
1033
1034 static const uint32_t word_8_code[] = {
1035 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1036 0xe5c13000, /* strb r3, [r1] */
1037 0xe5c14000, /* strb r4, [r1] */
1038 0xe5d14000, /* busy ldrb r4, [r1] */
1039 0xe0047005, /* and r7, r4, r5 */
1040 0xe1570005, /* cmp r7, r5 */
1041 0x1afffffb, /* bne busy */
1042 0xe1140006, /* tst r4, r6 */
1043 0x1a000003, /* bne done */
1044 0xe2522001, /* subs r2, r2, #1 */
1045 0x0a000001, /* beq done */
1046 0xe2811001, /* add r1, r1 #1 */
1047 0xeafffff2, /* b loop */
1048 0xeafffffe /* done: b -2 */
1049 };
1050 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1051 const uint32_t *target_code_src;
1052 uint32_t target_code_size;
1053 int retval = ERROR_OK;
1054
1055
1056 cfi_intel_clear_status_register(bank);
1057
1058 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1059 armv4_5_info.core_mode = ARM_MODE_SVC;
1060 armv4_5_info.core_state = ARM_STATE_ARM;
1061
1062 /* If we are setting up the write_algorith, we need target_code_src */
1063 /* if not we only need target_code_size. */
1064
1065 /* However, we don't want to create multiple code paths, so we */
1066 /* do the unecessary evaluation of target_code_src, which the */
1067 /* compiler will probably nicely optimize away if not needed */
1068
1069 /* prepare algorithm code for target endian */
1070 switch (bank->bus_width)
1071 {
1072 case 1 :
1073 target_code_src = word_8_code;
1074 target_code_size = sizeof(word_8_code);
1075 break;
1076 case 2 :
1077 target_code_src = word_16_code;
1078 target_code_size = sizeof(word_16_code);
1079 break;
1080 case 4 :
1081 target_code_src = word_32_code;
1082 target_code_size = sizeof(word_32_code);
1083 break;
1084 default:
1085 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1086 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1087 }
1088
1089 /* flash write code */
1090 if (!cfi_info->write_algorithm)
1091 {
1092 if (target_code_size > sizeof(target_code))
1093 {
1094 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1095 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1096 }
1097 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1098
1099 /* Get memory for block write handler */
1100 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1101 if (retval != ERROR_OK)
1102 {
1103 LOG_WARNING("No working area available, can't do block memory writes");
1104 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1105 };
1106
1107 /* write algorithm code to working area */
1108 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1109 if (retval != ERROR_OK)
1110 {
1111 LOG_ERROR("Unable to write block write code to target");
1112 goto cleanup;
1113 }
1114 }
1115
1116 /* Get a workspace buffer for the data to flash starting with 32k size.
1117 Half size until buffer would be smaller 256 Bytem then fail back */
1118 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1119 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1120 {
1121 buffer_size /= 2;
1122 if (buffer_size <= 256)
1123 {
1124 LOG_WARNING("no large enough working area available, can't do block memory writes");
1125 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126 goto cleanup;
1127 }
1128 };
1129
1130 /* setup algo registers */
1131 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1132 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1133 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1134 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1135 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1136 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1137 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1138
1139 /* prepare command and status register patterns */
1140 write_command_val = cfi_command_val(bank, 0x40);
1141 busy_pattern_val = cfi_command_val(bank, 0x80);
1142 error_pattern_val = cfi_command_val(bank, 0x7e);
1143
1144 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1145
1146 /* Programming main loop */
1147 while (count > 0)
1148 {
1149 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1150 uint32_t wsm_error;
1151
1152 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1153 {
1154 goto cleanup;
1155 }
1156
1157 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1158 buf_set_u32(reg_params[1].value, 0, 32, address);
1159 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1160
1161 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1162 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1163 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1164
1165 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1166
1167 /* Execute algorithm, assume breakpoint for last instruction */
1168 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1169 cfi_info->write_algorithm->address,
1170 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1171 10000, /* 10s should be enough for max. 32k of data */
1172 &armv4_5_info);
1173
1174 /* On failure try a fall back to direct word writes */
1175 if (retval != ERROR_OK)
1176 {
1177 cfi_intel_clear_status_register(bank);
1178 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1179 retval = ERROR_FLASH_OPERATION_FAILED;
1180 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1181 /* FIXME To allow fall back or recovery, we must save the actual status
1182 somewhere, so that a higher level code can start recovery. */
1183 goto cleanup;
1184 }
1185
1186 /* Check return value from algo code */
1187 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1188 if (wsm_error)
1189 {
1190 /* read status register (outputs debug inforation) */
1191 cfi_intel_wait_status_busy(bank, 100);
1192 cfi_intel_clear_status_register(bank);
1193 retval = ERROR_FLASH_OPERATION_FAILED;
1194 goto cleanup;
1195 }
1196
1197 buffer += thisrun_count;
1198 address += thisrun_count;
1199 count -= thisrun_count;
1200 }
1201
1202 /* free up resources */
1203 cleanup:
1204 if (source)
1205 target_free_working_area(target, source);
1206
1207 if (cfi_info->write_algorithm)
1208 {
1209 target_free_working_area(target, cfi_info->write_algorithm);
1210 cfi_info->write_algorithm = NULL;
1211 }
1212
1213 destroy_reg_param(&reg_params[0]);
1214 destroy_reg_param(&reg_params[1]);
1215 destroy_reg_param(&reg_params[2]);
1216 destroy_reg_param(&reg_params[3]);
1217 destroy_reg_param(&reg_params[4]);
1218 destroy_reg_param(&reg_params[5]);
1219 destroy_reg_param(&reg_params[6]);
1220
1221 return retval;
1222 }
1223
1224 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1225 {
1226 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1227 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1228 struct target *target = bank->target;
1229 struct reg_param reg_params[10];
1230 struct arm_algorithm armv4_5_info;
1231 struct working_area *source;
1232 uint32_t buffer_size = 32768;
1233 uint32_t status;
1234 int retval, retvaltemp;
1235 int exit_code = ERROR_OK;
1236
1237 /* input parameters - */
1238 /* R0 = source address */
1239 /* R1 = destination address */
1240 /* R2 = number of writes */
1241 /* R3 = flash write command */
1242 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1243 /* output parameters - */
1244 /* R5 = 0x80 ok 0x00 bad */
1245 /* temp registers - */
1246 /* R6 = value read from flash to test status */
1247 /* R7 = holding register */
1248 /* unlock registers - */
1249 /* R8 = unlock1_addr */
1250 /* R9 = unlock1_cmd */
1251 /* R10 = unlock2_addr */
1252 /* R11 = unlock2_cmd */
1253
1254 static const uint32_t word_32_code[] = {
1255 /* 00008100 <sp_32_code>: */
1256 0xe4905004, /* ldr r5, [r0], #4 */
1257 0xe5889000, /* str r9, [r8] */
1258 0xe58ab000, /* str r11, [r10] */
1259 0xe5883000, /* str r3, [r8] */
1260 0xe5815000, /* str r5, [r1] */
1261 0xe1a00000, /* nop */
1262 /* */
1263 /* 00008110 <sp_32_busy>: */
1264 0xe5916000, /* ldr r6, [r1] */
1265 0xe0257006, /* eor r7, r5, r6 */
1266 0xe0147007, /* ands r7, r4, r7 */
1267 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1268 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1269 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1270 0xe5916000, /* ldr r6, [r1] */
1271 0xe0257006, /* eor r7, r5, r6 */
1272 0xe0147007, /* ands r7, r4, r7 */
1273 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1274 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1275 0x1a000004, /* bne 8154 <sp_32_done> */
1276 /* */
1277 /* 00008140 <sp_32_cont>: */
1278 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1279 0x03a05080, /* moveq r5, #128 ; 0x80 */
1280 0x0a000001, /* beq 8154 <sp_32_done> */
1281 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1282 0xeaffffe8, /* b 8100 <sp_32_code> */
1283 /* */
1284 /* 00008154 <sp_32_done>: */
1285 0xeafffffe /* b 8154 <sp_32_done> */
1286 };
1287
1288 static const uint32_t word_16_code[] = {
1289 /* 00008158 <sp_16_code>: */
1290 0xe0d050b2, /* ldrh r5, [r0], #2 */
1291 0xe1c890b0, /* strh r9, [r8] */
1292 0xe1cab0b0, /* strh r11, [r10] */
1293 0xe1c830b0, /* strh r3, [r8] */
1294 0xe1c150b0, /* strh r5, [r1] */
1295 0xe1a00000, /* nop (mov r0,r0) */
1296 /* */
1297 /* 00008168 <sp_16_busy>: */
1298 0xe1d160b0, /* ldrh r6, [r1] */
1299 0xe0257006, /* eor r7, r5, r6 */
1300 0xe0147007, /* ands r7, r4, r7 */
1301 0x0a000007, /* beq 8198 <sp_16_cont> */
1302 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1303 0x0afffff9, /* beq 8168 <sp_16_busy> */
1304 0xe1d160b0, /* ldrh r6, [r1] */
1305 0xe0257006, /* eor r7, r5, r6 */
1306 0xe0147007, /* ands r7, r4, r7 */
1307 0x0a000001, /* beq 8198 <sp_16_cont> */
1308 0xe3a05000, /* mov r5, #0 ; 0x0 */
1309 0x1a000004, /* bne 81ac <sp_16_done> */
1310 /* */
1311 /* 00008198 <sp_16_cont>: */
1312 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1313 0x03a05080, /* moveq r5, #128 ; 0x80 */
1314 0x0a000001, /* beq 81ac <sp_16_done> */
1315 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1316 0xeaffffe8, /* b 8158 <sp_16_code> */
1317 /* */
1318 /* 000081ac <sp_16_done>: */
1319 0xeafffffe /* b 81ac <sp_16_done> */
1320 };
1321
1322 static const uint32_t word_16_code_dq7only[] = {
1323 /* <sp_16_code>: */
1324 0xe0d050b2, /* ldrh r5, [r0], #2 */
1325 0xe1c890b0, /* strh r9, [r8] */
1326 0xe1cab0b0, /* strh r11, [r10] */
1327 0xe1c830b0, /* strh r3, [r8] */
1328 0xe1c150b0, /* strh r5, [r1] */
1329 0xe1a00000, /* nop (mov r0,r0) */
1330 /* */
1331 /* <sp_16_busy>: */
1332 0xe1d160b0, /* ldrh r6, [r1] */
1333 0xe0257006, /* eor r7, r5, r6 */
1334 0xe2177080, /* ands r7, #0x80 */
1335 0x1afffffb, /* bne 8168 <sp_16_busy> */
1336 /* */
1337 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1338 0x03a05080, /* moveq r5, #128 ; 0x80 */
1339 0x0a000001, /* beq 81ac <sp_16_done> */
1340 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1341 0xeafffff0, /* b 8158 <sp_16_code> */
1342 /* */
1343 /* 000081ac <sp_16_done>: */
1344 0xeafffffe /* b 81ac <sp_16_done> */
1345 };
1346
1347 static const uint32_t word_8_code[] = {
1348 /* 000081b0 <sp_16_code_end>: */
1349 0xe4d05001, /* ldrb r5, [r0], #1 */
1350 0xe5c89000, /* strb r9, [r8] */
1351 0xe5cab000, /* strb r11, [r10] */
1352 0xe5c83000, /* strb r3, [r8] */
1353 0xe5c15000, /* strb r5, [r1] */
1354 0xe1a00000, /* nop (mov r0,r0) */
1355 /* */
1356 /* 000081c0 <sp_8_busy>: */
1357 0xe5d16000, /* ldrb r6, [r1] */
1358 0xe0257006, /* eor r7, r5, r6 */
1359 0xe0147007, /* ands r7, r4, r7 */
1360 0x0a000007, /* beq 81f0 <sp_8_cont> */
1361 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1362 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1363 0xe5d16000, /* ldrb r6, [r1] */
1364 0xe0257006, /* eor r7, r5, r6 */
1365 0xe0147007, /* ands r7, r4, r7 */
1366 0x0a000001, /* beq 81f0 <sp_8_cont> */
1367 0xe3a05000, /* mov r5, #0 ; 0x0 */
1368 0x1a000004, /* bne 8204 <sp_8_done> */
1369 /* */
1370 /* 000081f0 <sp_8_cont>: */
1371 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1372 0x03a05080, /* moveq r5, #128 ; 0x80 */
1373 0x0a000001, /* beq 8204 <sp_8_done> */
1374 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1375 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1376 /* */
1377 /* 00008204 <sp_8_done>: */
1378 0xeafffffe /* b 8204 <sp_8_done> */
1379 };
1380
1381 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1382 armv4_5_info.core_mode = ARM_MODE_SVC;
1383 armv4_5_info.core_state = ARM_STATE_ARM;
1384
1385 int target_code_size;
1386 const uint32_t *target_code_src;
1387
1388 switch (bank->bus_width)
1389 {
1390 case 1 :
1391 target_code_src = word_8_code;
1392 target_code_size = sizeof(word_8_code);
1393 break;
1394 case 2 :
1395 /* Check for DQ5 support */
1396 if( cfi_info->status_poll_mask & (1 << 5) )
1397 {
1398 target_code_src = word_16_code;
1399 target_code_size = sizeof(word_16_code);
1400 }
1401 else
1402 {
1403 /* No DQ5 support. Use DQ7 DATA# polling only. */
1404 target_code_src = word_16_code_dq7only;
1405 target_code_size = sizeof(word_16_code_dq7only);
1406 }
1407 break;
1408 case 4 :
1409 target_code_src = word_32_code;
1410 target_code_size = sizeof(word_32_code);
1411 break;
1412 default:
1413 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1414 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1415 }
1416
1417 /* flash write code */
1418 if (!cfi_info->write_algorithm)
1419 {
1420 uint8_t *target_code;
1421
1422 /* convert bus-width dependent algorithm code to correct endiannes */
1423 target_code = malloc(target_code_size);
1424 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1425
1426 /* allocate working area */
1427 retval = target_alloc_working_area(target, target_code_size,
1428 &cfi_info->write_algorithm);
1429 if (retval != ERROR_OK)
1430 {
1431 free(target_code);
1432 return retval;
1433 }
1434
1435 /* write algorithm code to working area */
1436 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1437 target_code_size, target_code)) != ERROR_OK)
1438 {
1439 free(target_code);
1440 return retval;
1441 }
1442
1443 free(target_code);
1444 }
1445 /* the following code still assumes target code is fixed 24*4 bytes */
1446
1447 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1448 {
1449 buffer_size /= 2;
1450 if (buffer_size <= 256)
1451 {
1452 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1453 if (cfi_info->write_algorithm)
1454 target_free_working_area(target, cfi_info->write_algorithm);
1455
1456 LOG_WARNING("not enough working area available, can't do block memory writes");
1457 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1458 }
1459 };
1460
1461 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1462 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1463 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1464 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1465 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1466 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1467 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1468 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1469 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1470 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1471
1472 while (count > 0)
1473 {
1474 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1475
1476 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1477
1478 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1479 buf_set_u32(reg_params[1].value, 0, 32, address);
1480 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1481 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1482 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1483 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1484 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1485 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1486 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1487
1488 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1489 cfi_info->write_algorithm->address,
1490 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1491 10000, &armv4_5_info);
1492
1493 status = buf_get_u32(reg_params[5].value, 0, 32);
1494
1495 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1496 {
1497 LOG_DEBUG("status: 0x%" PRIx32 , status);
1498 exit_code = ERROR_FLASH_OPERATION_FAILED;
1499 break;
1500 }
1501
1502 buffer += thisrun_count;
1503 address += thisrun_count;
1504 count -= thisrun_count;
1505 }
1506
1507 target_free_all_working_areas(target);
1508
1509 destroy_reg_param(&reg_params[0]);
1510 destroy_reg_param(&reg_params[1]);
1511 destroy_reg_param(&reg_params[2]);
1512 destroy_reg_param(&reg_params[3]);
1513 destroy_reg_param(&reg_params[4]);
1514 destroy_reg_param(&reg_params[5]);
1515 destroy_reg_param(&reg_params[6]);
1516 destroy_reg_param(&reg_params[7]);
1517 destroy_reg_param(&reg_params[8]);
1518 destroy_reg_param(&reg_params[9]);
1519
1520 return exit_code;
1521 }
1522
1523 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1524 {
1525 int retval;
1526 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1527 struct target *target = bank->target;
1528
1529 cfi_intel_clear_status_register(bank);
1530 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1531 {
1532 return retval;
1533 }
1534
1535 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1536 {
1537 return retval;
1538 }
1539
1540 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1541 {
1542 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1543 {
1544 return retval;
1545 }
1546
1547 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1548 return ERROR_FLASH_OPERATION_FAILED;
1549 }
1550
1551 return ERROR_OK;
1552 }
1553
1554 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1555 {
1556 int retval;
1557 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1558 struct target *target = bank->target;
1559
1560 /* Calculate buffer size and boundary mask */
1561 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1562 uint32_t buffermask = buffersize-1;
1563 uint32_t bufferwsize;
1564
1565 /* Check for valid range */
1566 if (address & buffermask)
1567 {
1568 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1569 bank->base, address, cfi_info->max_buf_write_size);
1570 return ERROR_FLASH_OPERATION_FAILED;
1571 }
1572 switch (bank->chip_width)
1573 {
1574 case 4 : bufferwsize = buffersize / 4; break;
1575 case 2 : bufferwsize = buffersize / 2; break;
1576 case 1 : bufferwsize = buffersize; break;
1577 default:
1578 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1579 return ERROR_FLASH_OPERATION_FAILED;
1580 }
1581
1582 bufferwsize/=(bank->bus_width / bank->chip_width);
1583
1584
1585 /* Check for valid size */
1586 if (wordcount > bufferwsize)
1587 {
1588 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1589 return ERROR_FLASH_OPERATION_FAILED;
1590 }
1591
1592 /* Write to flash buffer */
1593 cfi_intel_clear_status_register(bank);
1594
1595 /* Initiate buffer operation _*/
1596 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1597 {
1598 return retval;
1599 }
1600 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1601 {
1602 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1603 {
1604 return retval;
1605 }
1606
1607 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1608 return ERROR_FLASH_OPERATION_FAILED;
1609 }
1610
1611 /* Write buffer wordcount-1 and data words */
1612 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1613 {
1614 return retval;
1615 }
1616
1617 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1618 {
1619 return retval;
1620 }
1621
1622 /* Commit write operation */
1623 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1624 {
1625 return retval;
1626 }
1627 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1628 {
1629 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1630 {
1631 return retval;
1632 }
1633
1634 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1635 return ERROR_FLASH_OPERATION_FAILED;
1636 }
1637
1638 return ERROR_OK;
1639 }
1640
1641 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1642 {
1643 int retval;
1644 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1645 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1646 struct target *target = bank->target;
1647
1648 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1649 {
1650 return retval;
1651 }
1652
1653 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1654 {
1655 return retval;
1656 }
1657
1658 if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1659 {
1660 return retval;
1661 }
1662
1663 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1664 {
1665 return retval;
1666 }
1667
1668 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1669 {
1670 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1671 {
1672 return retval;
1673 }
1674
1675 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1676 return ERROR_FLASH_OPERATION_FAILED;
1677 }
1678
1679 return ERROR_OK;
1680 }
1681
1682 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1683 {
1684 int retval;
1685 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1686 struct target *target = bank->target;
1687 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1688
1689 /* Calculate buffer size and boundary mask */
1690 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1691 uint32_t buffermask = buffersize-1;
1692 uint32_t bufferwsize;
1693
1694 /* Check for valid range */
1695 if (address & buffermask)
1696 {
1697 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1698 return ERROR_FLASH_OPERATION_FAILED;
1699 }
1700 switch (bank->chip_width)
1701 {
1702 case 4 : bufferwsize = buffersize / 4; break;
1703 case 2 : bufferwsize = buffersize / 2; break;
1704 case 1 : bufferwsize = buffersize; break;
1705 default:
1706 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1707 return ERROR_FLASH_OPERATION_FAILED;
1708 }
1709
1710 bufferwsize/=(bank->bus_width / bank->chip_width);
1711
1712 /* Check for valid size */
1713 if (wordcount > bufferwsize)
1714 {
1715 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1716 return ERROR_FLASH_OPERATION_FAILED;
1717 }
1718
1719 // Unlock
1720 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1721 {
1722 return retval;
1723 }
1724
1725 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1726 {
1727 return retval;
1728 }
1729
1730 // Buffer load command
1731 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1732 {
1733 return retval;
1734 }
1735
1736 /* Write buffer wordcount-1 and data words */
1737 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1738 {
1739 return retval;
1740 }
1741
1742 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1743 {
1744 return retval;
1745 }
1746
1747 /* Commit write operation */
1748 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1749 {
1750 return retval;
1751 }
1752
1753 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1754 {
1755 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1756 {
1757 return retval;
1758 }
1759
1760 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1761 return ERROR_FLASH_OPERATION_FAILED;
1762 }
1763
1764 return ERROR_OK;
1765 }
1766
1767 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1768 {
1769 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1770
1771 switch (cfi_info->pri_id)
1772 {
1773 case 1:
1774 case 3:
1775 return cfi_intel_write_word(bank, word, address);
1776 break;
1777 case 2:
1778 return cfi_spansion_write_word(bank, word, address);
1779 break;
1780 default:
1781 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1782 break;
1783 }
1784
1785 return ERROR_FLASH_OPERATION_FAILED;
1786 }
1787
1788 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1789 {
1790 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1791
1792 switch (cfi_info->pri_id)
1793 {
1794 case 1:
1795 case 3:
1796 return cfi_intel_write_words(bank, word, wordcount, address);
1797 break;
1798 case 2:
1799 return cfi_spansion_write_words(bank, word, wordcount, address);
1800 break;
1801 default:
1802 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1803 break;
1804 }
1805
1806 return ERROR_FLASH_OPERATION_FAILED;
1807 }
1808
1809 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1810 {
1811 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1812 struct target *target = bank->target;
1813 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1814 uint32_t write_p, copy_p;
1815 int align; /* number of unaligned bytes */
1816 int blk_count; /* number of bus_width bytes for block copy */
1817 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1818 int i;
1819 int retval;
1820
1821 if (bank->target->state != TARGET_HALTED)
1822 {
1823 LOG_ERROR("Target not halted");
1824 return ERROR_TARGET_NOT_HALTED;
1825 }
1826
1827 if (offset + count > bank->size)
1828 return ERROR_FLASH_DST_OUT_OF_BANK;
1829
1830 if (cfi_info->qry[0] != 'Q')
1831 return ERROR_FLASH_BANK_NOT_PROBED;
1832
1833 /* start at the first byte of the first word (bus_width size) */
1834 write_p = address & ~(bank->bus_width - 1);
1835 if ((align = address - write_p) != 0)
1836 {
1837 LOG_INFO("Fixup %d unaligned head bytes", align);
1838
1839 for (i = 0; i < bank->bus_width; i++)
1840 current_word[i] = 0;
1841 copy_p = write_p;
1842
1843 /* copy bytes before the first write address */
1844 for (i = 0; i < align; ++i, ++copy_p)
1845 {
1846 uint8_t byte;
1847 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1848 {
1849 return retval;
1850 }
1851 cfi_add_byte(bank, current_word, byte);
1852 }
1853
1854 /* add bytes from the buffer */
1855 for (; (i < bank->bus_width) && (count > 0); i++)
1856 {
1857 cfi_add_byte(bank, current_word, *buffer++);
1858 count--;
1859 copy_p++;
1860 }
1861
1862 /* if the buffer is already finished, copy bytes after the last write address */
1863 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1864 {
1865 uint8_t byte;
1866 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1867 {
1868 return retval;
1869 }
1870 cfi_add_byte(bank, current_word, byte);
1871 }
1872
1873 retval = cfi_write_word(bank, current_word, write_p);
1874 if (retval != ERROR_OK)
1875 return retval;
1876 write_p = copy_p;
1877 }
1878
1879 /* handle blocks of bus_size aligned bytes */
1880 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1881 switch (cfi_info->pri_id)
1882 {
1883 /* try block writes (fails without working area) */
1884 case 1:
1885 case 3:
1886 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1887 break;
1888 case 2:
1889 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1890 break;
1891 default:
1892 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1893 retval = ERROR_FLASH_OPERATION_FAILED;
1894 break;
1895 }
1896 if (retval == ERROR_OK)
1897 {
1898 /* Increment pointers and decrease count on succesful block write */
1899 buffer += blk_count;
1900 write_p += blk_count;
1901 count -= blk_count;
1902 }
1903 else
1904 {
1905 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1906 {
1907 //adjust buffersize for chip width
1908 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1909 uint32_t buffermask = buffersize-1;
1910 uint32_t bufferwsize;
1911
1912 switch (bank->chip_width)
1913 {
1914 case 4 : bufferwsize = buffersize / 4; break;
1915 case 2 : bufferwsize = buffersize / 2; break;
1916 case 1 : bufferwsize = buffersize; break;
1917 default:
1918 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1919 return ERROR_FLASH_OPERATION_FAILED;
1920 }
1921
1922 bufferwsize/=(bank->bus_width / bank->chip_width);
1923
1924 /* fall back to memory writes */
1925 while (count >= (uint32_t)bank->bus_width)
1926 {
1927 int fallback;
1928 if ((write_p & 0xff) == 0)
1929 {
1930 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1931 }
1932 fallback = 1;
1933 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1934 {
1935 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1936 if (retval == ERROR_OK)
1937 {
1938 buffer += buffersize;
1939 write_p += buffersize;
1940 count -= buffersize;
1941 fallback = 0;
1942 }
1943 }
1944 /* try the slow way? */
1945 if (fallback)
1946 {
1947 for (i = 0; i < bank->bus_width; i++)
1948 current_word[i] = 0;
1949
1950 for (i = 0; i < bank->bus_width; i++)
1951 {
1952 cfi_add_byte(bank, current_word, *buffer++);
1953 }
1954
1955 retval = cfi_write_word(bank, current_word, write_p);
1956 if (retval != ERROR_OK)
1957 return retval;
1958
1959 write_p += bank->bus_width;
1960 count -= bank->bus_width;
1961 }
1962 }
1963 }
1964 else
1965 return retval;
1966 }
1967
1968 /* return to read array mode, so we can read from flash again for padding */
1969 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1970 {
1971 return retval;
1972 }
1973 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1974 {
1975 return retval;
1976 }
1977
1978 /* handle unaligned tail bytes */
1979 if (count > 0)
1980 {
1981 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
1982
1983 copy_p = write_p;
1984 for (i = 0; i < bank->bus_width; i++)
1985 current_word[i] = 0;
1986
1987 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1988 {
1989 cfi_add_byte(bank, current_word, *buffer++);
1990 count--;
1991 }
1992 for (; i < bank->bus_width; ++i, ++copy_p)
1993 {
1994 uint8_t byte;
1995 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1996 {
1997 return retval;
1998 }
1999 cfi_add_byte(bank, current_word, byte);
2000 }
2001 retval = cfi_write_word(bank, current_word, write_p);
2002 if (retval != ERROR_OK)
2003 return retval;
2004 }
2005
2006 /* return to read array mode */
2007 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
2008 {
2009 return retval;
2010 }
2011 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2012 }
2013
2014 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2015 {
2016 (void) param;
2017 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2018 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2019
2020 pri_ext->_reversed_geometry = 1;
2021 }
2022
2023 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2024 {
2025 int i;
2026 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2027 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2028 (void) param;
2029
2030 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2031 {
2032 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2033
2034 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2035 {
2036 int j = (cfi_info->num_erase_regions - 1) - i;
2037 uint32_t swap;
2038
2039 swap = cfi_info->erase_region_info[i];
2040 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2041 cfi_info->erase_region_info[j] = swap;
2042 }
2043 }
2044 }
2045
2046 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2047 {
2048 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2049 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2050 struct cfi_unlock_addresses *unlock_addresses = param;
2051
2052 pri_ext->_unlock1 = unlock_addresses->unlock1;
2053 pri_ext->_unlock2 = unlock_addresses->unlock2;
2054 }
2055
2056
2057 static int cfi_query_string(struct flash_bank *bank, int address)
2058 {
2059 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2060 int retval;
2061
2062 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2063 {
2064 return retval;
2065 }
2066
2067 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2068 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2069 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2070
2071 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2072
2073 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2074 {
2075 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
2076 {
2077 return retval;
2078 }
2079 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
2080 {
2081 return retval;
2082 }
2083 LOG_ERROR("Could not probe bank: no QRY");
2084 return ERROR_FLASH_BANK_INVALID;
2085 }
2086
2087 return ERROR_OK;
2088 }
2089
2090 static int cfi_probe(struct flash_bank *bank)
2091 {
2092 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2093 struct target *target = bank->target;
2094 int num_sectors = 0;
2095 int i;
2096 int sector = 0;
2097 uint32_t unlock1 = 0x555;
2098 uint32_t unlock2 = 0x2aa;
2099 int retval;
2100
2101 if (bank->target->state != TARGET_HALTED)
2102 {
2103 LOG_ERROR("Target not halted");
2104 return ERROR_TARGET_NOT_HALTED;
2105 }
2106
2107 cfi_info->probed = 0;
2108
2109 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2110 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2111 */
2112 if (cfi_info->jedec_probe)
2113 {
2114 unlock1 = 0x5555;
2115 unlock2 = 0x2aaa;
2116 }
2117
2118 /* switch to read identifier codes mode ("AUTOSELECT") */
2119 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2120 {
2121 return retval;
2122 }
2123 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2124 {
2125 return retval;
2126 }
2127 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2128 {
2129 return retval;
2130 }
2131
2132 if (bank->chip_width == 1)
2133 {
2134 uint8_t manufacturer, device_id;
2135 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2136 {
2137 return retval;
2138 }
2139 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2140 {
2141 return retval;
2142 }
2143 cfi_info->manufacturer = manufacturer;
2144 cfi_info->device_id = device_id;
2145 }
2146 else if (bank->chip_width == 2)
2147 {
2148 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2149 {
2150 return retval;
2151 }
2152 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2153 {
2154 return retval;
2155 }
2156 }
2157
2158 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2159 /* switch back to read array mode */
2160 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
2161 {
2162 return retval;
2163 }
2164 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x00))) != ERROR_OK)
2165 {
2166 return retval;
2167 }
2168
2169 /* check device/manufacturer ID for known non-CFI flashes. */
2170 cfi_fixup_non_cfi(bank);
2171
2172 /* query only if this is a CFI compatible flash,
2173 * otherwise the relevant info has already been filled in
2174 */
2175 if (cfi_info->not_cfi == 0)
2176 {
2177 int retval;
2178
2179 /* enter CFI query mode
2180 * according to JEDEC Standard No. 68.01,
2181 * a single bus sequence with address = 0x55, data = 0x98 should put
2182 * the device into CFI query mode.
2183 *
2184 * SST flashes clearly violate this, and we will consider them incompatbile for now
2185 */
2186
2187 retval = cfi_query_string(bank, 0x55);
2188 if (retval != ERROR_OK)
2189 {
2190 /*
2191 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2192 * be harmless enough:
2193 *
2194 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2195 */
2196 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2197 retval = cfi_query_string(bank, 0x555);
2198 }
2199 if (retval != ERROR_OK)
2200 return retval;
2201
2202 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2203 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2204 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2205 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2206
2207 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2208
2209 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2210 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2211 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2212 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2213 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2214 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2215 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2216 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2217 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2218 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2219 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2220 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2221
2222 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2223 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2224 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2225 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2226 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2227 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2228 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2229 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2230 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2231 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2232 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2233
2234 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2235 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2236 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2237 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2238
2239 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2240
2241 if (cfi_info->num_erase_regions)
2242 {
2243 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2244 for (i = 0; i < cfi_info->num_erase_regions; i++)
2245 {
2246 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2247 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2248 i,
2249 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2250 (cfi_info->erase_region_info[i] >> 16) * 256);
2251 }
2252 }
2253 else
2254 {
2255 cfi_info->erase_region_info = NULL;
2256 }
2257
2258 /* We need to read the primary algorithm extended query table before calculating
2259 * the sector layout to be able to apply fixups
2260 */
2261 switch (cfi_info->pri_id)
2262 {
2263 /* Intel command set (standard and extended) */
2264 case 0x0001:
2265 case 0x0003:
2266 cfi_read_intel_pri_ext(bank);
2267 break;
2268 /* AMD/Spansion, Atmel, ... command set */
2269 case 0x0002:
2270 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2271 cfi_read_0002_pri_ext(bank);
2272 break;
2273 default:
2274 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2275 break;
2276 }
2277
2278 /* return to read array mode
2279 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2280 */
2281 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
2282 {
2283 return retval;
2284 }
2285 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
2286 {
2287 return retval;
2288 }
2289 } /* end CFI case */
2290
2291 /* apply fixups depending on the primary command set */
2292 switch (cfi_info->pri_id)
2293 {
2294 /* Intel command set (standard and extended) */
2295 case 0x0001:
2296 case 0x0003:
2297 cfi_fixup(bank, cfi_0001_fixups);
2298 break;
2299 /* AMD/Spansion, Atmel, ... command set */
2300 case 0x0002:
2301 cfi_fixup(bank, cfi_0002_fixups);
2302 break;
2303 default:
2304 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2305 break;
2306 }
2307
2308 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2309 {
2310 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2311 }
2312
2313 if (cfi_info->num_erase_regions == 0)
2314 {
2315 /* a device might have only one erase block, spanning the whole device */
2316 bank->num_sectors = 1;
2317 bank->sectors = malloc(sizeof(struct flash_sector));
2318
2319 bank->sectors[sector].offset = 0x0;
2320 bank->sectors[sector].size = bank->size;
2321 bank->sectors[sector].is_erased = -1;
2322 bank->sectors[sector].is_protected = -1;
2323 }
2324 else
2325 {
2326 uint32_t offset = 0;
2327
2328 for (i = 0; i < cfi_info->num_erase_regions; i++)
2329 {
2330 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2331 }
2332
2333 bank->num_sectors = num_sectors;
2334 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2335
2336 for (i = 0; i < cfi_info->num_erase_regions; i++)
2337 {
2338 uint32_t j;
2339 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2340 {
2341 bank->sectors[sector].offset = offset;
2342 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2343 offset += bank->sectors[sector].size;
2344 bank->sectors[sector].is_erased = -1;
2345 bank->sectors[sector].is_protected = -1;
2346 sector++;
2347 }
2348 }
2349 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2350 {
2351 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2352 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2353 }
2354 }
2355
2356 cfi_info->probed = 1;
2357
2358 return ERROR_OK;
2359 }
2360
2361 static int cfi_auto_probe(struct flash_bank *bank)
2362 {
2363 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2364 if (cfi_info->probed)
2365 return ERROR_OK;
2366 return cfi_probe(bank);
2367 }
2368
2369
2370 static int cfi_intel_protect_check(struct flash_bank *bank)
2371 {
2372 int retval;
2373 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2374 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2375 int i;
2376
2377 /* check if block lock bits are supported on this device */
2378 if (!(pri_ext->blk_status_reg_mask & 0x1))
2379 return ERROR_FLASH_OPERATION_FAILED;
2380
2381 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2382 {
2383 return retval;
2384 }
2385
2386 for (i = 0; i < bank->num_sectors; i++)
2387 {
2388 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2389
2390 if (block_status & 1)
2391 bank->sectors[i].is_protected = 1;
2392 else
2393 bank->sectors[i].is_protected = 0;
2394 }
2395
2396 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2397 }
2398
2399 static int cfi_spansion_protect_check(struct flash_bank *bank)
2400 {
2401 int retval;
2402 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2403 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2404 int i;
2405
2406 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2407 {
2408 return retval;
2409 }
2410
2411 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2412 {
2413 return retval;
2414 }
2415
2416 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2417 {
2418 return retval;
2419 }
2420
2421 for (i = 0; i < bank->num_sectors; i++)
2422 {
2423 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2424
2425 if (block_status & 1)
2426 bank->sectors[i].is_protected = 1;
2427 else
2428 bank->sectors[i].is_protected = 0;
2429 }
2430
2431 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2432 }
2433
2434 static int cfi_protect_check(struct flash_bank *bank)
2435 {
2436 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2437
2438 if (bank->target->state != TARGET_HALTED)
2439 {
2440 LOG_ERROR("Target not halted");
2441 return ERROR_TARGET_NOT_HALTED;
2442 }
2443
2444 if (cfi_info->qry[0] != 'Q')
2445 return ERROR_FLASH_BANK_NOT_PROBED;
2446
2447 switch (cfi_info->pri_id)
2448 {
2449 case 1:
2450 case 3:
2451 return cfi_intel_protect_check(bank);
2452 break;
2453 case 2:
2454 return cfi_spansion_protect_check(bank);
2455 break;
2456 default:
2457 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2458 break;
2459 }
2460
2461 return ERROR_OK;
2462 }
2463
2464 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2465 {
2466 int printed;
2467 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2468
2469 if (cfi_info->qry[0] == (char)-1)
2470 {
2471 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2472 return ERROR_OK;
2473 }
2474
2475 if (cfi_info->not_cfi == 0)
2476 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2477 else
2478 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2479 buf += printed;
2480 buf_size -= printed;
2481
2482 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2483 cfi_info->manufacturer, cfi_info->device_id);
2484 buf += printed;
2485 buf_size -= printed;
2486
2487 if (cfi_info->not_cfi == 0)
2488 {
2489 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2490 buf += printed;
2491 buf_size -= printed;
2492
2493 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2494 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2495 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2496 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2497 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2498 buf += printed;
2499 buf_size -= printed;
2500
2501 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2502 1 << cfi_info->word_write_timeout_typ,
2503 1 << cfi_info->buf_write_timeout_typ,
2504 1 << cfi_info->block_erase_timeout_typ,
2505 1 << cfi_info->chip_erase_timeout_typ);
2506 buf += printed;
2507 buf_size -= printed;
2508
2509 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2510 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2511 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2512 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2513 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2514 buf += printed;
2515 buf_size -= printed;
2516
2517 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2518 cfi_info->dev_size,
2519 cfi_info->interface_desc,
2520 1 << cfi_info->max_buf_write_size);
2521 buf += printed;
2522 buf_size -= printed;
2523
2524 switch (cfi_info->pri_id)
2525 {
2526 case 1:
2527 case 3:
2528 cfi_intel_info(bank, buf, buf_size);
2529 break;
2530 case 2:
2531 cfi_spansion_info(bank, buf, buf_size);
2532 break;
2533 default:
2534 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2535 break;
2536 }
2537 }
2538
2539 return ERROR_OK;
2540 }
2541
2542 struct flash_driver cfi_flash = {
2543 .name = "cfi",
2544 .flash_bank_command = cfi_flash_bank_command,
2545 .erase = cfi_erase,
2546 .protect = cfi_protect,
2547 .write = cfi_write,
2548 .probe = cfi_probe,
2549 .auto_probe = cfi_auto_probe,
2550 .erase_check = default_flash_blank_check,
2551 .protect_check = cfi_protect_check,
2552 .info = cfi_info,
2553 };
Marex's Cortex A8 development branch