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zy1000: arm11 load is now faster
[openocd/cortex.git] / src / jtag / zy1000 / zy1000.c
blob6465aaa7b25db1ffbe16c705a941e2f62019ee9c
1 /***************************************************************************
2 * Copyright (C) 2007-2010 by Øyvind Harboe *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /* This file supports the zy1000 debugger: http://www.zylin.com/zy1000.html
21 *
22 * The zy1000 is a standalone debugger that has a web interface and
23 * requires no drivers on the developer host as all communication
24 * is via TCP/IP. The zy1000 gets it performance(~400-700kBytes/s
25 * DCC downloads @ 16MHz target) as it has an FPGA to hardware
26 * accelerate the JTAG commands, while offering *very* low latency
27 * between OpenOCD and the FPGA registers.
28 *
29 * The disadvantage of the zy1000 is that it has a feeble CPU compared to
30 * a PC(ca. 50-500 DMIPS depending on how one counts it), whereas a PC
31 * is on the order of 10000 DMIPS(i.e. at a factor of 20-200).
32 *
33 * The zy1000 revc hardware is using an Altera Nios CPU, whereas the
34 * revb is using ARM7 + Xilinx.
35 *
36 * See Zylin web pages or contact Zylin for more information.
37 *
38 * The reason this code is in OpenOCD rather than OpenOCD linked with the
39 * ZY1000 code is that OpenOCD is the long road towards getting
40 * libopenocd into place. libopenocd will support both low performance,
41 * low latency systems(embedded) and high performance high latency
42 * systems(PCs).
43 */
44 #ifdef HAVE_CONFIG_H
45 #include "config.h"
46 #endif
47
48 #include <target/embeddedice.h>
49 #include <jtag/minidriver.h>
50 #include <jtag/interface.h>
51 #include "zy1000_version.h"
52
53 #include <cyg/hal/hal_io.h> // low level i/o
54 #include <cyg/hal/hal_diag.h>
55
56 #include <time.h>
57
58 #ifdef CYGPKG_HAL_NIOS2
59 #include <cyg/hal/io.h>
60 #include <cyg/firmwareutil/firmwareutil.h>
61 #endif
62
63 #define ZYLIN_VERSION GIT_ZY1000_VERSION
64 #define ZYLIN_DATE __DATE__
65 #define ZYLIN_TIME __TIME__
66 #define ZYLIN_OPENOCD GIT_OPENOCD_VERSION
67 #define ZYLIN_OPENOCD_VERSION "ZY1000 " ZYLIN_VERSION " " ZYLIN_DATE
68
69
70 static int zy1000_khz(int khz, int *jtag_speed)
71 {
72 if (khz == 0)
73 {
74 *jtag_speed = 0;
75 }
76 else
77 {
78 *jtag_speed = 64000/khz;
79 }
80 return ERROR_OK;
81 }
82
83 static int zy1000_speed_div(int speed, int *khz)
84 {
85 if (speed == 0)
86 {
87 *khz = 0;
88 }
89 else
90 {
91 *khz = 64000/speed;
92 }
93
94 return ERROR_OK;
95 }
96
97 static bool readPowerDropout(void)
98 {
99 cyg_uint32 state;
100 // sample and clear power dropout
101 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80);
102 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
103 bool powerDropout;
104 powerDropout = (state & 0x80) != 0;
105 return powerDropout;
106 }
107
108
109 static bool readSRST(void)
110 {
111 cyg_uint32 state;
112 // sample and clear SRST sensing
113 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040);
114 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
115 bool srstAsserted;
116 srstAsserted = (state & 0x40) != 0;
117 return srstAsserted;
118 }
119
120 static int zy1000_srst_asserted(int *srst_asserted)
121 {
122 *srst_asserted = readSRST();
123 return ERROR_OK;
124 }
125
126 static int zy1000_power_dropout(int *dropout)
127 {
128 *dropout = readPowerDropout();
129 return ERROR_OK;
130 }
131
132 void zy1000_reset(int trst, int srst)
133 {
134 LOG_DEBUG("zy1000 trst=%d, srst=%d", trst, srst);
135
136 /* flush the JTAG FIFO. Not flushing the queue before messing with
137 * reset has such interesting bugs as causing hard to reproduce
138 * RCLK bugs as RCLK will stop responding when TRST is asserted
139 */
140 waitIdle();
141
142 if (!srst)
143 {
144 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000001);
145 }
146 else
147 {
148 /* Danger!!! if clk != 0 when in
149 * idle in TAP_IDLE, reset halt on str912 will fail.
150 */
151 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000001);
152 }
153
154 if (!trst)
155 {
156 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000002);
157 }
158 else
159 {
160 /* assert reset */
161 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000002);
162 }
163
164 if (trst||(srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
165 {
166 /* we're now in the RESET state until trst is deasserted */
167 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_RESET);
168 } else
169 {
170 /* We'll get RCLK failure when we assert TRST, so clear any false positives here */
171 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
172 }
173
174 /* wait for srst to float back up */
175 if (!srst)
176 {
177 int i;
178 for (i = 0; i < 1000; i++)
179 {
180 // We don't want to sense our own reset, so we clear here.
181 // There is of course a timing hole where we could loose
182 // a "real" reset.
183 if (!readSRST())
184 break;
185
186 /* wait 1ms */
187 alive_sleep(1);
188 }
189
190 if (i == 1000)
191 {
192 LOG_USER("SRST didn't deassert after %dms", i);
193 } else if (i > 1)
194 {
195 LOG_USER("SRST took %dms to deassert", i);
196 }
197 }
198 }
199
200 int zy1000_speed(int speed)
201 {
202 /* flush JTAG master FIFO before setting speed */
203 waitIdle();
204
205 if (speed == 0)
206 {
207 /*0 means RCLK*/
208 speed = 0;
209 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x100);
210 LOG_DEBUG("jtag_speed using RCLK");
211 }
212 else
213 {
214 if (speed > 8190 || speed < 2)
215 {
216 LOG_USER("valid ZY1000 jtag_speed=[8190,2]. Divisor is 64MHz / even values between 8190-2, i.e. min 7814Hz, max 32MHz");
217 return ERROR_INVALID_ARGUMENTS;
218 }
219
220 LOG_USER("jtag_speed %d => JTAG clk=%f", speed, 64.0/(float)speed);
221 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x100);
222 ZY1000_POKE(ZY1000_JTAG_BASE + 0x1c, speed&~1);
223 }
224 return ERROR_OK;
225 }
226
227 static bool savePower;
228
229
230 static void setPower(bool power)
231 {
232 savePower = power;
233 if (power)
234 {
235 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8);
236 } else
237 {
238 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8);
239 }
240 }
241
242 COMMAND_HANDLER(handle_power_command)
243 {
244 switch (CMD_ARGC)
245 {
246 case 1: {
247 bool enable;
248 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
249 setPower(enable);
250 // fall through
251 }
252 case 0:
253 LOG_INFO("Target power %s", savePower ? "on" : "off");
254 break;
255 default:
256 return ERROR_INVALID_ARGUMENTS;
257 }
258
259 return ERROR_OK;
260 }
261
262
263 /* Give TELNET a way to find out what version this is */
264 static int jim_zy1000_version(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
265 {
266 if ((argc < 1) || (argc > 3))
267 return JIM_ERR;
268 const char *version_str = NULL;
269
270 if (argc == 1)
271 {
272 version_str = ZYLIN_OPENOCD_VERSION;
273 } else
274 {
275 const char *str = Jim_GetString(argv[1], NULL);
276 const char *str2 = NULL;
277 if (argc > 2)
278 str2 = Jim_GetString(argv[2], NULL);
279 if (strcmp("openocd", str) == 0)
280 {
281 version_str = ZYLIN_OPENOCD;
282 }
283 else if (strcmp("zy1000", str) == 0)
284 {
285 version_str = ZYLIN_VERSION;
286 }
287 else if (strcmp("date", str) == 0)
288 {
289 version_str = ZYLIN_DATE;
290 }
291 else if (strcmp("time", str) == 0)
292 {
293 version_str = ZYLIN_TIME;
294 }
295 else if (strcmp("pcb", str) == 0)
296 {
297 #ifdef CYGPKG_HAL_NIOS2
298 version_str="c";
299 #else
300 version_str="b";
301 #endif
302 }
303 #ifdef CYGPKG_HAL_NIOS2
304 else if (strcmp("fpga", str) == 0)
305 {
306
307 /* return a list of 32 bit integers to describe the expected
308 * and actual FPGA
309 */
310 static char *fpga_id = "0x12345678 0x12345678 0x12345678 0x12345678";
311 cyg_uint32 id, timestamp;
312 HAL_READ_UINT32(SYSID_BASE, id);
313 HAL_READ_UINT32(SYSID_BASE+4, timestamp);
314 sprintf(fpga_id, "0x%08x 0x%08x 0x%08x 0x%08x", id, timestamp, SYSID_ID, SYSID_TIMESTAMP);
315 version_str = fpga_id;
316 if ((argc>2) && (strcmp("time", str2) == 0))
317 {
318 time_t last_mod = timestamp;
319 char * t = ctime (&last_mod) ;
320 t[strlen(t)-1] = 0;
321 version_str = t;
322 }
323 }
324 #endif
325
326 else
327 {
328 return JIM_ERR;
329 }
330 }
331
332 Jim_SetResult(interp, Jim_NewStringObj(interp, version_str, -1));
333
334 return JIM_OK;
335 }
336
337
338 #ifdef CYGPKG_HAL_NIOS2
339
340
341 struct info_forward
342 {
343 void *data;
344 struct cyg_upgrade_info *upgraded_file;
345 };
346
347 static void report_info(void *data, const char * format, va_list args)
348 {
349 char *s = alloc_vprintf(format, args);
350 LOG_USER_N("%s", s);
351 free(s);
352 }
353
354 struct cyg_upgrade_info firmware_info =
355 {
356 (cyg_uint8 *)0x84000000,
357 "/ram/firmware.phi",
358 "Firmware",
359 0x0300000,
360 0x1f00000 -
361 0x0300000,
362 "ZylinNiosFirmware\n",
363 report_info,
364 };
365
366 static int jim_zy1000_writefirmware(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
367 {
368 if (argc != 2)
369 return JIM_ERR;
370
371 int length;
372 const char *str = Jim_GetString(argv[1], &length);
373
374 /* */
375 int tmpFile;
376 if ((tmpFile = open(firmware_info.file, O_RDWR | O_CREAT | O_TRUNC)) <= 0)
377 {
378 return JIM_ERR;
379 }
380 bool success;
381 success = write(tmpFile, str, length) == length;
382 close(tmpFile);
383 if (!success)
384 return JIM_ERR;
385
386 if (!cyg_firmware_upgrade(NULL, firmware_info))
387 return JIM_ERR;
388
389 return JIM_OK;
390 }
391 #endif
392
393 static int
394 zylinjtag_Jim_Command_powerstatus(Jim_Interp *interp,
395 int argc,
396 Jim_Obj * const *argv)
397 {
398 if (argc != 1)
399 {
400 Jim_WrongNumArgs(interp, 1, argv, "powerstatus");
401 return JIM_ERR;
402 }
403
404 cyg_uint32 status;
405 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, status);
406
407 Jim_SetResult(interp, Jim_NewIntObj(interp, (status&0x80) != 0));
408
409 return JIM_OK;
410 }
411
412
413
414
415 int zy1000_init(void)
416 {
417 LOG_USER("%s", ZYLIN_OPENOCD_VERSION);
418
419 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x30); // Turn on LED1 & LED2
420
421 setPower(true); // on by default
422
423
424 /* deassert resets. Important to avoid infinite loop waiting for SRST to deassert */
425 zy1000_reset(0, 0);
426 zy1000_speed(jtag_get_speed());
427
428 return ERROR_OK;
429 }
430
431 int zy1000_quit(void)
432 {
433
434 return ERROR_OK;
435 }
436
437
438
439 int interface_jtag_execute_queue(void)
440 {
441 cyg_uint32 empty;
442
443 waitIdle();
444 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty);
445 /* clear JTAG error register */
446 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
447
448 if ((empty&0x400) != 0)
449 {
450 LOG_WARNING("RCLK timeout");
451 /* the error is informative only as we don't want to break the firmware if there
452 * is a false positive.
453 */
454 // return ERROR_FAIL;
455 }
456 return ERROR_OK;
457 }
458
459
460
461
462
463 static cyg_uint32 getShiftValue(void)
464 {
465 cyg_uint32 value;
466 waitIdle();
467 ZY1000_PEEK(ZY1000_JTAG_BASE + 0xc, value);
468 VERBOSE(LOG_INFO("getShiftValue %08x", value));
469 return value;
470 }
471 #if 0
472 static cyg_uint32 getShiftValueFlip(void)
473 {
474 cyg_uint32 value;
475 waitIdle();
476 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x18, value);
477 VERBOSE(LOG_INFO("getShiftValue %08x (flipped)", value));
478 return value;
479 }
480 #endif
481
482 #if 0
483 static void shiftValueInnerFlip(const tap_state_t state, const tap_state_t endState, int repeat, cyg_uint32 value)
484 {
485 VERBOSE(LOG_INFO("shiftValueInner %s %s %d %08x (flipped)", tap_state_name(state), tap_state_name(endState), repeat, value));
486 cyg_uint32 a,b;
487 a = state;
488 b = endState;
489 ZY1000_POKE(ZY1000_JTAG_BASE + 0xc, value);
490 ZY1000_POKE(ZY1000_JTAG_BASE + 0x8, (1 << 15) | (repeat << 8) | (a << 4) | b);
491 VERBOSE(getShiftValueFlip());
492 }
493 #endif
494
495 static void gotoEndState(tap_state_t end_state)
496 {
497 setCurrentState(end_state);
498 }
499
500 static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, int pause)
501 {
502 int i;
503 int j;
504 int k;
505
506 for (i = 0; i < num_fields; i++)
507 {
508 cyg_uint32 value;
509
510 uint8_t *inBuffer = NULL;
511
512
513 // figure out where to store the input data
514 int num_bits = fields[i].num_bits;
515 if (fields[i].in_value != NULL)
516 {
517 inBuffer = fields[i].in_value;
518 }
519
520 // here we shuffle N bits out/in
521 j = 0;
522 while (j < num_bits)
523 {
524 tap_state_t pause_state;
525 int l;
526 k = num_bits-j;
527 pause_state = (shiftState == TAP_DRSHIFT)?TAP_DRSHIFT:TAP_IRSHIFT;
528 if (k > 32)
529 {
530 k = 32;
531 /* we have more to shift out */
532 } else if (pause&&(i == num_fields-1))
533 {
534 /* this was the last to shift out this time */
535 pause_state = (shiftState==TAP_DRSHIFT)?TAP_DRPAUSE:TAP_IRPAUSE;
536 }
537
538 // we have (num_bits + 7)/8 bytes of bits to toggle out.
539 // bits are pushed out LSB to MSB
540 value = 0;
541 if (fields[i].out_value != NULL)
542 {
543 for (l = 0; l < k; l += 8)
544 {
545 value|=fields[i].out_value[(j + l)/8]<<l;
546 }
547 }
548 /* mask away unused bits for easier debugging */
549 if (k < 32)
550 {
551 value&=~(((uint32_t)0xffffffff) << k);
552 } else
553 {
554 /* Shifting by >= 32 is not defined by the C standard
555 * and will in fact shift by &0x1f bits on nios */
556 }
557
558 shiftValueInner(shiftState, pause_state, k, value);
559
560 if (inBuffer != NULL)
561 {
562 // data in, LSB to MSB
563 value = getShiftValue();
564 // we're shifting in data to MSB, shift data to be aligned for returning the value
565 value >>= 32-k;
566
567 for (l = 0; l < k; l += 8)
568 {
569 inBuffer[(j + l)/8]=(value >> l)&0xff;
570 }
571 }
572 j += k;
573 }
574 }
575 }
576
577 int interface_jtag_add_ir_scan(int num_fields, const struct scan_field *fields, tap_state_t state)
578 {
579
580 int j;
581 int scan_size = 0;
582 struct jtag_tap *tap, *nextTap;
583 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
584 {
585 nextTap = jtag_tap_next_enabled(tap);
586 int pause = (nextTap==NULL);
587
588 int found = 0;
589
590 scan_size = tap->ir_length;
591
592 /* search the list */
593 for (j = 0; j < num_fields; j++)
594 {
595 if (tap == fields[j].tap)
596 {
597 found = 1;
598
599 scanFields(1, fields + j, TAP_IRSHIFT, pause);
600 /* update device information */
601 buf_cpy(fields[j].out_value, tap->cur_instr, scan_size);
602
603 tap->bypass = 0;
604 break;
605 }
606 }
607
608 if (!found)
609 {
610 /* if a device isn't listed, set it to BYPASS */
611 uint8_t ones[]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
612
613 struct scan_field tmp;
614 memset(&tmp, 0, sizeof(tmp));
615 tmp.out_value = ones;
616 tmp.num_bits = scan_size;
617 scanFields(1, &tmp, TAP_IRSHIFT, pause);
618 /* update device information */
619 buf_cpy(tmp.out_value, tap->cur_instr, scan_size);
620 tap->bypass = 1;
621 }
622 }
623 gotoEndState(state);
624
625 return ERROR_OK;
626 }
627
628
629
630
631
632 int interface_jtag_add_plain_ir_scan(int num_fields, const struct scan_field *fields, tap_state_t state)
633 {
634 scanFields(num_fields, fields, TAP_IRSHIFT, 1);
635 gotoEndState(state);
636
637 return ERROR_OK;
638 }
639
640 int interface_jtag_add_dr_scan(int num_fields, const struct scan_field *fields, tap_state_t state)
641 {
642
643 int j;
644 struct jtag_tap *tap, *nextTap;
645 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
646 {
647 nextTap = jtag_tap_next_enabled(tap);
648 int found = 0;
649 int pause = (nextTap==NULL);
650
651 for (j = 0; j < num_fields; j++)
652 {
653 /* Find a range of fields to write to this tap */
654 if (tap == fields[j].tap)
655 {
656 found = 1;
657 int i;
658 for (i = j + 1; i < num_fields; i++)
659 {
660 if (tap != fields[j].tap)
661 {
662 break;
663 }
664 }
665
666 scanFields(i - j, fields + j, TAP_DRSHIFT, pause);
667
668 j = i;
669 }
670 }
671
672 if (!found)
673 {
674 /* Shift out a 0 for disabled tap's */
675 shiftValueInner(TAP_DRSHIFT, pause?TAP_DRPAUSE:TAP_DRSHIFT, 1, 0);
676 }
677 else
678 {
679 }
680 }
681 gotoEndState(state);
682 return ERROR_OK;
683 }
684
685 int interface_jtag_add_plain_dr_scan(int num_fields, const struct scan_field *fields, tap_state_t state)
686 {
687 scanFields(num_fields, fields, TAP_DRSHIFT, 1);
688 gotoEndState(state);
689 return ERROR_OK;
690 }
691
692
693 int interface_jtag_add_tlr()
694 {
695 setCurrentState(TAP_RESET);
696 return ERROR_OK;
697 }
698
699
700
701
702 int interface_jtag_add_reset(int req_trst, int req_srst)
703 {
704 zy1000_reset(req_trst, req_srst);
705 return ERROR_OK;
706 }
707
708 static int zy1000_jtag_add_clocks(int num_cycles, tap_state_t state, tap_state_t clockstate)
709 {
710 /* num_cycles can be 0 */
711 setCurrentState(clockstate);
712
713 /* execute num_cycles, 32 at the time. */
714 int i;
715 for (i = 0; i < num_cycles; i += 32)
716 {
717 int num;
718 num = 32;
719 if (num_cycles-i < num)
720 {
721 num = num_cycles-i;
722 }
723 shiftValueInner(clockstate, clockstate, num, 0);
724 }
725
726 #if !TEST_MANUAL()
727 /* finish in end_state */
728 setCurrentState(state);
729 #else
730 tap_state_t t = TAP_IDLE;
731 /* test manual drive code on any target */
732 int tms;
733 uint8_t tms_scan = tap_get_tms_path(t, state);
734 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
735
736 for (i = 0; i < tms_count; i++)
737 {
738 tms = (tms_scan >> i) & 1;
739 waitIdle();
740 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
741 }
742 waitIdle();
743 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
744 #endif
745
746
747 return ERROR_OK;
748 }
749
750 int interface_jtag_add_runtest(int num_cycles, tap_state_t state)
751 {
752 return zy1000_jtag_add_clocks(num_cycles, state, TAP_IDLE);
753 }
754
755 int interface_jtag_add_clocks(int num_cycles)
756 {
757 return zy1000_jtag_add_clocks(num_cycles, cmd_queue_cur_state, cmd_queue_cur_state);
758 }
759
760 int interface_jtag_add_sleep(uint32_t us)
761 {
762 jtag_sleep(us);
763 return ERROR_OK;
764 }
765
766 int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state state)
767 {
768 /*wait for the fifo to be empty*/
769 waitIdle();
770
771 for (unsigned i = 0; i < num_bits; i++)
772 {
773 int tms;
774
775 if (((seq[i/8] >> (i % 8)) & 1) == 0)
776 {
777 tms = 0;
778 }
779 else
780 {
781 tms = 1;
782 }
783
784 waitIdle();
785 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
786 }
787
788 waitIdle();
789 if (state != TAP_INVALID)
790 {
791 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
792 } else
793 {
794 /* this would be normal if we are switching to SWD mode */
795 }
796 return ERROR_OK;
797 }
798
799 int interface_jtag_add_pathmove(int num_states, const tap_state_t *path)
800 {
801 int state_count;
802 int tms = 0;
803
804 state_count = 0;
805
806 tap_state_t cur_state = cmd_queue_cur_state;
807
808 uint8_t seq[16];
809 memset(seq, 0, sizeof(seq));
810 assert(num_states < (sizeof(seq) * 8));
811
812 while (num_states)
813 {
814 if (tap_state_transition(cur_state, false) == path[state_count])
815 {
816 tms = 0;
817 }
818 else if (tap_state_transition(cur_state, true) == path[state_count])
819 {
820 tms = 1;
821 }
822 else
823 {
824 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_name(cur_state), tap_state_name(path[state_count]));
825 exit(-1);
826 }
827
828 seq[state_count/8] = seq[state_count/8] | (tms << (state_count % 8));
829
830 cur_state = path[state_count];
831 state_count++;
832 num_states--;
833 }
834
835 return interface_add_tms_seq(state_count, seq, cur_state);
836 }
837
838 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
839 {
840 // static int const reg_addr = 0x5;
841 tap_state_t end_state = jtag_get_end_state();
842 if (jtag_tap_next_enabled(jtag_tap_next_enabled(NULL)) == NULL)
843 {
844 /* better performance via code duplication */
845 if (little)
846 {
847 int i;
848 for (i = 0; i < count; i++)
849 {
850 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
851 shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr | (1 << 5));
852 buffer += 4;
853 }
854 } else
855 {
856 int i;
857 for (i = 0; i < count; i++)
858 {
859 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
860 shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr | (1 << 5));
861 buffer += 4;
862 }
863 }
864 }
865 else
866 {
867 int i;
868 for (i = 0; i < count; i++)
869 {
870 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
871 buffer += 4;
872 }
873 }
874 }
875
876
877
878 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
879 {
880 #if 0
881 int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count);
882 return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
883 #else
884 static const int bits[] = {32, 2};
885 uint32_t values[] = {0, 0};
886
887 /* FIX!!!!!! the target_write_memory() API started this nasty problem
888 * with unaligned uint32_t * pointers... */
889 const uint8_t *t = (const uint8_t *)data;
890
891
892 /* bypass bits before and after */
893 int pre_bits = 0;
894 int post_bits = 0;
895
896 bool found = false;
897 struct jtag_tap *cur_tap, *nextTap;
898 for (cur_tap = jtag_tap_next_enabled(NULL); cur_tap!= NULL; cur_tap = nextTap)
899 {
900 nextTap = jtag_tap_next_enabled(cur_tap);
901 if (cur_tap == tap)
902 {
903 found = true;
904 } else
905 {
906 if (found)
907 {
908 post_bits++;
909 } else
910 {
911 pre_bits++;
912 }
913 }
914 }
915
916 post_bits+=2;
917
918
919 while (--count > 0)
920 {
921 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
922
923 uint32_t value;
924 value = *t++;
925 value |= (*t++<<8);
926 value |= (*t++<<16);
927 value |= (*t++<<24);
928
929 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, value);
930 shiftValueInner(TAP_DRSHIFT, TAP_DRPAUSE, post_bits, 0);
931
932 #if 1
933 /* copy & paste from arm11_dbgtap.c */
934 //TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
935
936 waitIdle();
937 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
938 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
939 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
940 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
941 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
942 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
943 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
944 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
945 /* we don't have to wait for the queue to empty here. waitIdle(); */
946 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_DRSHIFT);
947 #else
948 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
949 {
950 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
951 };
952
953 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
954 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
955 #endif
956 }
957
958 values[0] = *t++;
959 values[0] |= (*t++<<8);
960 values[0] |= (*t++<<16);
961 values[0] |= (*t++<<24);
962
963 /* This will happen on the last iteration updating the current tap state
964 * so we don't have to track it during the common code path */
965 jtag_add_dr_out(tap,
966 2,
967 bits,
968 values,
969 TAP_IDLE);
970
971 return jtag_execute_queue();
972 #endif
973 }
974
975
976 static const struct command_registration zy1000_commands[] = {
977 {
978 .name = "power",
979 .handler = handle_power_command,
980 .mode = COMMAND_ANY,
981 .help = "Turn power switch to target on/off. "
982 "With no arguments, prints status.",
983 .usage = "('on'|'off)",
984 },
985 {
986 .name = "zy1000_version",
987 .mode = COMMAND_ANY,
988 .jim_handler = jim_zy1000_version,
989 .help = "Print version info for zy1000.",
990 .usage = "['openocd'|'zy1000'|'date'|'time'|'pcb'|'fpga']",
991 },
992 {
993 .name = "powerstatus",
994 .mode = COMMAND_ANY,
995 .jim_handler = zylinjtag_Jim_Command_powerstatus,
996 .help = "Returns power status of target",
997 },
998 #ifdef CYGPKG_HAL_NIOS2
999 {
1000 .name = "updatezy1000firmware",
1001 .mode = COMMAND_ANY,
1002 .jim_handler = jim_zy1000_writefirmware,
1003 .help = "writes firmware to flash",
1004 /* .usage = "some_string", */
1005 },
1006 #endif
1007 COMMAND_REGISTRATION_DONE
1008 };
1009
1010
1011
1012 struct jtag_interface zy1000_interface =
1013 {
1014 .name = "ZY1000",
1015 .supported = DEBUG_CAP_TMS_SEQ,
1016 .execute_queue = NULL,
1017 .speed = zy1000_speed,
1018 .commands = zy1000_commands,
1019 .init = zy1000_init,
1020 .quit = zy1000_quit,
1021 .khz = zy1000_khz,
1022 .speed_div = zy1000_speed_div,
1023 .power_dropout = zy1000_power_dropout,
1024 .srst_asserted = zy1000_srst_asserted,
1025 };
1026
Marex's Cortex A8 development branch