1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
28 #include "breakpoints.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
35 static void mips_m4k_enable_breakpoints(struct target
*target
);
36 static void mips_m4k_enable_watchpoints(struct target
*target
);
37 static int mips_m4k_set_breakpoint(struct target
*target
,
38 struct breakpoint
*breakpoint
);
39 static int mips_m4k_unset_breakpoint(struct target
*target
,
40 struct breakpoint
*breakpoint
);
42 static int mips_m4k_examine_debug_reason(struct target
*target
)
44 uint32_t break_status
;
47 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
48 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
50 /* get info about inst breakpoint support */
51 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
53 if (break_status
& 0x1f)
55 /* we have halted on a breakpoint */
56 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
58 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
61 /* get info about data breakpoint support */
62 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &break_status
)) != ERROR_OK
)
64 if (break_status
& 0x1f)
66 /* we have halted on a breakpoint */
67 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
69 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
76 static int mips_m4k_debug_entry(struct target
*target
)
78 struct mips32_common
*mips32
= target_to_mips32(target
);
79 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
82 /* read debug register */
83 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
85 /* make sure break unit configured */
86 mips32_configure_break_unit(target
);
88 /* attempt to find halt reason */
89 mips_m4k_examine_debug_reason(target
);
91 /* clear single step if active */
92 if (debug_reg
& EJTAG_DEBUG_DSS
)
94 /* stopped due to single step - clear step bit */
95 mips_ejtag_config_step(ejtag_info
, 0);
98 mips32_save_context(target
);
100 /* default to mips32 isa, it will be changed below if required */
101 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
103 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
104 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
107 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
108 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
109 target_state_name(target
));
114 static int mips_m4k_poll(struct target
*target
)
117 struct mips32_common
*mips32
= target_to_mips32(target
);
118 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
119 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
121 /* read ejtag control reg */
122 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
123 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
125 /* clear this bit before handling polling
126 * as after reset registers will read zero */
127 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
129 /* we have detected a reset, clear flag
130 * otherwise ejtag will not work */
131 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
133 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
134 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
135 LOG_DEBUG("Reset Detected");
138 /* check for processor halted */
139 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
141 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
143 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
145 target
->state
= TARGET_HALTED
;
147 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
150 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
152 else if (target
->state
== TARGET_DEBUG_RUNNING
)
154 target
->state
= TARGET_HALTED
;
156 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
159 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
164 target
->state
= TARGET_RUNNING
;
167 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
172 static int mips_m4k_halt(struct target
*target
)
174 struct mips32_common
*mips32
= target_to_mips32(target
);
175 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
177 LOG_DEBUG("target->state: %s",
178 target_state_name(target
));
180 if (target
->state
== TARGET_HALTED
)
182 LOG_DEBUG("target was already halted");
186 if (target
->state
== TARGET_UNKNOWN
)
188 LOG_WARNING("target was in unknown state when halt was requested");
191 if (target
->state
== TARGET_RESET
)
193 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
195 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
196 return ERROR_TARGET_FAILURE
;
200 /* we came here in a reset_halt or reset_init sequence
201 * debug entry was already prepared in mips32_prepare_reset_halt()
203 target
->debug_reason
= DBG_REASON_DBGRQ
;
209 /* break processor */
210 mips_ejtag_enter_debug(ejtag_info
);
212 target
->debug_reason
= DBG_REASON_DBGRQ
;
217 static int mips_m4k_assert_reset(struct target
*target
)
219 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
220 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
223 LOG_DEBUG("target->state: %s",
224 target_state_name(target
));
226 enum reset_types jtag_reset_config
= jtag_get_reset_config();
228 if (!(jtag_reset_config
& RESET_HAS_SRST
))
231 if (target
->reset_halt
)
233 /* use hardware to catch reset */
234 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
238 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
243 /* here we should issue a srst only, but we may have to assert trst as well */
244 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
246 jtag_add_reset(1, 1);
250 jtag_add_reset(0, 1);
255 if (mips_m4k
->is_pic32mx
)
259 LOG_DEBUG("Using MTAP reset to reset processor...");
261 /* use microchip specific MTAP reset */
262 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
263 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
265 mchip_cmd
= MCHP_ASERT_RST
;
266 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
267 mchip_cmd
= MCHP_DE_ASSERT_RST
;
268 mips_ejtag_drscan_8(ejtag_info
, &mchip_cmd
);
269 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
273 /* use ejtag reset - not supported by all cores */
274 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
275 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
276 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
277 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
281 target
->state
= TARGET_RESET
;
282 jtag_add_sleep(50000);
284 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
286 if (target
->reset_halt
)
289 if ((retval
= target_halt(target
)) != ERROR_OK
)
296 static int mips_m4k_deassert_reset(struct target
*target
)
298 LOG_DEBUG("target->state: %s",
299 target_state_name(target
));
301 /* deassert reset lines */
302 jtag_add_reset(0, 0);
307 static int mips_m4k_soft_reset_halt(struct target
*target
)
313 static int mips_m4k_single_step_core(struct target
*target
)
315 struct mips32_common
*mips32
= target_to_mips32(target
);
316 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
318 /* configure single step mode */
319 mips_ejtag_config_step(ejtag_info
, 1);
321 /* disable interrupts while stepping */
322 mips32_enable_interrupts(target
, 0);
324 /* exit debug mode */
325 mips_ejtag_exit_debug(ejtag_info
);
327 mips_m4k_debug_entry(target
);
332 static int mips_m4k_resume(struct target
*target
, int current
,
333 uint32_t address
, int handle_breakpoints
, int debug_execution
)
335 struct mips32_common
*mips32
= target_to_mips32(target
);
336 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
337 struct breakpoint
*breakpoint
= NULL
;
340 if (target
->state
!= TARGET_HALTED
)
342 LOG_WARNING("target not halted");
343 return ERROR_TARGET_NOT_HALTED
;
346 if (!debug_execution
)
348 target_free_all_working_areas(target
);
349 mips_m4k_enable_breakpoints(target
);
350 mips_m4k_enable_watchpoints(target
);
353 /* current = 1: continue on current pc, otherwise continue at <address> */
356 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
357 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
358 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
361 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
) {
362 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
365 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
367 mips32_restore_context(target
);
369 /* the front-end may request us not to handle breakpoints */
370 if (handle_breakpoints
)
372 /* Single step past breakpoint at current address */
373 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
375 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
376 mips_m4k_unset_breakpoint(target
, breakpoint
);
377 mips_m4k_single_step_core(target
);
378 mips_m4k_set_breakpoint(target
, breakpoint
);
382 /* enable interrupts if we are running */
383 mips32_enable_interrupts(target
, !debug_execution
);
385 /* exit debug mode */
386 mips_ejtag_exit_debug(ejtag_info
);
387 target
->debug_reason
= DBG_REASON_NOTHALTED
;
389 /* registers are now invalid */
390 register_cache_invalidate(mips32
->core_cache
);
392 if (!debug_execution
)
394 target
->state
= TARGET_RUNNING
;
395 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
396 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
400 target
->state
= TARGET_DEBUG_RUNNING
;
401 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
402 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
408 static int mips_m4k_step(struct target
*target
, int current
,
409 uint32_t address
, int handle_breakpoints
)
411 /* get pointers to arch-specific information */
412 struct mips32_common
*mips32
= target_to_mips32(target
);
413 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
414 struct breakpoint
*breakpoint
= NULL
;
416 if (target
->state
!= TARGET_HALTED
)
418 LOG_WARNING("target not halted");
419 return ERROR_TARGET_NOT_HALTED
;
422 /* current = 1: continue on current pc, otherwise continue at <address> */
424 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
426 /* the front-end may request us not to handle breakpoints */
427 if (handle_breakpoints
) {
428 breakpoint
= breakpoint_find(target
,
429 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
431 mips_m4k_unset_breakpoint(target
, breakpoint
);
434 /* restore context */
435 mips32_restore_context(target
);
437 /* configure single step mode */
438 mips_ejtag_config_step(ejtag_info
, 1);
440 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
442 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
444 /* disable interrupts while stepping */
445 mips32_enable_interrupts(target
, 0);
447 /* exit debug mode */
448 mips_ejtag_exit_debug(ejtag_info
);
450 /* registers are now invalid */
451 register_cache_invalidate(mips32
->core_cache
);
454 mips_m4k_set_breakpoint(target
, breakpoint
);
456 LOG_DEBUG("target stepped ");
458 mips_m4k_debug_entry(target
);
459 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
464 static void mips_m4k_enable_breakpoints(struct target
*target
)
466 struct breakpoint
*breakpoint
= target
->breakpoints
;
468 /* set any pending breakpoints */
471 if (breakpoint
->set
== 0)
472 mips_m4k_set_breakpoint(target
, breakpoint
);
473 breakpoint
= breakpoint
->next
;
477 static int mips_m4k_set_breakpoint(struct target
*target
,
478 struct breakpoint
*breakpoint
)
480 struct mips32_common
*mips32
= target_to_mips32(target
);
481 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
486 LOG_WARNING("breakpoint already set");
490 if (breakpoint
->type
== BKPT_HARD
)
494 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
496 if (bp_num
>= mips32
->num_inst_bpoints
)
498 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
499 breakpoint
->unique_id
);
502 breakpoint
->set
= bp_num
+ 1;
503 comparator_list
[bp_num
].used
= 1;
504 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
505 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
506 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
507 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
508 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
509 breakpoint
->unique_id
,
510 bp_num
, comparator_list
[bp_num
].bp_value
);
512 else if (breakpoint
->type
== BKPT_SOFT
)
514 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
515 if (breakpoint
->length
== 4)
517 uint32_t verify
= 0xffffffff;
519 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
520 breakpoint
->orig_instr
)) != ERROR_OK
)
524 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
529 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
533 if (verify
!= MIPS32_SDBBP
)
535 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
541 uint16_t verify
= 0xffff;
543 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
544 breakpoint
->orig_instr
)) != ERROR_OK
)
548 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
553 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
557 if (verify
!= MIPS16_SDBBP
)
559 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
564 breakpoint
->set
= 20; /* Any nice value but 0 */
570 static int mips_m4k_unset_breakpoint(struct target
*target
,
571 struct breakpoint
*breakpoint
)
573 /* get pointers to arch-specific information */
574 struct mips32_common
*mips32
= target_to_mips32(target
);
575 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
578 if (!breakpoint
->set
)
580 LOG_WARNING("breakpoint not set");
584 if (breakpoint
->type
== BKPT_HARD
)
586 int bp_num
= breakpoint
->set
- 1;
587 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
589 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
590 breakpoint
->unique_id
);
593 LOG_DEBUG("bpid: %d - releasing hw: %d",
594 breakpoint
->unique_id
,
596 comparator_list
[bp_num
].used
= 0;
597 comparator_list
[bp_num
].bp_value
= 0;
598 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
603 /* restore original instruction (kept in target endianness) */
604 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
605 if (breakpoint
->length
== 4)
607 uint32_t current_instr
;
609 /* check that user program has not modified breakpoint instruction */
610 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
611 (uint8_t*)¤t_instr
)) != ERROR_OK
)
615 if (current_instr
== MIPS32_SDBBP
)
617 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
618 breakpoint
->orig_instr
)) != ERROR_OK
)
626 uint16_t current_instr
;
628 /* check that user program has not modified breakpoint instruction */
629 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
630 (uint8_t*)¤t_instr
)) != ERROR_OK
)
635 if (current_instr
== MIPS16_SDBBP
)
637 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
638 breakpoint
->orig_instr
)) != ERROR_OK
)
650 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
652 struct mips32_common
*mips32
= target_to_mips32(target
);
654 if (breakpoint
->type
== BKPT_HARD
)
656 if (mips32
->num_inst_bpoints_avail
< 1)
658 LOG_INFO("no hardware breakpoint available");
659 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
662 mips32
->num_inst_bpoints_avail
--;
665 mips_m4k_set_breakpoint(target
, breakpoint
);
670 static int mips_m4k_remove_breakpoint(struct target
*target
,
671 struct breakpoint
*breakpoint
)
673 /* get pointers to arch-specific information */
674 struct mips32_common
*mips32
= target_to_mips32(target
);
676 if (target
->state
!= TARGET_HALTED
)
678 LOG_WARNING("target not halted");
679 return ERROR_TARGET_NOT_HALTED
;
684 mips_m4k_unset_breakpoint(target
, breakpoint
);
687 if (breakpoint
->type
== BKPT_HARD
)
688 mips32
->num_inst_bpoints_avail
++;
693 static int mips_m4k_set_watchpoint(struct target
*target
,
694 struct watchpoint
*watchpoint
)
696 struct mips32_common
*mips32
= target_to_mips32(target
);
697 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
700 * watchpoint enabled, ignore all byte lanes in value register
701 * and exclude both load and store accesses from watchpoint
702 * condition evaluation
704 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
705 (0xff << EJTAG_DBCn_BLM_SHIFT
);
709 LOG_WARNING("watchpoint already set");
713 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
715 if (wp_num
>= mips32
->num_data_bpoints
)
717 LOG_ERROR("Can not find free FP Comparator");
721 if (watchpoint
->length
!= 4)
723 LOG_ERROR("Only watchpoints of length 4 are supported");
724 return ERROR_TARGET_UNALIGNED_ACCESS
;
727 if (watchpoint
->address
% 4)
729 LOG_ERROR("Watchpoints address should be word aligned");
730 return ERROR_TARGET_UNALIGNED_ACCESS
;
733 switch (watchpoint
->rw
)
736 enable
&= ~EJTAG_DBCn_NOLB
;
739 enable
&= ~EJTAG_DBCn_NOSB
;
742 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
745 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
748 watchpoint
->set
= wp_num
+ 1;
749 comparator_list
[wp_num
].used
= 1;
750 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
751 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
752 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
753 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
754 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
755 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
756 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
761 static int mips_m4k_unset_watchpoint(struct target
*target
,
762 struct watchpoint
*watchpoint
)
764 /* get pointers to arch-specific information */
765 struct mips32_common
*mips32
= target_to_mips32(target
);
766 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
768 if (!watchpoint
->set
)
770 LOG_WARNING("watchpoint not set");
774 int wp_num
= watchpoint
->set
- 1;
775 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
777 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
780 comparator_list
[wp_num
].used
= 0;
781 comparator_list
[wp_num
].bp_value
= 0;
782 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
788 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
790 struct mips32_common
*mips32
= target_to_mips32(target
);
792 if (mips32
->num_data_bpoints_avail
< 1)
794 LOG_INFO("no hardware watchpoints available");
795 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
798 mips32
->num_data_bpoints_avail
--;
800 mips_m4k_set_watchpoint(target
, watchpoint
);
804 static int mips_m4k_remove_watchpoint(struct target
*target
,
805 struct watchpoint
*watchpoint
)
807 /* get pointers to arch-specific information */
808 struct mips32_common
*mips32
= target_to_mips32(target
);
810 if (target
->state
!= TARGET_HALTED
)
812 LOG_WARNING("target not halted");
813 return ERROR_TARGET_NOT_HALTED
;
818 mips_m4k_unset_watchpoint(target
, watchpoint
);
821 mips32
->num_data_bpoints_avail
++;
826 static void mips_m4k_enable_watchpoints(struct target
*target
)
828 struct watchpoint
*watchpoint
= target
->watchpoints
;
830 /* set any pending watchpoints */
833 if (watchpoint
->set
== 0)
834 mips_m4k_set_watchpoint(target
, watchpoint
);
835 watchpoint
= watchpoint
->next
;
839 static int mips_m4k_read_memory(struct target
*target
, uint32_t address
,
840 uint32_t size
, uint32_t count
, uint8_t *buffer
)
842 struct mips32_common
*mips32
= target_to_mips32(target
);
843 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
845 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
847 if (target
->state
!= TARGET_HALTED
)
849 LOG_WARNING("target not halted");
850 return ERROR_TARGET_NOT_HALTED
;
853 /* sanitize arguments */
854 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
855 return ERROR_INVALID_ARGUMENTS
;
857 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
858 return ERROR_TARGET_UNALIGNED_ACCESS
;
860 /* if noDMA off, use DMAACC mode for memory read */
862 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
863 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
865 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
866 if (ERROR_OK
!= retval
)
872 static int mips_m4k_write_memory(struct target
*target
, uint32_t address
,
873 uint32_t size
, uint32_t count
, uint8_t *buffer
)
875 struct mips32_common
*mips32
= target_to_mips32(target
);
876 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
878 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
879 address
, size
, count
);
881 if (target
->state
!= TARGET_HALTED
)
883 LOG_WARNING("target not halted");
884 return ERROR_TARGET_NOT_HALTED
;
887 /* sanitize arguments */
888 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
889 return ERROR_INVALID_ARGUMENTS
;
891 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
892 return ERROR_TARGET_UNALIGNED_ACCESS
;
894 /* if noDMA off, use DMAACC mode for memory write */
895 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
896 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
898 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
901 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
902 struct target
*target
)
904 mips32_build_reg_cache(target
);
909 static int mips_m4k_init_arch_info(struct target
*target
,
910 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
912 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
914 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
916 /* initialize mips4k specific info */
917 mips32_init_arch_info(target
, mips32
, tap
);
918 mips32
->arch_info
= mips_m4k
;
923 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
925 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
927 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
932 static int mips_m4k_examine(struct target
*target
)
935 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
936 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
939 if (!target_was_examined(target
))
941 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
942 ejtag_info
->idcode
= idcode
;
944 if (((idcode
>> 1) & 0x7FF) == 0x29)
946 /* we are using a pic32mx so select ejtag port
947 * as it is not selected by default */
948 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
949 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
950 mips_m4k
->is_pic32mx
= true;
954 /* init rest of ejtag interface */
955 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
958 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
964 static int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
965 uint32_t count
, uint8_t *buffer
)
967 struct mips32_common
*mips32
= target_to_mips32(target
);
968 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
969 struct working_area
*source
;
973 LOG_DEBUG("address: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, count
);
975 if (target
->state
!= TARGET_HALTED
)
977 LOG_WARNING("target not halted");
978 return ERROR_TARGET_NOT_HALTED
;
981 /* check alignment */
983 return ERROR_TARGET_UNALIGNED_ACCESS
;
985 /* Get memory for block write handler */
986 retval
= target_alloc_working_area(target
, MIPS32_FASTDATA_HANDLER_SIZE
, &source
);
987 if (retval
!= ERROR_OK
)
989 LOG_WARNING("No working area available, falling back to non-bulk write");
990 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
993 /* TAP data register is loaded LSB first (little endian) */
994 if (target
->endianness
== TARGET_BIG_ENDIAN
)
997 for(i
= 0; i
< (count
* 4); i
+= 4)
999 t32
= be_to_h_u32((uint8_t *) &buffer
[i
]);
1000 h_u32_to_le(&buffer
[i
], t32
);
1004 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, source
, write_t
, address
,
1005 count
, (uint32_t*) buffer
);
1006 if (retval
!= ERROR_OK
)
1008 /* FASTDATA access failed, try normal memory write */
1009 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
1010 retval
= mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
1014 target_free_working_area(target
, source
);
1019 struct target_type mips_m4k_target
=
1023 .poll
= mips_m4k_poll
,
1024 .arch_state
= mips32_arch_state
,
1026 .target_request_data
= NULL
,
1028 .halt
= mips_m4k_halt
,
1029 .resume
= mips_m4k_resume
,
1030 .step
= mips_m4k_step
,
1032 .assert_reset
= mips_m4k_assert_reset
,
1033 .deassert_reset
= mips_m4k_deassert_reset
,
1034 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
1036 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1038 .read_memory
= mips_m4k_read_memory
,
1039 .write_memory
= mips_m4k_write_memory
,
1040 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
1041 .checksum_memory
= mips32_checksum_memory
,
1042 .blank_check_memory
= mips32_blank_check_memory
,
1044 .run_algorithm
= mips32_run_algorithm
,
1046 .add_breakpoint
= mips_m4k_add_breakpoint
,
1047 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1048 .add_watchpoint
= mips_m4k_add_watchpoint
,
1049 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1051 .target_create
= mips_m4k_target_create
,
1052 .init_target
= mips_m4k_init_target
,
1053 .examine
= mips_m4k_examine
,