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build: fix problems with "struct stat" not being defined under eCos
[openocd/cortex.git] / src / target / arm_adi_v5.c
blobbfa5cb4259de7fe431c02e961ade35973fb6d25c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 */
46
47 /*
48 * Relevant specifications from ARM include:
49 *
50 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
51 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
52 *
53 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
54 * Cortex-M3(tm) TRM, ARM DDI 0337G
55 */
56
57 #ifdef HAVE_CONFIG_H
58 #include "config.h"
59 #endif
60
61 #include "arm_adi_v5.h"
62 #include <helper/time_support.h>
63
64 /*
65 * Transaction Mode:
66 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
67 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
68 * result checking until swjdp_end_transaction()
69 * This must be done before using or deallocating any return variables.
70 * swjdp->trans_mode == TRANS_MODE_ATOMIC
71 * All reads and writes to the AHB bus are checked for valid completion, and return values
72 * are immediatley available.
73 */
74
75
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
77
78 /*
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
81 */
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
83 {
84 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
85 }
86
87 /***************************************************************************
88 * *
89 * DPACC and APACC scanchain access through JTAG-DP *
90 * *
91 ***************************************************************************/
92
93 /**
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
97 *
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
101 *
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
110 */
111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
112 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
113 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
114 {
115 struct arm_jtag *jtag_info = swjdp->jtag_info;
116 struct scan_field fields[2];
117 uint8_t out_addr_buf;
118
119 jtag_set_end_state(TAP_IDLE);
120 arm_jtag_set_instr(jtag_info, instr, NULL);
121
122 /* Add specified number of tck clocks before accessing memory bus */
123
124 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
125 * they provide more time for the (MEM) AP to complete the read ...
126 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
127 */
128 if ((instr == JTAG_DP_APACC)
129 && ((reg_addr == AP_REG_DRW)
130 || ((reg_addr & 0xF0) == AP_REG_BD0))
131 && (swjdp->memaccess_tck != 0))
132 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
133
134 /* Scan out a read or write operation using some DP or AP register.
135 * For APACC access with any sticky error flag set, this is discarded.
136 */
137 fields[0].tap = jtag_info->tap;
138 fields[0].num_bits = 3;
139 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
140 fields[0].out_value = &out_addr_buf;
141 fields[0].in_value = ack;
142
143 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
144 * complete; data we write is discarded, data we read is unpredictable.
145 * When overrun detect is active, STICKYORUN is set.
146 */
147
148 fields[1].tap = jtag_info->tap;
149 fields[1].num_bits = 32;
150 fields[1].out_value = outvalue;
151 fields[1].in_value = invalue;
152
153 jtag_add_dr_scan(2, fields, jtag_get_end_state());
154
155 return ERROR_OK;
156 }
157
158 /* Scan out and in from host ordered uint32_t variables */
159 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
160 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
161 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
162 {
163 struct arm_jtag *jtag_info = swjdp->jtag_info;
164 struct scan_field fields[2];
165 uint8_t out_value_buf[4];
166 uint8_t out_addr_buf;
167
168 jtag_set_end_state(TAP_IDLE);
169 arm_jtag_set_instr(jtag_info, instr, NULL);
170
171 /* Add specified number of tck clocks before accessing memory bus */
172
173 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
174 * they provide more time for the (MEM) AP to complete the read ...
175 */
176 if ((instr == JTAG_DP_APACC)
177 && ((reg_addr == AP_REG_DRW)
178 || ((reg_addr & 0xF0) == AP_REG_BD0))
179 && (swjdp->memaccess_tck != 0))
180 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
181
182 fields[0].tap = jtag_info->tap;
183 fields[0].num_bits = 3;
184 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
185 fields[0].out_value = &out_addr_buf;
186 fields[0].in_value = ack;
187
188 fields[1].tap = jtag_info->tap;
189 fields[1].num_bits = 32;
190 buf_set_u32(out_value_buf, 0, 32, outvalue);
191 fields[1].out_value = out_value_buf;
192 fields[1].in_value = NULL;
193
194 if (invalue)
195 {
196 fields[1].in_value = (uint8_t *)invalue;
197 jtag_add_dr_scan(2, fields, jtag_get_end_state());
198
199 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
200 } else
201 {
202
203 jtag_add_dr_scan(2, fields, jtag_get_end_state());
204 }
205
206 return ERROR_OK;
207 }
208
209 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
210 static int scan_inout_check(struct swjdp_common *swjdp,
211 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
212 uint8_t *outvalue, uint8_t *invalue)
213 {
214 adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
215
216 if ((RnW == DPAP_READ) && (invalue != NULL))
217 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
218 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
219
220 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
221 * ack = OK/FAULT and the check CTRL_STAT
222 */
223 if ((instr == JTAG_DP_APACC)
224 && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
225 return jtagdp_transaction_endcheck(swjdp);
226
227 return ERROR_OK;
228 }
229
230 static int scan_inout_check_u32(struct swjdp_common *swjdp,
231 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
232 uint32_t outvalue, uint32_t *invalue)
233 {
234 /* Issue the read or write */
235 adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
236
237 /* For reads, collect posted value; RDBUFF has no other effect.
238 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
239 */
240 if ((RnW == DPAP_READ) && (invalue != NULL))
241 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
242 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
243
244 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
245 * ack = OK/FAULT and then check CTRL_STAT
246 */
247 if ((instr == JTAG_DP_APACC)
248 && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
249 return jtagdp_transaction_endcheck(swjdp);
250
251 return ERROR_OK;
252 }
253
254 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
255 {
256 int retval;
257 uint32_t ctrlstat;
258
259 /* too expensive to call keep_alive() here */
260
261 #if 0
262 /* Danger!!!! BROKEN!!!! */
263 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
264 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
265 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
266 R956 introduced the check on return value here and now Michael Schwingen reports
267 that this code no longer works....
268
269 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
270 */
271 if ((retval = jtag_execute_queue()) != ERROR_OK)
272 {
273 LOG_ERROR("BUG: Why does this fail the first time????");
274 }
275 /* Why??? second time it works??? */
276 #endif
277
278 /* Post CTRL/STAT read; discard any previous posted read value
279 * but collect its ACK status.
280 */
281 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
282 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
283 if ((retval = jtag_execute_queue()) != ERROR_OK)
284 return retval;
285
286 swjdp->ack = swjdp->ack & 0x7;
287
288 /* common code path avoids calling timeval_ms() */
289 if (swjdp->ack != JTAG_ACK_OK_FAULT)
290 {
291 long long then = timeval_ms();
292
293 while (swjdp->ack != JTAG_ACK_OK_FAULT)
294 {
295 if (swjdp->ack == JTAG_ACK_WAIT)
296 {
297 if ((timeval_ms()-then) > 1000)
298 {
299 /* NOTE: this would be a good spot
300 * to use JTAG_DP_ABORT.
301 */
302 LOG_WARNING("Timeout (1000ms) waiting "
303 "for ACK=OK/FAULT "
304 "in JTAG-DP transaction");
305 return ERROR_JTAG_DEVICE_ERROR;
306 }
307 }
308 else
309 {
310 LOG_WARNING("Invalid ACK %#x "
311 "in JTAG-DP transaction",
312 swjdp->ack);
313 return ERROR_JTAG_DEVICE_ERROR;
314 }
315
316 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
317 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
318 if ((retval = jtag_execute_queue()) != ERROR_OK)
319 return retval;
320 swjdp->ack = swjdp->ack & 0x7;
321 }
322 }
323
324 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
325
326 /* Check for STICKYERR and STICKYORUN */
327 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
328 {
329 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
330 /* Check power to debug regions */
331 if ((ctrlstat & 0xf0000000) != 0xf0000000)
332 ahbap_debugport_init(swjdp);
333 else
334 {
335 uint32_t mem_ap_csw, mem_ap_tar;
336
337 /* Maybe print information about last MEM-AP access */
338 if (swjdp->ap_tar_value != (uint32_t) -1)
339 LOG_DEBUG("MEM-AP Cached values: "
340 "ap_bank 0x%" PRIx32
341 ", ap_csw 0x%" PRIx32
342 ", ap_tar 0x%" PRIx32,
343 swjdp->dp_select_value,
344 swjdp->ap_csw_value,
345 swjdp->ap_tar_value);
346 else
347 LOG_ERROR("Invalid MEM-AP TAR cache!");
348
349 if (ctrlstat & SSTICKYORUN)
350 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
351 "memaccess, or reduce jtag speed");
352
353 if (ctrlstat & SSTICKYERR)
354 LOG_ERROR("JTAG-DP STICKY ERROR");
355
356 /* Clear Sticky Error Bits */
357 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
358 DP_CTRL_STAT, DPAP_WRITE,
359 swjdp->dp_ctrl_stat | SSTICKYORUN
360 | SSTICKYERR, NULL);
361 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
362 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
363 if ((retval = jtag_execute_queue()) != ERROR_OK)
364 return retval;
365
366 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
367
368 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
369 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
370 if ((retval = jtag_execute_queue()) != ERROR_OK)
371 return retval;
372 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
373 PRIx32, mem_ap_csw, mem_ap_tar);
374
375 }
376 if ((retval = jtag_execute_queue()) != ERROR_OK)
377 return retval;
378 return ERROR_JTAG_DEVICE_ERROR;
379 }
380
381 return ERROR_OK;
382 }
383
384 /***************************************************************************
385 * *
386 * DP and MEM-AP register access through APACC and DPACC *
387 * *
388 ***************************************************************************/
389
390 static int dap_dp_write_reg(struct swjdp_common *swjdp,
391 uint32_t value, uint8_t reg_addr)
392 {
393 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
394 reg_addr, DPAP_WRITE, value, NULL);
395 }
396
397 static int dap_dp_read_reg(struct swjdp_common *swjdp,
398 uint32_t *value, uint8_t reg_addr)
399 {
400 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
401 reg_addr, DPAP_READ, 0, value);
402 }
403
404 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
405 {
406 uint32_t select;
407 select = (apsel << 24) & 0xFF000000;
408
409 if (select != swjdp->apsel)
410 {
411 swjdp->apsel = select;
412 /* Switching AP invalidates cached values */
413 swjdp->dp_select_value = -1;
414 swjdp->ap_csw_value = -1;
415 swjdp->ap_tar_value = -1;
416 }
417
418 return ERROR_OK;
419 }
420
421 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
422 {
423 uint32_t select;
424 select = (ap_reg & 0x000000F0);
425
426 if (select != swjdp->dp_select_value)
427 {
428 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
429 swjdp->dp_select_value = select;
430 }
431
432 return ERROR_OK;
433 }
434
435 static int dap_ap_write_reg(struct swjdp_common *swjdp,
436 uint32_t reg_addr, uint8_t *out_value_buf)
437 {
438 dap_dp_bankselect(swjdp, reg_addr);
439 scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
440 DPAP_WRITE, out_value_buf, NULL);
441
442 return ERROR_OK;
443 }
444
445 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
446 {
447 uint8_t out_value_buf[4];
448
449 buf_set_u32(out_value_buf, 0, 32, value);
450 dap_dp_bankselect(swjdp, reg_addr);
451 scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
452 DPAP_WRITE, out_value_buf, NULL);
453
454 return ERROR_OK;
455 }
456
457 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
458 {
459 dap_dp_bankselect(swjdp, reg_addr);
460 scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
461 DPAP_READ, 0, value);
462
463 return ERROR_OK;
464 }
465
466 /***************************************************************************
467 * *
468 * AHB-AP access to memory and system registers on AHB bus *
469 * *
470 ***************************************************************************/
471
472 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
473 {
474 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
475 if (csw != swjdp->ap_csw_value)
476 {
477 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
478 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
479 swjdp->ap_csw_value = csw;
480 }
481 if (tar != swjdp->ap_tar_value)
482 {
483 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
484 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
485 swjdp->ap_tar_value = tar;
486 }
487 if (csw & CSW_ADDRINC_MASK)
488 {
489 /* Do not cache TAR value when autoincrementing */
490 swjdp->ap_tar_value = -1;
491 }
492 return ERROR_OK;
493 }
494
495 /*****************************************************************************
496 * *
497 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
498 * *
499 * Read a uint32_t value from memory or system register *
500 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
501 * but with less overhead *
502 *****************************************************************************/
503 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
504 {
505 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
506
507 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
508 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
509
510 return ERROR_OK;
511 }
512
513 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
514 {
515 mem_ap_read_u32(swjdp, address, value);
516
517 return jtagdp_transaction_endcheck(swjdp);
518 }
519
520 /*****************************************************************************
521 * *
522 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
523 * *
524 * Write a uint32_t value to memory or memory mapped register *
525 * *
526 *****************************************************************************/
527 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
528 {
529 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
530
531 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
532 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
533
534 return ERROR_OK;
535 }
536
537 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
538 {
539 mem_ap_write_u32(swjdp, address, value);
540
541 return jtagdp_transaction_endcheck(swjdp);
542 }
543
544 /*****************************************************************************
545 * *
546 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
547 * *
548 * Write a buffer in target order (little endian) *
549 * *
550 *****************************************************************************/
551 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
552 {
553 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
554 uint32_t adr = address;
555 uint8_t* pBuffer = buffer;
556
557 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
558
559 count >>= 2;
560 wcount = count;
561
562 /* if we have an unaligned access - reorder data */
563 if (adr & 0x3u)
564 {
565 for (writecount = 0; writecount < count; writecount++)
566 {
567 int i;
568 uint32_t outvalue;
569 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
570
571 for (i = 0; i < 4; i++)
572 {
573 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
574 outvalue >>= 8;
575 adr++;
576 }
577 pBuffer += sizeof(uint32_t);
578 }
579 }
580
581 while (wcount > 0)
582 {
583 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
584 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
585 if (wcount < blocksize)
586 blocksize = wcount;
587
588 /* handle unaligned data at 4k boundary */
589 if (blocksize == 0)
590 blocksize = 1;
591
592 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
593
594 for (writecount = 0; writecount < blocksize; writecount++)
595 {
596 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
597 }
598
599 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
600 {
601 wcount = wcount - blocksize;
602 address = address + 4 * blocksize;
603 buffer = buffer + 4 * blocksize;
604 }
605 else
606 {
607 errorcount++;
608 }
609
610 if (errorcount > 1)
611 {
612 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
613 return ERROR_JTAG_DEVICE_ERROR;
614 }
615 }
616
617 return retval;
618 }
619
620 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
621 uint8_t *buffer, int count, uint32_t address)
622 {
623 int retval = ERROR_OK;
624 int wcount, blocksize, writecount, i;
625
626 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
627
628 wcount = count >> 1;
629
630 while (wcount > 0)
631 {
632 int nbytes;
633
634 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
635 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
636
637 if (wcount < blocksize)
638 blocksize = wcount;
639
640 /* handle unaligned data at 4k boundary */
641 if (blocksize == 0)
642 blocksize = 1;
643
644 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
645 writecount = blocksize;
646
647 do
648 {
649 nbytes = MIN((writecount << 1), 4);
650
651 if (nbytes < 4)
652 {
653 if (mem_ap_write_buf_u16(swjdp, buffer,
654 nbytes, address) != ERROR_OK)
655 {
656 LOG_WARNING("Block write error address "
657 "0x%" PRIx32 ", count 0x%x",
658 address, count);
659 return ERROR_JTAG_DEVICE_ERROR;
660 }
661
662 address += nbytes >> 1;
663 }
664 else
665 {
666 uint32_t outvalue;
667 memcpy(&outvalue, buffer, sizeof(uint32_t));
668
669 for (i = 0; i < nbytes; i++)
670 {
671 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
672 outvalue >>= 8;
673 address++;
674 }
675
676 memcpy(&outvalue, buffer, sizeof(uint32_t));
677 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
678 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
679 {
680 LOG_WARNING("Block write error address "
681 "0x%" PRIx32 ", count 0x%x",
682 address, count);
683 return ERROR_JTAG_DEVICE_ERROR;
684 }
685 }
686
687 buffer += nbytes >> 1;
688 writecount -= nbytes >> 1;
689
690 } while (writecount);
691 wcount -= blocksize;
692 }
693
694 return retval;
695 }
696
697 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
698 {
699 int retval = ERROR_OK;
700
701 if (count >= 4)
702 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
703
704 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
705
706 while (count > 0)
707 {
708 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
709 uint16_t svalue;
710 memcpy(&svalue, buffer, sizeof(uint16_t));
711 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
712 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
713 retval = jtagdp_transaction_endcheck(swjdp);
714 count -= 2;
715 address += 2;
716 buffer += 2;
717 }
718
719 return retval;
720 }
721
722 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
723 uint8_t *buffer, int count, uint32_t address)
724 {
725 int retval = ERROR_OK;
726 int wcount, blocksize, writecount, i;
727
728 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
729
730 wcount = count;
731
732 while (wcount > 0)
733 {
734 int nbytes;
735
736 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
737 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
738
739 if (wcount < blocksize)
740 blocksize = wcount;
741
742 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
743 writecount = blocksize;
744
745 do
746 {
747 nbytes = MIN(writecount, 4);
748
749 if (nbytes < 4)
750 {
751 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
752 {
753 LOG_WARNING("Block write error address "
754 "0x%" PRIx32 ", count 0x%x",
755 address, count);
756 return ERROR_JTAG_DEVICE_ERROR;
757 }
758
759 address += nbytes;
760 }
761 else
762 {
763 uint32_t outvalue;
764 memcpy(&outvalue, buffer, sizeof(uint32_t));
765
766 for (i = 0; i < nbytes; i++)
767 {
768 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
769 outvalue >>= 8;
770 address++;
771 }
772
773 memcpy(&outvalue, buffer, sizeof(uint32_t));
774 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
775 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
776 {
777 LOG_WARNING("Block write error address "
778 "0x%" PRIx32 ", count 0x%x",
779 address, count);
780 return ERROR_JTAG_DEVICE_ERROR;
781 }
782 }
783
784 buffer += nbytes;
785 writecount -= nbytes;
786
787 } while (writecount);
788 wcount -= blocksize;
789 }
790
791 return retval;
792 }
793
794 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
795 {
796 int retval = ERROR_OK;
797
798 if (count >= 4)
799 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
800
801 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
802
803 while (count > 0)
804 {
805 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
806 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
807 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
808 retval = jtagdp_transaction_endcheck(swjdp);
809 count--;
810 address++;
811 buffer++;
812 }
813
814 return retval;
815 }
816
817 /*********************************************************************************
818 * *
819 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
820 * *
821 * Read block fast in target order (little endian) into a buffer *
822 * *
823 **********************************************************************************/
824 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
825 {
826 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
827 uint32_t adr = address;
828 uint8_t* pBuffer = buffer;
829
830 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
831
832 count >>= 2;
833 wcount = count;
834
835 while (wcount > 0)
836 {
837 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
838 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
839 if (wcount < blocksize)
840 blocksize = wcount;
841
842 /* handle unaligned data at 4k boundary */
843 if (blocksize == 0)
844 blocksize = 1;
845
846 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
847
848 /* Scan out first read */
849 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
850 DPAP_READ, 0, NULL, NULL);
851 for (readcount = 0; readcount < blocksize - 1; readcount++)
852 {
853 /* Scan out next read; scan in posted value for the
854 * previous one. Assumes read is acked "OK/FAULT",
855 * and CTRL_STAT says that meant "OK".
856 */
857 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
858 DPAP_READ, 0, buffer + 4 * readcount,
859 &swjdp->ack);
860 }
861
862 /* Scan in last posted value; RDBUFF has no other effect,
863 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
864 */
865 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
866 DPAP_READ, 0, buffer + 4 * readcount,
867 &swjdp->ack);
868 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
869 {
870 wcount = wcount - blocksize;
871 address += 4 * blocksize;
872 buffer += 4 * blocksize;
873 }
874 else
875 {
876 errorcount++;
877 }
878
879 if (errorcount > 1)
880 {
881 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
882 return ERROR_JTAG_DEVICE_ERROR;
883 }
884 }
885
886 /* if we have an unaligned access - reorder data */
887 if (adr & 0x3u)
888 {
889 for (readcount = 0; readcount < count; readcount++)
890 {
891 int i;
892 uint32_t data;
893 memcpy(&data, pBuffer, sizeof(uint32_t));
894
895 for (i = 0; i < 4; i++)
896 {
897 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
898 pBuffer++;
899 adr++;
900 }
901 }
902 }
903
904 return retval;
905 }
906
907 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
908 uint8_t *buffer, int count, uint32_t address)
909 {
910 uint32_t invalue;
911 int retval = ERROR_OK;
912 int wcount, blocksize, readcount, i;
913
914 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
915
916 wcount = count >> 1;
917
918 while (wcount > 0)
919 {
920 int nbytes;
921
922 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
923 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
924 if (wcount < blocksize)
925 blocksize = wcount;
926
927 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
928
929 /* handle unaligned data at 4k boundary */
930 if (blocksize == 0)
931 blocksize = 1;
932 readcount = blocksize;
933
934 do
935 {
936 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
937 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
938 {
939 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
940 return ERROR_JTAG_DEVICE_ERROR;
941 }
942
943 nbytes = MIN((readcount << 1), 4);
944
945 for (i = 0; i < nbytes; i++)
946 {
947 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
948 buffer++;
949 address++;
950 }
951
952 readcount -= (nbytes >> 1);
953 } while (readcount);
954 wcount -= blocksize;
955 }
956
957 return retval;
958 }
959
960 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
961 {
962 uint32_t invalue, i;
963 int retval = ERROR_OK;
964
965 if (count >= 4)
966 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
967
968 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
969
970 while (count > 0)
971 {
972 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
973 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
974 retval = jtagdp_transaction_endcheck(swjdp);
975 if (address & 0x1)
976 {
977 for (i = 0; i < 2; i++)
978 {
979 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
980 buffer++;
981 address++;
982 }
983 }
984 else
985 {
986 uint16_t svalue = (invalue >> 8 * (address & 0x3));
987 memcpy(buffer, &svalue, sizeof(uint16_t));
988 address += 2;
989 buffer += 2;
990 }
991 count -= 2;
992 }
993
994 return retval;
995 }
996
997 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
998 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
999 *
1000 * The solution is to arrange for a large out/in scan in this loop and
1001 * and convert data afterwards.
1002 */
1003 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1004 uint8_t *buffer, int count, uint32_t address)
1005 {
1006 uint32_t invalue;
1007 int retval = ERROR_OK;
1008 int wcount, blocksize, readcount, i;
1009
1010 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1011
1012 wcount = count;
1013
1014 while (wcount > 0)
1015 {
1016 int nbytes;
1017
1018 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1019 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1020
1021 if (wcount < blocksize)
1022 blocksize = wcount;
1023
1024 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1025 readcount = blocksize;
1026
1027 do
1028 {
1029 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1030 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1031 {
1032 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1033 return ERROR_JTAG_DEVICE_ERROR;
1034 }
1035
1036 nbytes = MIN(readcount, 4);
1037
1038 for (i = 0; i < nbytes; i++)
1039 {
1040 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1041 buffer++;
1042 address++;
1043 }
1044
1045 readcount -= nbytes;
1046 } while (readcount);
1047 wcount -= blocksize;
1048 }
1049
1050 return retval;
1051 }
1052
1053 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1054 {
1055 uint32_t invalue;
1056 int retval = ERROR_OK;
1057
1058 if (count >= 4)
1059 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1060
1061 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1062
1063 while (count > 0)
1064 {
1065 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1066 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1067 retval = jtagdp_transaction_endcheck(swjdp);
1068 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1069 count--;
1070 address++;
1071 buffer++;
1072 }
1073
1074 return retval;
1075 }
1076
1077 /**
1078 * Initialize a DAP.
1079 *
1080 * @todo Rename this. We also need an initialization scheme which account
1081 * for SWD transports not just JTAG; that will need to address differences
1082 * in layering. (JTAG is useful without any debug target; but not SWD.)
1083 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1084 */
1085 int ahbap_debugport_init(struct swjdp_common *swjdp)
1086 {
1087 uint32_t idreg, romaddr, dummy;
1088 uint32_t ctrlstat;
1089 int cnt = 0;
1090 int retval;
1091
1092 LOG_DEBUG(" ");
1093
1094 /* Default MEM-AP setup.
1095 *
1096 * REVISIT AP #0 may be an inappropriate default for this.
1097 * Should we probe, or receve a hint from the caller?
1098 * Presumably we can ignore the possibility of multiple APs.
1099 */
1100 swjdp->apsel = 0;
1101 swjdp->ap_csw_value = -1;
1102 swjdp->ap_tar_value = -1;
1103
1104 /* DP initialization */
1105 swjdp->trans_mode = TRANS_MODE_ATOMIC;
1106 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1107 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1108 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1109
1110 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1111
1112 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1113 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1114 if ((retval = jtag_execute_queue()) != ERROR_OK)
1115 return retval;
1116
1117 /* Check that we have debug power domains activated */
1118 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1119 {
1120 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1121 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1122 if ((retval = jtag_execute_queue()) != ERROR_OK)
1123 return retval;
1124 alive_sleep(10);
1125 }
1126
1127 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1128 {
1129 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1130 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1131 if ((retval = jtag_execute_queue()) != ERROR_OK)
1132 return retval;
1133 alive_sleep(10);
1134 }
1135
1136 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1137 /* With debug power on we can activate OVERRUN checking */
1138 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1139 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1140 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1141
1142 /*
1143 * REVISIT this isn't actually *initializing* anything in an AP,
1144 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1145 * Should it? If the ROM address is valid, is this the right
1146 * place to scan the table and do any topology detection?
1147 */
1148 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1149 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1150
1151 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1152 ", Debug ROM Address 0x%" PRIx32,
1153 swjdp->apsel, idreg, romaddr);
1154
1155 return ERROR_OK;
1156 }
1157
1158 /* CID interpretation -- see ARM IHI 0029B section 3
1159 * and ARM IHI 0031A table 13-3.
1160 */
1161 static const char *class_description[16] ={
1162 "Reserved", "ROM table", "Reserved", "Reserved",
1163 "Reserved", "Reserved", "Reserved", "Reserved",
1164 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1165 "Reserved", "OptimoDE DESS",
1166 "Generic IP component", "PrimeCell or System component"
1167 };
1168
1169 static bool
1170 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1171 {
1172 return cid3 == 0xb1 && cid2 == 0x05
1173 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1174 }
1175
1176 int dap_info_command(struct command_context *cmd_ctx,
1177 struct swjdp_common *swjdp, int apsel)
1178 {
1179
1180 uint32_t dbgbase, apid;
1181 int romtable_present = 0;
1182 uint8_t mem_ap;
1183 uint32_t apselold;
1184
1185 /* AP address is in bits 31:24 of DP_SELECT */
1186 if (apsel >= 256)
1187 return ERROR_INVALID_ARGUMENTS;
1188
1189 apselold = swjdp->apsel;
1190 dap_ap_select(swjdp, apsel);
1191 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1192 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1193 jtagdp_transaction_endcheck(swjdp);
1194 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1195 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1196 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1197 if (apid)
1198 {
1199 switch (apid&0x0F)
1200 {
1201 case 0:
1202 command_print(cmd_ctx, "\tType is JTAG-AP");
1203 break;
1204 case 1:
1205 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1206 break;
1207 case 2:
1208 command_print(cmd_ctx, "\tType is MEM-AP APB");
1209 break;
1210 default:
1211 command_print(cmd_ctx, "\tUnknown AP type");
1212 break;
1213 }
1214
1215 /* NOTE: a MEM-AP may have a single CoreSight component that's
1216 * not a ROM table ... or have no such components at all.
1217 */
1218 if (mem_ap)
1219 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1220 dbgbase);
1221 }
1222 else
1223 {
1224 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1225 }
1226
1227 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1228 if (romtable_present)
1229 {
1230 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1231 uint16_t entry_offset;
1232
1233 /* bit 16 of apid indicates a memory access port */
1234 if (dbgbase & 0x02)
1235 command_print(cmd_ctx, "\tValid ROM table present");
1236 else
1237 command_print(cmd_ctx, "\tROM table in legacy format");
1238
1239 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1240 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1241 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1242 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1243 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1244 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1245 jtagdp_transaction_endcheck(swjdp);
1246 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1247 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1248 ", CID2 0x%2.2" PRIx32
1249 ", CID1 0x%2.2" PRIx32
1250 ", CID0 0x%2.2" PRIx32,
1251 cid3, cid2, cid1, cid0);
1252 if (memtype & 0x01)
1253 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1254 else
1255 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1256 "Dedicated debug bus.");
1257
1258 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1259 entry_offset = 0;
1260 do
1261 {
1262 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1263 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1264 if (romentry&0x01)
1265 {
1266 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1267 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1268 uint32_t component_start, component_base;
1269 unsigned part_num;
1270 char *type, *full;
1271
1272 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1273 + (int)(romentry & 0xFFFFF000));
1274 mem_ap_read_atomic_u32(swjdp,
1275 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1276 mem_ap_read_atomic_u32(swjdp,
1277 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1278 mem_ap_read_atomic_u32(swjdp,
1279 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1280 mem_ap_read_atomic_u32(swjdp,
1281 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1282 mem_ap_read_atomic_u32(swjdp,
1283 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1284 mem_ap_read_atomic_u32(swjdp,
1285 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1286 mem_ap_read_atomic_u32(swjdp,
1287 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1288 mem_ap_read_atomic_u32(swjdp,
1289 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1290 mem_ap_read_atomic_u32(swjdp,
1291 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1292 component_start = component_base - 0x1000*(c_pid4 >> 4);
1293
1294 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1295 ", start address 0x%" PRIx32,
1296 component_base, component_start);
1297 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1298 (int) (c_cid1 >> 4) & 0xf,
1299 /* See ARM IHI 0029B Table 3-3 */
1300 class_description[(c_cid1 >> 4) & 0xf]);
1301
1302 /* CoreSight component? */
1303 if (((c_cid1 >> 4) & 0x0f) == 9) {
1304 uint32_t devtype;
1305 unsigned minor;
1306 char *major = "Reserved", *subtype = "Reserved";
1307
1308 mem_ap_read_atomic_u32(swjdp,
1309 (component_base & 0xfffff000) | 0xfcc,
1310 &devtype);
1311 minor = (devtype >> 4) & 0x0f;
1312 switch (devtype & 0x0f) {
1313 case 0:
1314 major = "Miscellaneous";
1315 switch (minor) {
1316 case 0:
1317 subtype = "other";
1318 break;
1319 case 4:
1320 subtype = "Validation component";
1321 break;
1322 }
1323 break;
1324 case 1:
1325 major = "Trace Sink";
1326 switch (minor) {
1327 case 0:
1328 subtype = "other";
1329 break;
1330 case 1:
1331 subtype = "Port";
1332 break;
1333 case 2:
1334 subtype = "Buffer";
1335 break;
1336 }
1337 break;
1338 case 2:
1339 major = "Trace Link";
1340 switch (minor) {
1341 case 0:
1342 subtype = "other";
1343 break;
1344 case 1:
1345 subtype = "Funnel, router";
1346 break;
1347 case 2:
1348 subtype = "Filter";
1349 break;
1350 case 3:
1351 subtype = "FIFO, buffer";
1352 break;
1353 }
1354 break;
1355 case 3:
1356 major = "Trace Source";
1357 switch (minor) {
1358 case 0:
1359 subtype = "other";
1360 break;
1361 case 1:
1362 subtype = "Processor";
1363 break;
1364 case 2:
1365 subtype = "DSP";
1366 break;
1367 case 3:
1368 subtype = "Engine/Coprocessor";
1369 break;
1370 case 4:
1371 subtype = "Bus";
1372 break;
1373 }
1374 break;
1375 case 4:
1376 major = "Debug Control";
1377 switch (minor) {
1378 case 0:
1379 subtype = "other";
1380 break;
1381 case 1:
1382 subtype = "Trigger Matrix";
1383 break;
1384 case 2:
1385 subtype = "Debug Auth";
1386 break;
1387 }
1388 break;
1389 case 5:
1390 major = "Debug Logic";
1391 switch (minor) {
1392 case 0:
1393 subtype = "other";
1394 break;
1395 case 1:
1396 subtype = "Processor";
1397 break;
1398 case 2:
1399 subtype = "DSP";
1400 break;
1401 case 3:
1402 subtype = "Engine/Coprocessor";
1403 break;
1404 }
1405 break;
1406 }
1407 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1408 (unsigned) (devtype & 0xff),
1409 major, subtype);
1410 /* REVISIT also show 0xfc8 DevId */
1411 }
1412
1413 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1414 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1415 ", CID2 0x%2.2" PRIx32
1416 ", CID1 0x%2.2" PRIx32
1417 ", CID0 0x%2.2" PRIx32,
1418 c_cid3, c_cid2, c_cid1, c_cid0);
1419 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1420 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1421 (int) c_pid4,
1422 (int) c_pid3, (int) c_pid2,
1423 (int) c_pid1, (int) c_pid0);
1424
1425 /* Part number interpretations are from Cortex
1426 * core specs, the CoreSight components TRM
1427 * (ARM DDI 0314H), and ETM specs; also from
1428 * chip observation (e.g. TI SDTI).
1429 */
1430 part_num = c_pid0 & 0xff;
1431 part_num |= (c_pid1 & 0x0f) << 8;
1432 switch (part_num) {
1433 case 0x000:
1434 type = "Cortex-M3 NVIC";
1435 full = "(Interrupt Controller)";
1436 break;
1437 case 0x001:
1438 type = "Cortex-M3 ITM";
1439 full = "(Instrumentation Trace Module)";
1440 break;
1441 case 0x002:
1442 type = "Cortex-M3 DWT";
1443 full = "(Data Watchpoint and Trace)";
1444 break;
1445 case 0x003:
1446 type = "Cortex-M3 FBP";
1447 full = "(Flash Patch and Breakpoint)";
1448 break;
1449 case 0x00d:
1450 type = "CoreSight ETM11";
1451 full = "(Embedded Trace)";
1452 break;
1453 // case 0x113: what?
1454 case 0x120: /* from OMAP3 memmap */
1455 type = "TI SDTI";
1456 full = "(System Debug Trace Interface)";
1457 break;
1458 case 0x343: /* from OMAP3 memmap */
1459 type = "TI DAPCTL";
1460 full = "";
1461 break;
1462 case 0x4e0:
1463 type = "Cortex-M3 ETM";
1464 full = "(Embedded Trace)";
1465 break;
1466 case 0x906:
1467 type = "Coresight CTI";
1468 full = "(Cross Trigger)";
1469 break;
1470 case 0x907:
1471 type = "Coresight ETB";
1472 full = "(Trace Buffer)";
1473 break;
1474 case 0x908:
1475 type = "Coresight CSTF";
1476 full = "(Trace Funnel)";
1477 break;
1478 case 0x910:
1479 type = "CoreSight ETM9";
1480 full = "(Embedded Trace)";
1481 break;
1482 case 0x912:
1483 type = "Coresight TPIU";
1484 full = "(Trace Port Interface Unit)";
1485 break;
1486 case 0x921:
1487 type = "Cortex-A8 ETM";
1488 full = "(Embedded Trace)";
1489 break;
1490 case 0x922:
1491 type = "Cortex-A8 CTI";
1492 full = "(Cross Trigger)";
1493 break;
1494 case 0x923:
1495 type = "Cortex-M3 TPIU";
1496 full = "(Trace Port Interface Unit)";
1497 break;
1498 case 0xc08:
1499 type = "Cortex-A8 Debug";
1500 full = "(Debug Unit)";
1501 break;
1502 default:
1503 type = "-*- unrecognized -*-";
1504 full = "";
1505 break;
1506 }
1507 command_print(cmd_ctx, "\t\tPart is %s %s",
1508 type, full);
1509 }
1510 else
1511 {
1512 if (romentry)
1513 command_print(cmd_ctx, "\t\tComponent not present");
1514 else
1515 command_print(cmd_ctx, "\t\tEnd of ROM table");
1516 }
1517 entry_offset += 4;
1518 } while (romentry > 0);
1519 }
1520 else
1521 {
1522 command_print(cmd_ctx, "\tNo ROM table present");
1523 }
1524 dap_ap_select(swjdp, apselold);
1525
1526 return ERROR_OK;
1527 }
1528
1529 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1530 {
1531 uint32_t apsel, apselsave, baseaddr;
1532 int retval;
1533
1534 apselsave = swjdp->apsel;
1535 switch (CMD_ARGC) {
1536 case 0:
1537 apsel = swjdp->apsel;
1538 break;
1539 case 1:
1540 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1541 /* AP address is in bits 31:24 of DP_SELECT */
1542 if (apsel >= 256)
1543 return ERROR_INVALID_ARGUMENTS;
1544 break;
1545 default:
1546 return ERROR_COMMAND_SYNTAX_ERROR;
1547 }
1548
1549 if (apselsave != apsel)
1550 dap_ap_select(swjdp, apsel);
1551
1552 /* NOTE: assumes we're talking to a MEM-AP, which
1553 * has a base address. There are other kinds of AP,
1554 * though they're not common for now. This should
1555 * use the ID register to verify it's a MEM-AP.
1556 */
1557 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1558 retval = jtagdp_transaction_endcheck(swjdp);
1559 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1560
1561 if (apselsave != apsel)
1562 dap_ap_select(swjdp, apselsave);
1563
1564 return retval;
1565 }
1566
1567 DAP_COMMAND_HANDLER(dap_memaccess_command)
1568 {
1569 uint32_t memaccess_tck;
1570
1571 switch (CMD_ARGC) {
1572 case 0:
1573 memaccess_tck = swjdp->memaccess_tck;
1574 break;
1575 case 1:
1576 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1577 break;
1578 default:
1579 return ERROR_COMMAND_SYNTAX_ERROR;
1580 }
1581 swjdp->memaccess_tck = memaccess_tck;
1582
1583 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1584 swjdp->memaccess_tck);
1585
1586 return ERROR_OK;
1587 }
1588
1589 DAP_COMMAND_HANDLER(dap_apsel_command)
1590 {
1591 uint32_t apsel, apid;
1592 int retval;
1593
1594 switch (CMD_ARGC) {
1595 case 0:
1596 apsel = 0;
1597 break;
1598 case 1:
1599 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1600 /* AP address is in bits 31:24 of DP_SELECT */
1601 if (apsel >= 256)
1602 return ERROR_INVALID_ARGUMENTS;
1603 break;
1604 default:
1605 return ERROR_COMMAND_SYNTAX_ERROR;
1606 }
1607
1608 dap_ap_select(swjdp, apsel);
1609 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1610 retval = jtagdp_transaction_endcheck(swjdp);
1611 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1612 apsel, apid);
1613
1614 return retval;
1615 }
1616
1617 DAP_COMMAND_HANDLER(dap_apid_command)
1618 {
1619 uint32_t apsel, apselsave, apid;
1620 int retval;
1621
1622 apselsave = swjdp->apsel;
1623 switch (CMD_ARGC) {
1624 case 0:
1625 apsel = swjdp->apsel;
1626 break;
1627 case 1:
1628 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1629 /* AP address is in bits 31:24 of DP_SELECT */
1630 if (apsel >= 256)
1631 return ERROR_INVALID_ARGUMENTS;
1632 break;
1633 default:
1634 return ERROR_COMMAND_SYNTAX_ERROR;
1635 }
1636
1637 if (apselsave != apsel)
1638 dap_ap_select(swjdp, apsel);
1639
1640 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1641 retval = jtagdp_transaction_endcheck(swjdp);
1642 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1643 if (apselsave != apsel)
1644 dap_ap_select(swjdp, apselsave);
1645
1646 return retval;
1647 }
Marex's Cortex A8 development branch