nand flash support for s3c64xx
[openocd/cortex.git] / src / flash / nand / s3c6400.c
blob20b6cc17edd53559b882a8261beb3cd5f31682e9
1 /***************************************************************************
2 * Copyright (C) 2010 by Peter Korsgaard <jacmet@sunsite.dk> *
3 * Heavily based on s3c2412.c by Ben Dooks <ben@fluff.org> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
25 #include "s3c24xx.h"
26 /* s3c64xx uses another base address for the nand controller than 24xx */
27 #undef S3C2410_NFREG
28 #define S3C2410_NFREG(x) ((x) + 0x70200000)
30 NAND_DEVICE_COMMAND_HANDLER(s3c6400_nand_device_command)
32 struct s3c24xx_nand_controller *info;
33 CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
35 /* fill in the address fields for the core device */
36 info->cmd = S3C2440_NFCMD;
37 info->addr = S3C2440_NFADDR;
38 info->data = S3C2440_NFDATA;
39 info->nfstat = S3C2412_NFSTAT;
41 return ERROR_OK;
44 static int s3c6400_init(struct nand_device *nand)
46 struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
47 struct target *target = s3c24xx_info->target;
49 target_write_u32(target, S3C2410_NFCONF,
50 S3C2440_NFCONF_TACLS(3) |
51 S3C2440_NFCONF_TWRPH0(7) |
52 S3C2440_NFCONF_TWRPH1(7) | 4);
54 target_write_u32(target, S3C2440_NFCONT,
55 S3C2412_NFCONT_INIT_MAIN_ECC |
56 S3C2440_NFCONT_ENABLE);
58 return ERROR_OK;
61 struct nand_flash_controller s3c6400_nand_controller = {
62 .name = "s3c6400",
63 .nand_device_command = &s3c6400_nand_device_command,
64 .init = &s3c6400_init,
65 .reset = &s3c24xx_reset,
66 .command = &s3c24xx_command,
67 .address = &s3c24xx_address,
68 .write_data = &s3c24xx_write_data,
69 .read_data = &s3c24xx_read_data,
70 .write_page = s3c24xx_write_page,
71 .read_page = s3c24xx_read_page,
72 .write_block_data = &s3c2440_write_block_data,
73 .read_block_data = &s3c2440_read_block_data,
74 .controller_ready = &s3c24xx_controller_ready,
75 .nand_ready = &s3c2440_nand_ready,