src/jtag/swd.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009-2010 by David Brownell                             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* Bits in SWD command packets, written from host to target
  21  * first bit on the wire is START
  22  */
  23 #define SWD_CMD_START   (1 << 0)        /* always set */
  24 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
  25 #define SWD_CMD_RnW     (1 << 2)                /* set only for read access */
  26 #define SWD_CMD_A32     (3 << 3)                /* bits A[3:2] of register addr */
  27 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  28 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  29 #define SWD_CMD_PARK    (0 << 7)        /* not driven by host (pull high) */
  30 /* followed by TRN, 3-bits of ACK, TRN */
  31
  32 /* pbit16 holds precomputed parity bits for each nibble */
  33 #define pbit(parity, nibble) (parity << nibble)
  34
  35 static const uint16_t pbit16 =
  36         pbit(0, 0) | pbit(1, 1) | pbit(1, 2) | pbit(0, 3)
  37         | pbit(1, 4) | pbit(0, 5) | pbit(0, 6) | pbit(1, 7)
  38         | pbit(1, 8) | pbit(0, 9) | pbit(0, 0xa) | pbit(1, 0xb)
  39         | pbit(0, 0xc) | pbit(1, 0xd) | pbit(1, 0xe) | pbit(0, 0xf);
  40
  41 #define nibble_parity(nibble) (pbit16 & pbit(1, nibble))
  42
  43 /**
  44  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  45  * and swd_driver.write_reg() methods will use directly.
  46  */
  47 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  48 {
  49         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  50                 | (is_read ? SWD_CMD_RnW : 0)
  51                 | ((regnum & 0xc) << 1);
  52
  53         /* 8 cmd bits 4:1 may be set */
  54         if (nibble_parity(cmd >> 1))
  55                 cmd |= SWD_CMD_PARITY;
  56
  57         /* driver handles START, STOP, and TRN */
  58
  59         return cmd;
  60 }
  61
  62 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  63
  64 /*
  65  * FOR NOW  ... SWD driver ops are synchronous and return ACK
  66  * status ... no quueueing.
  67  *
  68  * Individual ops are request/response, and fast-fail permits much
  69  * better fault handling.  Upper layers may queue if desired.
  70  */
  71
  72 struct swd_driver {
  73         /**
  74          * Initialize the debug link so it can perform
  75          * synchronous SWD operations.
  76          * @param trn value from WCR: how many clocks
  77          * to not drive the SWDIO line at certain points in
  78          * the SWD protocol (at least 1 clock).
  79          *
  80          * As an example, this would switch a dual-mode debug adapter
  81          * into SWD mode and out of JTAG mode.
  82           *
  83           * @return ERROR_OK on success, else a negative fault code.
  84          */
  85         int (*init)(uint8_t trn);
  86
  87
  88          /**
  89           * Synchronous read of an AP or DP register.
  90           *
  91           * @param cmd with APnDP/RnW/addr/parity bits
  92           * @param where to store value to read from register
  93           *
  94           * @return SWD_ACK_* code for the transaction
  95           *             or (negative) fault code
  96           */
  97          int (*read_reg)(uint8_t cmd, uint32_t *value);
  98
  99          /**
 100           * Synchronous write of an AP or DP register.
 101           *
 102           * @param cmd with APnDP/RnW/addr/parity bits
 103           * @param value to be written to the register
 104           *
 105           * @return SWD_ACK_* code for the transaction
 106           *             or (negative) fault code
 107           */
 108          int (*write_reg)(uint8_t cmd, uint32_t value);
 109
 110         /* XXX START WITH enough to:
 111          *      init (synch mode, WCR)
 112          *              for async, TRN > 1
 113          *      read IDCODE from DP
 114          */
 115
 116         /**
 117          * Configures data collection from the Single-wire
 118          * trace (SWO) signal.
 119          * @param swo true if SWO data collection should be routed.
 120          *
 121          * For example,  some debug adapters include a UART which
 122          * is normally connected to a microcontroller's UART TX,
 123          * but which may instead be connected to SWO for use in
 124          * collecting ITM (and possibly ETM) trace data.
 125           *
 126           * @return ERROR_OK on success, else a negative fault code.
 127          */
 128         int *(*trace)(bool swo);
 129 };
 130
 131 bool transport_is_swd(void);