1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
28 #include "breakpoints.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
37 /* forward declarations */
38 int mips_m4k_poll(struct target
*target
);
39 int mips_m4k_halt(struct target
*target
);
40 int mips_m4k_soft_reset_halt(struct target
*target
);
41 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
44 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
45 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
);
46 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
);
48 int mips_m4k_examine(struct target
*target
);
49 int mips_m4k_assert_reset(struct target
*target
);
50 int mips_m4k_deassert_reset(struct target
*target
);
51 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
);
53 struct target_type mips_m4k_target
=
57 .poll
= mips_m4k_poll
,
58 .arch_state
= mips32_arch_state
,
60 .target_request_data
= NULL
,
62 .halt
= mips_m4k_halt
,
63 .resume
= mips_m4k_resume
,
64 .step
= mips_m4k_step
,
66 .assert_reset
= mips_m4k_assert_reset
,
67 .deassert_reset
= mips_m4k_deassert_reset
,
68 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
70 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
72 .read_memory
= mips_m4k_read_memory
,
73 .write_memory
= mips_m4k_write_memory
,
74 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
75 .checksum_memory
= mips_m4k_checksum_memory
,
76 .blank_check_memory
= NULL
,
78 .run_algorithm
= mips32_run_algorithm
,
80 .add_breakpoint
= mips_m4k_add_breakpoint
,
81 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
82 .add_watchpoint
= mips_m4k_add_watchpoint
,
83 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
85 .target_create
= mips_m4k_target_create
,
86 .init_target
= mips_m4k_init_target
,
87 .examine
= mips_m4k_examine
,
90 int mips_m4k_examine_debug_reason(struct target
*target
)
92 uint32_t break_status
;
95 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
96 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
98 /* get info about inst breakpoint support */
99 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
101 if (break_status
& 0x1f)
103 /* we have halted on a breakpoint */
104 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
106 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
109 /* get info about data breakpoint support */
110 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &break_status
)) != ERROR_OK
)
112 if (break_status
& 0x1f)
114 /* we have halted on a breakpoint */
115 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
117 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
124 int mips_m4k_debug_entry(struct target
*target
)
126 struct mips32_common
*mips32
= target_to_mips32(target
);
127 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
133 /* make sure break unit configured */
134 mips32_configure_break_unit(target
);
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target
);
139 /* clear single step if active */
140 if (debug_reg
& EJTAG_DEBUG_DSS
)
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info
, 0);
146 mips32_save_context(target
);
148 /* default to mips32 isa, it will be changed below if required */
149 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
151 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
153 if (buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32) & 0x01)
155 /* core is running mips16e isa */
156 mips32
->isa_mode
= MIPS32_ISA_MIPS16E
;
160 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
161 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
162 target_state_name(target
));
167 int mips_m4k_poll(struct target
*target
)
170 struct mips32_common
*mips32
= target_to_mips32(target
);
171 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
172 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
174 /* read ejtag control reg */
175 jtag_set_end_state(TAP_IDLE
);
176 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
177 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
179 /* clear this bit before handling polling
180 * as after reset registers will read zero */
181 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
183 /* we have detected a reset, clear flag
184 * otherwise ejtag will not work */
185 jtag_set_end_state(TAP_IDLE
);
186 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
188 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
189 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
190 LOG_DEBUG("Reset Detected");
193 /* check for processor halted */
194 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
196 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
198 jtag_set_end_state(TAP_IDLE
);
199 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
201 target
->state
= TARGET_HALTED
;
203 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
206 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
208 else if (target
->state
== TARGET_DEBUG_RUNNING
)
210 target
->state
= TARGET_HALTED
;
212 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
215 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
220 target
->state
= TARGET_RUNNING
;
223 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
228 int mips_m4k_halt(struct target
*target
)
230 struct mips32_common
*mips32
= target_to_mips32(target
);
231 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
233 LOG_DEBUG("target->state: %s",
234 target_state_name(target
));
236 if (target
->state
== TARGET_HALTED
)
238 LOG_DEBUG("target was already halted");
242 if (target
->state
== TARGET_UNKNOWN
)
244 LOG_WARNING("target was in unknown state when halt was requested");
247 if (target
->state
== TARGET_RESET
)
249 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
251 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
252 return ERROR_TARGET_FAILURE
;
256 /* we came here in a reset_halt or reset_init sequence
257 * debug entry was already prepared in mips32_prepare_reset_halt()
259 target
->debug_reason
= DBG_REASON_DBGRQ
;
265 /* break processor */
266 mips_ejtag_enter_debug(ejtag_info
);
268 target
->debug_reason
= DBG_REASON_DBGRQ
;
273 int mips_m4k_assert_reset(struct target
*target
)
275 struct mips32_common
*mips32
= target_to_mips32(target
);
276 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
278 LOG_DEBUG("target->state: %s",
279 target_state_name(target
));
281 enum reset_types jtag_reset_config
= jtag_get_reset_config();
282 if (!(jtag_reset_config
& RESET_HAS_SRST
))
284 LOG_ERROR("Can't assert SRST");
288 if (target
->reset_halt
)
290 /* use hardware to catch reset */
291 jtag_set_end_state(TAP_IDLE
);
292 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
296 jtag_set_end_state(TAP_IDLE
);
297 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
300 if (strcmp(target
->variant
, "ejtag_srst") == 0)
302 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
303 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
304 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
305 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
309 /* here we should issue a srst only, but we may have to assert trst as well */
310 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
312 jtag_add_reset(1, 1);
316 jtag_add_reset(0, 1);
320 target
->state
= TARGET_RESET
;
321 jtag_add_sleep(50000);
323 register_cache_invalidate(mips32
->core_cache
);
325 if (target
->reset_halt
)
328 if ((retval
= target_halt(target
)) != ERROR_OK
)
335 int mips_m4k_deassert_reset(struct target
*target
)
337 LOG_DEBUG("target->state: %s",
338 target_state_name(target
));
340 /* deassert reset lines */
341 jtag_add_reset(0, 0);
346 int mips_m4k_soft_reset_halt(struct target
*target
)
352 int mips_m4k_single_step_core(struct target
*target
)
354 struct mips32_common
*mips32
= target_to_mips32(target
);
355 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
357 /* configure single step mode */
358 mips_ejtag_config_step(ejtag_info
, 1);
360 /* disable interrupts while stepping */
361 mips32_enable_interrupts(target
, 0);
363 /* exit debug mode */
364 mips_ejtag_exit_debug(ejtag_info
);
366 mips_m4k_debug_entry(target
);
371 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
373 struct mips32_common
*mips32
= target_to_mips32(target
);
374 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
375 struct breakpoint
*breakpoint
= NULL
;
378 if (target
->state
!= TARGET_HALTED
)
380 LOG_WARNING("target not halted");
381 return ERROR_TARGET_NOT_HALTED
;
384 if (!debug_execution
)
386 target_free_all_working_areas(target
);
387 mips_m4k_enable_breakpoints(target
);
388 mips_m4k_enable_watchpoints(target
);
391 /* current = 1: continue on current pc, otherwise continue at <address> */
394 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
395 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
396 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
399 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
401 mips32_restore_context(target
);
403 /* the front-end may request us not to handle breakpoints */
404 if (handle_breakpoints
)
406 /* Single step past breakpoint at current address */
407 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
409 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
410 mips_m4k_unset_breakpoint(target
, breakpoint
);
411 mips_m4k_single_step_core(target
);
412 mips_m4k_set_breakpoint(target
, breakpoint
);
416 /* enable interrupts if we are running */
417 mips32_enable_interrupts(target
, !debug_execution
);
419 /* exit debug mode */
420 mips_ejtag_exit_debug(ejtag_info
);
421 target
->debug_reason
= DBG_REASON_NOTHALTED
;
423 /* registers are now invalid */
424 register_cache_invalidate(mips32
->core_cache
);
426 if (!debug_execution
)
428 target
->state
= TARGET_RUNNING
;
429 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
430 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
434 target
->state
= TARGET_DEBUG_RUNNING
;
435 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
436 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
442 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
444 /* get pointers to arch-specific information */
445 struct mips32_common
*mips32
= target_to_mips32(target
);
446 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
447 struct breakpoint
*breakpoint
= NULL
;
449 if (target
->state
!= TARGET_HALTED
)
451 LOG_WARNING("target not halted");
452 return ERROR_TARGET_NOT_HALTED
;
455 /* current = 1: continue on current pc, otherwise continue at <address> */
457 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
459 /* the front-end may request us not to handle breakpoints */
460 if (handle_breakpoints
)
461 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
462 mips_m4k_unset_breakpoint(target
, breakpoint
);
464 /* restore context */
465 mips32_restore_context(target
);
467 /* configure single step mode */
468 mips_ejtag_config_step(ejtag_info
, 1);
470 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
472 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
474 /* disable interrupts while stepping */
475 mips32_enable_interrupts(target
, 0);
477 /* exit debug mode */
478 mips_ejtag_exit_debug(ejtag_info
);
480 /* registers are now invalid */
481 register_cache_invalidate(mips32
->core_cache
);
484 mips_m4k_set_breakpoint(target
, breakpoint
);
486 LOG_DEBUG("target stepped ");
488 mips_m4k_debug_entry(target
);
489 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
494 void mips_m4k_enable_breakpoints(struct target
*target
)
496 struct breakpoint
*breakpoint
= target
->breakpoints
;
498 /* set any pending breakpoints */
501 if (breakpoint
->set
== 0)
502 mips_m4k_set_breakpoint(target
, breakpoint
);
503 breakpoint
= breakpoint
->next
;
507 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
509 struct mips32_common
*mips32
= target_to_mips32(target
);
510 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
515 LOG_WARNING("breakpoint already set");
519 if (breakpoint
->type
== BKPT_HARD
)
523 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
525 if (bp_num
>= mips32
->num_inst_bpoints
)
527 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
528 breakpoint
->unique_id
);
531 breakpoint
->set
= bp_num
+ 1;
532 comparator_list
[bp_num
].used
= 1;
533 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
534 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
535 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
536 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
537 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
538 breakpoint
->unique_id
,
539 bp_num
, comparator_list
[bp_num
].bp_value
);
541 else if (breakpoint
->type
== BKPT_SOFT
)
543 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
544 if (breakpoint
->length
== 4)
546 uint32_t verify
= 0xffffffff;
548 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
552 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
557 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
561 if (verify
!= MIPS32_SDBBP
)
563 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
569 uint16_t verify
= 0xffff;
571 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
575 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
580 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
584 if (verify
!= MIPS16_SDBBP
)
586 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
591 breakpoint
->set
= 20; /* Any nice value but 0 */
597 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
599 /* get pointers to arch-specific information */
600 struct mips32_common
*mips32
= target_to_mips32(target
);
601 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
604 if (!breakpoint
->set
)
606 LOG_WARNING("breakpoint not set");
610 if (breakpoint
->type
== BKPT_HARD
)
612 int bp_num
= breakpoint
->set
- 1;
613 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
615 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
616 breakpoint
->unique_id
);
619 LOG_DEBUG("bpid: %d - releasing hw: %d",
620 breakpoint
->unique_id
,
622 comparator_list
[bp_num
].used
= 0;
623 comparator_list
[bp_num
].bp_value
= 0;
624 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
629 /* restore original instruction (kept in target endianness) */
630 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
631 if (breakpoint
->length
== 4)
633 uint32_t current_instr
;
635 /* check that user program has not modified breakpoint instruction */
636 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
640 if (current_instr
== MIPS32_SDBBP
)
642 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
650 uint16_t current_instr
;
652 /* check that user program has not modified breakpoint instruction */
653 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
658 if (current_instr
== MIPS16_SDBBP
)
660 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
672 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
674 struct mips32_common
*mips32
= target_to_mips32(target
);
676 if (breakpoint
->type
== BKPT_HARD
)
678 if (mips32
->num_inst_bpoints_avail
< 1)
680 LOG_INFO("no hardware breakpoint available");
681 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
684 mips32
->num_inst_bpoints_avail
--;
687 mips_m4k_set_breakpoint(target
, breakpoint
);
692 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
694 /* get pointers to arch-specific information */
695 struct mips32_common
*mips32
= target_to_mips32(target
);
697 if (target
->state
!= TARGET_HALTED
)
699 LOG_WARNING("target not halted");
700 return ERROR_TARGET_NOT_HALTED
;
705 mips_m4k_unset_breakpoint(target
, breakpoint
);
708 if (breakpoint
->type
== BKPT_HARD
)
709 mips32
->num_inst_bpoints_avail
++;
714 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
716 struct mips32_common
*mips32
= target_to_mips32(target
);
717 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
720 * watchpoint enabled, ignore all byte lanes in value register
721 * and exclude both load and store accesses from watchpoint
722 * condition evaluation
724 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
725 (0xff << EJTAG_DBCn_BLM_SHIFT
);
729 LOG_WARNING("watchpoint already set");
733 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
735 if (wp_num
>= mips32
->num_data_bpoints
)
737 LOG_ERROR("Can not find free FP Comparator");
741 if (watchpoint
->length
!= 4)
743 LOG_ERROR("Only watchpoints of length 4 are supported");
744 return ERROR_TARGET_UNALIGNED_ACCESS
;
747 if (watchpoint
->address
% 4)
749 LOG_ERROR("Watchpoints address should be word aligned");
750 return ERROR_TARGET_UNALIGNED_ACCESS
;
753 switch (watchpoint
->rw
)
756 enable
&= ~EJTAG_DBCn_NOLB
;
759 enable
&= ~EJTAG_DBCn_NOSB
;
762 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
765 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
768 watchpoint
->set
= wp_num
+ 1;
769 comparator_list
[wp_num
].used
= 1;
770 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
771 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
772 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
773 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
774 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
775 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
776 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
781 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
783 /* get pointers to arch-specific information */
784 struct mips32_common
*mips32
= target_to_mips32(target
);
785 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
787 if (!watchpoint
->set
)
789 LOG_WARNING("watchpoint not set");
793 int wp_num
= watchpoint
->set
- 1;
794 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
796 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
799 comparator_list
[wp_num
].used
= 0;
800 comparator_list
[wp_num
].bp_value
= 0;
801 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
807 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
809 struct mips32_common
*mips32
= target_to_mips32(target
);
811 if (mips32
->num_data_bpoints_avail
< 1)
813 LOG_INFO("no hardware watchpoints available");
814 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
817 mips32
->num_data_bpoints_avail
--;
819 mips_m4k_set_watchpoint(target
, watchpoint
);
823 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
825 /* get pointers to arch-specific information */
826 struct mips32_common
*mips32
= target_to_mips32(target
);
828 if (target
->state
!= TARGET_HALTED
)
830 LOG_WARNING("target not halted");
831 return ERROR_TARGET_NOT_HALTED
;
836 mips_m4k_unset_watchpoint(target
, watchpoint
);
839 mips32
->num_data_bpoints_avail
++;
844 void mips_m4k_enable_watchpoints(struct target
*target
)
846 struct watchpoint
*watchpoint
= target
->watchpoints
;
848 /* set any pending watchpoints */
851 if (watchpoint
->set
== 0)
852 mips_m4k_set_watchpoint(target
, watchpoint
);
853 watchpoint
= watchpoint
->next
;
857 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
859 struct mips32_common
*mips32
= target_to_mips32(target
);
860 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
862 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
864 if (target
->state
!= TARGET_HALTED
)
866 LOG_WARNING("target not halted");
867 return ERROR_TARGET_NOT_HALTED
;
870 /* sanitize arguments */
871 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
872 return ERROR_INVALID_ARGUMENTS
;
874 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
875 return ERROR_TARGET_UNALIGNED_ACCESS
;
877 /* if noDMA off, use DMAACC mode for memory read */
879 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
880 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
882 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
883 if (ERROR_OK
!= retval
)
889 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
891 struct mips32_common
*mips32
= target_to_mips32(target
);
892 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
894 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
896 if (target
->state
!= TARGET_HALTED
)
898 LOG_WARNING("target not halted");
899 return ERROR_TARGET_NOT_HALTED
;
902 /* sanitize arguments */
903 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
904 return ERROR_INVALID_ARGUMENTS
;
906 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
907 return ERROR_TARGET_UNALIGNED_ACCESS
;
909 /* if noDMA off, use DMAACC mode for memory write */
910 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
911 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
913 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
916 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
918 mips32_build_reg_cache(target
);
923 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
925 struct mips32_common
*mips32
= &mips_m4k
->mips32_common
;
927 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
929 /* initialize mips4k specific info */
930 mips32_init_arch_info(target
, mips32
, tap
);
931 mips32
->arch_info
= mips_m4k
;
936 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
938 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
940 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
945 int mips_m4k_examine(struct target
*target
)
948 struct mips32_common
*mips32
= target_to_mips32(target
);
949 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
952 if (!target_was_examined(target
))
954 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
955 ejtag_info
->idcode
= idcode
;
957 if (((idcode
>> 1) & 0x7FF) == 0x29)
959 /* we are using a pic32mx so select ejtag port
960 * as it is not selected by default */
961 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
962 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
966 /* init rest of ejtag interface */
967 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
970 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
976 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
978 struct mips32_common
*mips32
= target_to_mips32(target
);
979 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
980 struct working_area
*source
;
984 LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address
, count
);
986 if (target
->state
!= TARGET_HALTED
)
988 LOG_WARNING("target not halted");
989 return ERROR_TARGET_NOT_HALTED
;
992 /* check alignment */
994 return ERROR_TARGET_UNALIGNED_ACCESS
;
996 /* Get memory for block write handler */
997 retval
= target_alloc_working_area(target
, MIPS32_FASTDATA_HANDLER_SIZE
, &source
);
998 if (retval
!= ERROR_OK
)
1000 LOG_WARNING("No working area available, falling back to non-bulk write");
1001 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
1004 /* TAP data register is loaded LSB first (little endian) */
1005 if (target
->endianness
== TARGET_BIG_ENDIAN
)
1008 for(i
= 0; i
< (count
* 4); i
+= 4)
1010 t32
= be_to_h_u32((uint8_t *) &buffer
[i
]);
1011 h_u32_to_le(&buffer
[i
], t32
);
1015 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, source
, write
, address
, count
, (uint32_t*) buffer
);
1016 if (retval
!= ERROR_OK
)
1018 /* FASTDATA access failed, try normal memory write */
1019 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
1020 retval
= mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
1024 target_free_working_area(target
, source
);
1029 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
)
1031 return ERROR_FAIL
; /* use bulk read method */