1 /***************************************************************************
2 * Copyright (C) 2011 by Rodrigo L. Rosa *
3 * rodrigorosa.LG@gmail.com *
5 * Based on dsp563xx_once.h written by Mathias Kuester *
6 * mkdorg@users.sourceforge.net *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "target_type.h"
29 #include "dsp5680xx.h"
31 struct dsp5680xx_common dsp5680xx_context
;
33 #define _E "DSP5680XX_ERROR:%d\nAt:%s:%d:%s"
34 #define err_check(r, c, m) if (r != ERROR_OK) {LOG_ERROR(_E, c, __func__, __LINE__, m); return r; }
35 #define err_check_propagate(retval) if (retval != ERROR_OK) return retval;
37 int dsp5680xx_execute_queue(void){
39 retval
= jtag_execute_queue();
46 static int reset_jtag(void){
48 tap_state_t states
[2];
49 const char *cp
= "RESET";
50 states
[0] = tap_state_by_name(cp
);
51 retval
= jtag_add_statemove(states
[0]);
52 err_check_propagate(retval
);
53 retval
= jtag_execute_queue();
54 err_check_propagate(retval
);
55 jtag_add_pathmove(0, states
+ 1);
56 retval
= jtag_execute_queue();
60 static int dsp5680xx_drscan(struct target
* target
, uint8_t * data_to_shift_into_dr
, uint8_t * data_shifted_out_of_dr
, int len
){
61 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
64 // - data_to_shift_into_dr: This is the data that will be shifted into the JTAG DR reg.
65 // - data_shifted_out_of_dr: The data that will be shifted out of the JTAG DR reg will stored here
66 // - len: Length of the data to be shifted to JTAG DR.
68 // Note: If data_shifted_out_of_dr == NULL, discard incoming bits.
70 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
71 int retval
= ERROR_OK
;
72 if (NULL
== target
->tap
){
74 err_check(retval
, DSP5680XX_ERROR_JTAG_INVALID_TAP
, "Invalid tap");
78 err_check(retval
, DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW
, "dr_len overflow, maxium is 32");
80 //TODO what values of len are valid for jtag_add_plain_dr_scan?
81 //can i send as many bits as i want?
82 //is the casting necessary?
83 jtag_add_plain_dr_scan(len
,data_to_shift_into_dr
,data_shifted_out_of_dr
, TAP_IDLE
);
84 if(dsp5680xx_context
.flush
){
85 retval
= dsp5680xx_execute_queue();
86 err_check(retval
, DSP5680XX_ERROR_JTAG_DRSCAN
, "drscan failed!");
88 if(data_shifted_out_of_dr
!=NULL
){
89 LOG_DEBUG("Data read (%d bits): 0x%04X",len
,*data_shifted_out_of_dr
);
91 LOG_DEBUG("Data read was discarded.");
95 /** -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
97 * - data_to_shift_into_ir: This is the data that will be shifted into the JTAG IR reg.
98 * - data_shifted_out_of_ir: The data that will be shifted out of the JTAG IR reg will be
100 * - len: Length of the data to be shifted to JTAG IR.
102 * -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
104 static int dsp5680xx_irscan(struct target
*target
, uint32_t *d_in
, uint32_t *d_out
, uint8_t ir_len
)
106 int retval
= ERROR_OK
;
107 uint16_t tap_ir_len
= DSP5680XX_JTAG_MASTER_TAP_IRLEN
;
108 if (NULL
== target
->tap
) {
110 err_check(retval
, DSP5680XX_ERROR_JTAG_INVALID_TAP
, "Invalid tap");
112 if (ir_len
!= target
->tap
->ir_length
) {
113 if (target
->tap
->enabled
) {
115 err_check(retval
, DSP5680XX_ERROR_INVALID_IR_LEN
, "Invalid irlen");
117 struct jtag_tap
*t
= jtag_tap_by_string("dsp568013.chp");
118 if ((t
== NULL
) || ((t
->enabled
) && (ir_len
!= tap_ir_len
))) {
120 err_check(retval
, DSP5680XX_ERROR_INVALID_IR_LEN
, "Invalid irlen");
124 jtag_add_plain_ir_scan(ir_len
, (uint8_t *)d_in
, (uint8_t *)d_out
, TAP_IDLE
);
125 if (dsp5680xx_context
.flush
) {
126 retval
= dsp5680xx_execute_queue();
127 err_check(retval
, DSP5680XX_ERROR_JTAG_IRSCAN
, "irscan failed!");
132 static int dsp5680xx_jtag_status(struct target
*target
, uint8_t * status
){
133 uint32_t read_from_ir
;
136 instr
= JTAG_INSTR_ENABLE_ONCE
;
137 retval
= dsp5680xx_irscan(target
,& instr
, & read_from_ir
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
138 err_check_propagate(retval
);
140 *status
= (uint8_t)read_from_ir
;
144 static int jtag_data_read(struct target
* target
, uint8_t * data_read
, int num_bits
){
145 uint32_t bogus_instr
= 0;
146 int retval
= dsp5680xx_drscan(target
,(uint8_t *) & bogus_instr
,data_read
,num_bits
);
147 LOG_DEBUG("Data read (%d bits): 0x%04X",num_bits
,*data_read
);//TODO remove this or move to jtagio?
151 #define jtag_data_read8(target,data_read) jtag_data_read(target,data_read,8)
152 #define jtag_data_read16(target,data_read) jtag_data_read(target,data_read,16)
153 #define jtag_data_read32(target,data_read) jtag_data_read(target,data_read,32)
155 static uint32_t data_read_dummy
;
156 static int jtag_data_write(struct target
* target
, uint32_t instr
,int num_bits
, uint32_t * data_read
){
158 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & data_read_dummy
,num_bits
);
159 err_check_propagate(retval
);
160 if(data_read
!= NULL
)
161 *data_read
= data_read_dummy
;
165 #define jtag_data_write8(target,instr,data_read) jtag_data_write(target,instr,8,data_read)
166 #define jtag_data_write16(target,instr,data_read) jtag_data_write(target,instr,16,data_read)
167 #define jtag_data_write24(target,instr,data_read) jtag_data_write(target,instr,24,data_read)
168 #define jtag_data_write32(target,instr,data_read) jtag_data_write(target,instr,32,data_read)
171 * Executes EOnCE instruction.
174 * @param instr Instruction to execute.
178 * @param eonce_status Value read from the EOnCE status register.
182 static int eonce_instruction_exec_single(struct target
* target
, uint8_t instr
, uint8_t rw
, uint8_t go
, uint8_t ex
,uint8_t * eonce_status
){
185 uint8_t instr_with_flags
= instr
|(rw
<<7)|(go
<<6)|(ex
<<5);
186 retval
= jtag_data_write(target
,instr_with_flags
,8,&dr_out_tmp
);
187 err_check_propagate(retval
);
188 if(eonce_status
!= NULL
)
189 *eonce_status
= (uint8_t) dr_out_tmp
;
193 ///wrappers for multi opcode instructions
194 #define dsp5680xx_exe_1(target,opcode1,opcode2,opcode3) dsp5680xx_exe1(target,opcode1)
195 #define dsp5680xx_exe_2(target,opcode1,opcode2,opcode3) dsp5680xx_exe2(target,opcode1,opcode2)
196 #define dsp5680xx_exe_3(target,opcode1,opcode2,opcode3) dsp5680xx_exe3(target,opcode1,opcode2,opcode3)
197 #define dsp5680xx_exe_generic(target,words,opcode1,opcode2,opcode3) dsp5680xx_exe_##words(target,opcode1,opcode2,opcode3)
199 /// Executes one word DSP instruction
200 static int dsp5680xx_exe1(struct target
* target
, uint16_t opcode
){
202 retval
= eonce_instruction_exec_single(target
,0x04,0,1,0,NULL
);
203 err_check_propagate(retval
);
204 retval
= jtag_data_write16(target
,opcode
,NULL
);
205 err_check_propagate(retval
);
209 /// Executes two word DSP instruction
210 static int dsp5680xx_exe2(struct target
* target
,uint16_t opcode1
, uint16_t opcode2
){
212 retval
= eonce_instruction_exec_single(target
,0x04,0,0,0,NULL
);
213 err_check_propagate(retval
);
214 retval
= jtag_data_write16(target
,opcode1
,NULL
);
215 err_check_propagate(retval
);
216 retval
= eonce_instruction_exec_single(target
,0x04,0,1,0,NULL
);
217 err_check_propagate(retval
);
218 retval
= jtag_data_write16(target
,opcode2
,NULL
);
219 err_check_propagate(retval
);
223 /// Executes three word DSP instruction
224 static int dsp5680xx_exe3(struct target
* target
, uint16_t opcode1
,uint16_t opcode2
,uint16_t opcode3
){
226 retval
= eonce_instruction_exec_single(target
,0x04,0,0,0,NULL
);
227 err_check_propagate(retval
);
228 retval
= jtag_data_write16(target
,opcode1
,NULL
);
229 err_check_propagate(retval
);
230 retval
= eonce_instruction_exec_single(target
,0x04,0,0,0,NULL
);
231 err_check_propagate(retval
);
232 retval
= jtag_data_write16(target
,opcode2
,NULL
);
233 err_check_propagate(retval
);
234 retval
= eonce_instruction_exec_single(target
,0x04,0,1,0,NULL
);
235 err_check_propagate(retval
);
236 retval
= jtag_data_write16(target
,opcode3
,NULL
);
237 err_check_propagate(retval
);
242 * --------------- Real-time data exchange ---------------
243 * The EOnCE Transmit (OTX) and Receive (ORX) registers are data memory mapped, each with an upper and lower 16 bit word.
244 * Transmit and receive directions are defined from the core’s perspective.
245 * The core writes to the Transmit register and reads the Receive register, and the host through JTAG writes to the Receive register and reads the Transmit register.
246 * Both registers have a combined data memory mapped OTXRXSR which provides indication when each may be accessed.
247 *ref: eonce_rev.1.0_0208081.pdf@36
250 /// writes data into upper ORx register of the target
251 static int core_tx_upper_data(struct target
* target
, uint16_t data
, uint32_t * eonce_status_low
){
253 retval
= eonce_instruction_exec_single(target
,DSP5680XX_ONCE_ORX1
,0,0,0,NULL
);
254 err_check_propagate(retval
);
255 retval
= jtag_data_write16(target
,data
,eonce_status_low
);
256 err_check_propagate(retval
);
260 /// writes data into lower ORx register of the target
261 #define core_tx_lower_data(target,data) eonce_instruction_exec_single(target,DSP5680XX_ONCE_ORX,0,0,0,NULL);\
262 jtag_data_write16(target,data)
267 * @param data_read: Returns the data read from the upper OTX register via JTAG.
268 * @return: Returns an error code (see error code documentation)
270 static int core_rx_upper_data(struct target
* target
, uint8_t * data_read
)
273 retval
= eonce_instruction_exec_single(target
,DSP5680XX_ONCE_OTX1
,1,0,0,NULL
);
274 err_check_propagate(retval
);
275 retval
= jtag_data_read16(target
,data_read
);
276 err_check_propagate(retval
);
283 * @param data_read: Returns the data read from the lower OTX register via JTAG.
284 * @return: Returns an error code (see error code documentation)
286 static int core_rx_lower_data(struct target
* target
,uint8_t * data_read
)
289 retval
= eonce_instruction_exec_single(target
,DSP5680XX_ONCE_OTX
,1,0,0,NULL
);
290 err_check_propagate(retval
);
291 retval
= jtag_data_read16(target
,data_read
);
292 err_check_propagate(retval
);
297 * -- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- --
298 * -- -- -- -- --- -- -- -Core Instructions- -- -- -- --- -- -- -- --- --
299 * -- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- --
303 #define core_move_long_to_r0(target,value) dsp5680xx_exe_generic(target,3,0xe418,value&0xffff,value>>16)
306 #define core_move_long_to_n(target,value) dsp5680xx_exe_generic(target,3,0xe41e,value&0xffff,value>>16)
309 #define core_move_at_r0_to_y0(target) dsp5680xx_exe_generic(target,1,0xF514,0,0)
312 #define core_move_at_r0_to_y1(target) dsp5680xx_exe_generic(target,1,0xF714,0,0)
315 #define core_move_long_at_r0_y(target) dsp5680xx_exe_generic(target,1,0xF734,0,0)
318 #define core_move_y0_at_r0(target) dsp5680xx_exe_generic(target,1,0xd514,0,0)
320 /// bfclr #value,x:(r0)
321 #define eonce_bfclr_at_r0(target,value) dsp5680xx_exe_generic(target,2,0x8040,value,0)
324 #define core_move_value_to_y0(target,value) dsp5680xx_exe_generic(target,2,0x8745,value,0)
326 /// move.w y0,x:(r0)+
327 #define core_move_y0_at_r0_inc(target) dsp5680xx_exe_generic(target,1,0xd500,0,0)
329 /// move.w y0,p:(r0)+
330 #define core_move_y0_at_pr0_inc(target) dsp5680xx_exe_generic(target,1,0x8560,0,0)
332 /// move.w p:(r0)+,y0
333 #define core_move_at_pr0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x8568,0,0)
335 /// move.w p:(r0)+,y1
336 #define core_move_at_pr0_inc_to_y1(target) dsp5680xx_exe_generic(target,1,0x8768,0,0)
339 #define core_move_long_to_r2(target,value) dsp5680xx_exe_generic(target,3,0xe41A,value&0xffff,value>>16)
342 #define core_move_y0_at_r2(target) dsp5680xx_exe_generic(target,1,0xd516,0,0)
344 /// move.w #<value>,x:(r2)
345 #define core_move_value_at_r2(target,value) dsp5680xx_exe_generic(target,2,0x8642,value,0)
347 /// move.w #<value>,x:(r0)
348 #define core_move_value_at_r0(target,value) dsp5680xx_exe_generic(target,2,0x8640,value,0)
350 /// move.w #<value>,x:(R2+<disp>)
351 #define core_move_value_at_r2_disp(target,value,disp) dsp5680xx_exe_generic(target,3,0x8646,value,disp)
354 #define core_move_at_r2_to_y0(target) dsp5680xx_exe_generic(target,1,0xF516,0,0)
356 /// move.w p:(r2)+,y0
357 #define core_move_at_pr2_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x856A,0,0)
360 #define core_move_long_to_r1(target,value) dsp5680xx_exe_generic(target,3,0xE419,value&0xffff,value>>16)
363 #define core_move_long_to_r3(target,value) dsp5680xx_exe_generic(target,3,0xE41B,value&0xffff,value>>16)
365 /// move.w y0,p:(r3)+
366 #define core_move_y0_at_pr3_inc(target) dsp5680xx_exe_generic(target,1,0x8563,0,0)
369 #define core_move_y0_at_r3(target) dsp5680xx_exe_generic(target,1,0xD503,0,0)
372 #define core_move_long_to_r4(target,value) dsp5680xx_exe_generic(target,3,0xE41C,value&0xffff,value>>16)
375 #define core_move_pc_to_r4(target) dsp5680xx_exe_generic(target,1,0xE716,0,0)
378 #define core_move_r4_to_y(target) dsp5680xx_exe_generic(target,1,0xe764,0,0)
380 /// move.w p:(r0)+,y0
381 #define core_move_at_pr0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x8568,0,0)
383 /// move.w x:(r0)+,y0
384 #define core_move_at_r0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0xf500,0,0)
387 #define core_move_at_r0_y0(target) dsp5680xx_exe_generic(target,1,0xF514,0,0)
390 #define eonce_nop(target) dsp5680xx_exe_generic(target,1,0xe700,0,0)
392 /// move.w x:(R2+<disp>),Y0
393 #define core_move_at_r2_disp_to_y0(target,disp) dsp5680xx_exe_generic(target,2,0xF542,disp,0)
396 #define core_move_y1_at_r2(target) dsp5680xx_exe_generic(target,1,0xd716,0,0)
399 #define core_move_y1_at_r0(target) dsp5680xx_exe_generic(target,1,0xd714,0,0)
401 /// move.bp y0,x:(r0)+
402 #define core_move_byte_y0_at_r0(target) dsp5680xx_exe_generic(target,1,0xd5a0,0,0)
404 /// move.w y1,p:(r0)+
405 #define core_move_y1_at_pr0_inc(target) dsp5680xx_exe_generic(target,1,0x8760,0,0)
407 /// move.w y1,x:(r0)+
408 #define core_move_y1_at_r0_inc(target) dsp5680xx_exe_generic(target,1,0xD700,0,0)
411 #define core_move_long_to_y(target,value) dsp5680xx_exe_generic(target,3,0xe417,value&0xffff,value>>16)
413 static int core_move_value_to_pc(struct target
* target
, uint32_t value
){
414 if (!(target
->state
== TARGET_HALTED
)){
415 LOG_ERROR("Target must be halted to move PC. Target state = %d.",target
->state
);
416 return ERROR_TARGET_NOT_HALTED
;
419 retval
= dsp5680xx_exe_generic(target
,3,0xE71E,value
&0xffff,value
>>16);
420 err_check_propagate(retval
);
424 static int eonce_load_TX_RX_to_r0(struct target
* target
)
427 retval
= core_move_long_to_r0(target
,((MC568013_EONCE_TX_RX_ADDR
)+(MC568013_EONCE_OBASE_ADDR
<<16)));
431 static int core_load_TX_RX_high_addr_to_r0(struct target
* target
)
434 retval
= core_move_long_to_r0(target
,((MC568013_EONCE_TX1_RX1_HIGH_ADDR
)+(MC568013_EONCE_OBASE_ADDR
<<16)));
438 static int dsp5680xx_read_core_reg(struct target
* target
, uint8_t reg_addr
, uint16_t * data_read
)
440 //TODO implement a general version of this which matches what openocd uses.
442 uint32_t dummy_data_to_shift_into_dr
;
443 retval
= eonce_instruction_exec_single(target
,reg_addr
,1,0,0,NULL
);
444 err_check_propagate(retval
);
445 retval
= dsp5680xx_drscan(target
,(uint8_t *)& dummy_data_to_shift_into_dr
,(uint8_t *) data_read
, 8);
446 err_check_propagate(retval
);
447 LOG_DEBUG("Reg. data: 0x%02X.",*data_read
);
451 static int eonce_read_status_reg(struct target
* target
, uint16_t * data
){
453 retval
= dsp5680xx_read_core_reg(target
,DSP5680XX_ONCE_OSR
,data
);
454 err_check_propagate(retval
);
459 * Takes the core out of debug mode.
462 * @param eonce_status Data read from the EOnCE status register.
466 static int eonce_exit_debug_mode(struct target
* target
,uint8_t * eonce_status
){
468 retval
= eonce_instruction_exec_single(target
,0x1F,0,0,1,eonce_status
);
469 err_check_propagate(retval
);
473 static int switch_tap(struct target
* target
, struct jtag_tap
* master_tap
,struct jtag_tap
* core_tap
){
474 int retval
= ERROR_OK
;
476 uint32_t ir_out
;//not used, just to make jtag happy.
477 if(master_tap
== NULL
){
478 master_tap
= jtag_tap_by_string("dsp568013.chp");
479 if(master_tap
== NULL
){
481 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER
, "Failed to get master tap.");
484 if(core_tap
== NULL
){
485 core_tap
= jtag_tap_by_string("dsp568013.cpu");
486 if(core_tap
== NULL
){
488 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_FIND_CORE
, "Failed to get core tap.");
492 if(!(((int)master_tap
->enabled
) ^ ((int)core_tap
->enabled
))){
493 LOG_WARNING("Wrong tap enabled/disabled status:\nMaster tap:%d\nCore Tap:%d\nOnly one tap should be enabled at a given time.\n",(int)master_tap
->enabled
,(int)core_tap
->enabled
);
496 if(master_tap
->enabled
){
498 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_MASTER_TAP_IRLEN
);
499 err_check_propagate(retval
);
501 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,4);
502 err_check_propagate(retval
);
503 core_tap
->enabled
= true;
504 master_tap
->enabled
= false;
507 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
508 err_check_propagate(retval
);
510 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,4);
511 err_check_propagate(retval
);
512 core_tap
->enabled
= false;
513 master_tap
->enabled
= true;
519 * Puts the core into debug mode, enabling the EOnCE module.
520 * This will not always work, eonce_enter_debug_mode executes much
521 * more complicated routine, which is guaranteed to work, but requires
522 * a reset. This will complicate comm with the flash module, since
523 * after a reset clock divisors must be set again.
524 * This implementation works most of the time, and is not accesible to the
528 * @param eonce_status Data read from the EOnCE status register.
532 static int eonce_enter_debug_mode_without_reset(struct target
* target
, uint16_t * eonce_status
){
534 uint32_t instr
= JTAG_INSTR_DEBUG_REQUEST
;
535 uint32_t ir_out
;//not used, just to make jtag happy.
537 retval
= dsp5680xx_irscan(target
,& instr
,& ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
538 err_check_propagate(retval
);
540 // Enable EOnCE module
541 instr
= JTAG_INSTR_ENABLE_ONCE
;
542 //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
543 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
544 err_check_propagate(retval
);
545 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
546 err_check_propagate(retval
);
547 // Verify that debug mode is enabled
548 uint16_t data_read_from_dr
;
549 retval
= eonce_read_status_reg(target
,&data_read_from_dr
);
550 err_check_propagate(retval
);
551 if((data_read_from_dr
&0x30) == 0x30){
552 LOG_DEBUG("EOnCE successfully entered debug mode.");
553 target
->state
= TARGET_HALTED
;
556 retval
= ERROR_TARGET_FAILURE
;
558 * No error msg here, since there is still hope with full halting sequence
560 err_check_propagate(retval
);
562 if(eonce_status
!=NULL
)
563 *eonce_status
= data_read_from_dr
;
568 * Puts the core into debug mode, enabling the EOnCE module.
571 * @param eonce_status Data read from the EOnCE status register.
575 static int eonce_enter_debug_mode(struct target
* target
, uint16_t * eonce_status
){
576 int retval
= ERROR_OK
;
577 uint32_t instr
= JTAG_INSTR_DEBUG_REQUEST
;
578 uint32_t ir_out
;//not used, just to make jtag happy.
582 // First try the easy way
583 retval
= eonce_enter_debug_mode_without_reset(target
,eonce_status
);
584 if(retval
== ERROR_OK
)
587 struct jtag_tap
* tap_chp
;
588 struct jtag_tap
* tap_cpu
;
589 tap_chp
= jtag_tap_by_string("dsp568013.chp");
592 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER
, "Failed to get master tap.");
594 tap_cpu
= jtag_tap_by_string("dsp568013.cpu");
597 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_FIND_CORE
, "Failed to get master tap.");
601 tap_chp
->enabled
= true;
602 tap_cpu
->enabled
= false;
604 instr
= MASTER_TAP_CMD_IDCODE
;
605 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_MASTER_TAP_IRLEN
);
606 err_check_propagate(retval
);
607 jtag_add_sleep(TIME_DIV_FREESCALE
*100*1000);
609 // Enable EOnCE module
611 jtag_add_sleep(TIME_DIV_FREESCALE
*200*1000);
612 instr
= 0x0606ffff;// This was selected experimentally.
613 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,32);
614 err_check_propagate(retval
);
615 // ir_out now hold tap idcode
618 tap_chp
->enabled
= true;
619 retval
= switch_tap(target
,tap_chp
,tap_cpu
);
620 err_check_propagate(retval
);
622 instr
= JTAG_INSTR_ENABLE_ONCE
;
623 //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
624 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
625 err_check_propagate(retval
);
626 instr
= JTAG_INSTR_DEBUG_REQUEST
;
627 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
628 err_check_propagate(retval
);
630 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,8);
631 err_check_propagate(retval
);
633 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,8);
634 err_check_propagate(retval
);
635 jtag_add_sleep(TIME_DIV_FREESCALE
*100*1000);
637 jtag_add_sleep(TIME_DIV_FREESCALE
*300*1000);
639 instr
= JTAG_INSTR_ENABLE_ONCE
;
640 //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
641 for(int i
= 0; i
<3; i
++){
642 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
643 err_check_propagate(retval
);
646 for(int i
= 0; i
<3; i
++){
648 dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,16);
650 dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,16);
653 // Verify that debug mode is enabled
654 uint16_t data_read_from_dr
;
655 retval
= eonce_read_status_reg(target
,&data_read_from_dr
);
656 err_check_propagate(retval
);
657 if((data_read_from_dr
&0x30) == 0x30){
658 LOG_DEBUG("EOnCE successfully entered debug mode.");
659 target
->state
= TARGET_HALTED
;
662 const char *msg
= "Failed to set EOnCE module to debug mode";
663 retval
= ERROR_TARGET_FAILURE
;
664 err_check(retval
, DSP5680XX_ERROR_ENTER_DEBUG_MODE
, msg
);
666 if(eonce_status
!=NULL
)
667 *eonce_status
= data_read_from_dr
;
672 * Reads the current value of the program counter and stores it.
678 static int eonce_pc_store(struct target
* target
){
681 retval
= core_move_pc_to_r4(target
);
682 err_check_propagate(retval
);
683 retval
= core_move_r4_to_y(target
);
684 err_check_propagate(retval
);
685 retval
= eonce_load_TX_RX_to_r0(target
);
686 err_check_propagate(retval
);
687 retval
= core_move_y0_at_r0(target
);
688 err_check_propagate(retval
);
689 retval
= core_rx_lower_data(target
,tmp
);
690 err_check_propagate(retval
);
691 LOG_USER("PC value: 0x%X%X\n",tmp
[1],tmp
[0]);
692 dsp5680xx_context
.stored_pc
= (tmp
[0]|(tmp
[1]<<8));
696 static int dsp5680xx_target_create(struct target
*target
, Jim_Interp
* interp
){
697 struct dsp5680xx_common
*dsp5680xx
= calloc(1, sizeof(struct dsp5680xx_common
));
698 target
->arch_info
= dsp5680xx
;
702 static int dsp5680xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
){
703 dsp5680xx_context
.stored_pc
= 0;
704 dsp5680xx_context
.flush
= 1;
705 LOG_DEBUG("target initiated!");
706 //TODO core tap must be enabled before running these commands, currently this is done in the .cfg tcl script.
710 static int dsp5680xx_arch_state(struct target
*target
){
711 LOG_USER("%s not implemented yet.",__FUNCTION__
);
715 int dsp5680xx_target_status(struct target
* target
, uint8_t * jtag_st
, uint16_t * eonce_st
){
716 return target
->state
;
719 static int dsp5680xx_assert_reset(struct target
*target
){
720 target
->state
= TARGET_RESET
;
724 static int dsp5680xx_deassert_reset(struct target
*target
){
725 target
->state
= TARGET_RUNNING
;
729 static int dsp5680xx_halt(struct target
*target
){
731 uint16_t eonce_status
= 0xbeef;
732 if(target
->state
== TARGET_HALTED
){
733 LOG_USER("Target already halted.");
736 retval
= eonce_enter_debug_mode(target
,&eonce_status
);
737 err_check_propagate(retval
);
738 retval
= eonce_pc_store(target
);
739 err_check_propagate(retval
);
740 //TODO is it useful to store the pc?
744 static int dsp5680xx_poll(struct target
*target
){
747 uint8_t eonce_status
;
749 retval
= dsp5680xx_jtag_status(target
,&jtag_status
);
750 err_check_propagate(retval
);
751 if (jtag_status
== JTAG_STATUS_DEBUG
)
752 if (target
->state
!= TARGET_HALTED
){
753 retval
= eonce_enter_debug_mode(target
,&read_tmp
);
754 err_check_propagate(retval
);
755 eonce_status
= (uint8_t) read_tmp
;
756 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_DEBUG_M
){
757 LOG_WARNING("%s: Failed to put EOnCE in debug mode. Is flash locked?...",__FUNCTION__
);
758 return ERROR_TARGET_FAILURE
;
760 target
->state
= TARGET_HALTED
;
764 if (jtag_status
== JTAG_STATUS_NORMAL
){
765 if(target
->state
== TARGET_RESET
){
766 retval
= dsp5680xx_halt(target
);
767 err_check_propagate(retval
);
768 retval
= eonce_exit_debug_mode(target
,&eonce_status
);
769 err_check_propagate(retval
);
770 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_NORMAL_M
){
771 LOG_WARNING("%s: JTAG running, but cannot make EOnCE run. Try resetting...",__FUNCTION__
);
772 return ERROR_TARGET_FAILURE
;
774 target
->state
= TARGET_RUNNING
;
778 if(target
->state
!= TARGET_RUNNING
){
779 retval
= eonce_read_status_reg(target
,&read_tmp
);
780 err_check_propagate(retval
);
781 eonce_status
= (uint8_t) read_tmp
;
782 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_NORMAL_M
){
783 LOG_WARNING("Inconsistent target status. Restart!");
784 return ERROR_TARGET_FAILURE
;
787 target
->state
= TARGET_RUNNING
;
790 if(jtag_status
== JTAG_STATUS_DEAD
){
791 LOG_ERROR("%s: Cannot communicate with JTAG. Check connection...",__FUNCTION__
);
792 target
->state
= TARGET_UNKNOWN
;
793 return ERROR_TARGET_FAILURE
;
795 if (target
->state
== TARGET_UNKNOWN
){
796 LOG_ERROR("%s: Target status invalid - communication failure",__FUNCTION__
);
797 return ERROR_TARGET_FAILURE
;
802 static int dsp5680xx_resume(struct target
*target
, int current
, uint32_t address
,int handle_breakpoints
, int debug_execution
){
803 if(target
->state
== TARGET_RUNNING
){
804 LOG_USER("Target already running.");
808 uint8_t eonce_status
;
810 retval
= core_move_value_to_pc(target
,address
);
811 err_check_propagate(retval
);
816 retval
= eonce_exit_debug_mode(target
,&eonce_status
);
817 err_check_propagate(retval
);
818 if(eonce_status
== DSP5680XX_ONCE_OSCR_NORMAL_M
)
822 retval
= ERROR_TARGET_FAILURE
;
823 err_check(retval
, DSP5680XX_ERROR_RESUME
, "Failed to resume...");
825 target
->state
= TARGET_RUNNING
;
827 LOG_DEBUG("EOnCE status: 0x%02X.",eonce_status
);
837 * The value of @address determines if it corresponds to P: (program) or X: (data) memory. If the address is over 0x200000 then it is considered X: memory, and @pmem = 0.
838 * The special case of 0xFFXXXX is not modified, since it allows to read out the memory mapped EOnCE registers.
845 static int dsp5680xx_convert_address(uint32_t * address
, int * pmem
){
846 // Distinguish data memory (x:) from program memory (p:) by the address.
847 // Addresses over S_FILE_DATA_OFFSET are considered (x:) memory.
848 if(*address
>= S_FILE_DATA_OFFSET
){
850 if(((*address
)&0xff0000)!=0xff0000)
851 *address
-= S_FILE_DATA_OFFSET
;
856 static int dsp5680xx_read_16_single(struct target
* target
, uint32_t address
, uint8_t * data_read
, int r_pmem
){
858 retval
= core_move_long_to_r0(target
,address
);
859 err_check_propagate(retval
);
861 retval
= core_move_at_pr0_inc_to_y0(target
);
863 retval
= core_move_at_r0_to_y0(target
);
864 err_check_propagate(retval
);
865 retval
= eonce_load_TX_RX_to_r0(target
);
866 err_check_propagate(retval
);
867 retval
= core_move_y0_at_r0(target
);
868 err_check_propagate(retval
);
869 // at this point the data i want is at the reg eonce can read
870 retval
= core_rx_lower_data(target
,data_read
);
871 err_check_propagate(retval
);
872 LOG_DEBUG("%s: Data read from 0x%06X: 0x%02X%02X",__FUNCTION__
, address
,data_read
[1],data_read
[0]);
876 static int dsp5680xx_read_32_single(struct target
* target
, uint32_t address
, uint8_t * data_read
, int r_pmem
){
878 address
= (address
& 0xFFFFFE);
879 // Get data to an intermediate register
880 retval
= core_move_long_to_r0(target
,address
);
881 err_check_propagate(retval
);
883 retval
= core_move_at_pr0_inc_to_y0(target
);
884 err_check_propagate(retval
);
885 retval
= core_move_at_pr0_inc_to_y1(target
);
886 err_check_propagate(retval
);
888 retval
= core_move_at_r0_inc_to_y0(target
);
889 err_check_propagate(retval
);
890 retval
= core_move_at_r0_to_y1(target
);
891 err_check_propagate(retval
);
893 // Get lower part of data to TX/RX
894 retval
= eonce_load_TX_RX_to_r0(target
);
895 err_check_propagate(retval
);
896 retval
= core_move_y0_at_r0_inc(target
); // This also load TX/RX high to r0
897 err_check_propagate(retval
);
898 // Get upper part of data to TX/RX
899 retval
= core_move_y1_at_r0(target
);
900 err_check_propagate(retval
);
901 // at this point the data i want is at the reg eonce can read
902 retval
= core_rx_lower_data(target
,data_read
);
903 err_check_propagate(retval
);
904 retval
= core_rx_upper_data(target
,data_read
+2);
905 err_check_propagate(retval
);
909 static int dsp5680xx_read(struct target
* target
, uint32_t address
, unsigned size
, unsigned count
, uint8_t * buffer
){
910 if(target
->state
!= TARGET_HALTED
){
911 LOG_USER("Target must be halted.");
914 int retval
= ERROR_OK
;
917 retval
= dsp5680xx_convert_address(&address
, &pmem
);
918 err_check_propagate(retval
);
920 dsp5680xx_context
.flush
= 0;
921 int counter
= FLUSH_COUNT_READ_WRITE
;
923 for (unsigned i
=0; i
<count
; i
++){
925 dsp5680xx_context
.flush
= 1;
926 counter
= FLUSH_COUNT_READ_WRITE
;
931 retval
= dsp5680xx_read_16_single(target
, address
+ i
/2, buffer
+ i
, pmem
);
935 retval
= dsp5680xx_read_16_single(target
, address
+ i
, buffer
+2*i
, pmem
);
938 retval
= dsp5680xx_read_32_single(target
, address
+ 2*i
, buffer
+ 4*i
, pmem
);
941 LOG_USER("%s: Invalid read size.",__FUNCTION__
);
944 err_check_propagate(retval
);
945 dsp5680xx_context
.flush
= 0;
948 dsp5680xx_context
.flush
= 1;
949 retval
= dsp5680xx_execute_queue();
950 err_check_propagate(retval
);
955 static int dsp5680xx_write_16_single(struct target
*target
, uint32_t address
, uint16_t data
, uint8_t w_pmem
){
957 retval
= core_move_long_to_r0(target
,address
);
958 err_check_propagate(retval
);
960 retval
= core_move_value_to_y0(target
,data
);
961 err_check_propagate(retval
);
962 retval
= core_move_y0_at_pr0_inc(target
);
963 err_check_propagate(retval
);
965 retval
= core_move_value_at_r0(target
,data
);
966 err_check_propagate(retval
);
971 static int dsp5680xx_write_32_single(struct target
*target
, uint32_t address
, uint32_t data
, int w_pmem
){
973 retval
= core_move_long_to_r0(target
,address
);
974 err_check_propagate(retval
);
975 retval
= core_move_long_to_y(target
,data
);
976 err_check_propagate(retval
);
978 retval
= core_move_y0_at_pr0_inc(target
);
980 retval
= core_move_y0_at_r0_inc(target
);
981 err_check_propagate(retval
);
983 retval
= core_move_y1_at_pr0_inc(target
);
985 retval
= core_move_y1_at_r0_inc(target
);
986 err_check_propagate(retval
);
990 static int dsp5680xx_write_8(struct target
* target
, uint32_t address
, uint32_t count
, const uint8_t * data
, int pmem
){
991 if(target
->state
!= TARGET_HALTED
){
992 LOG_ERROR("%s: Target must be halted.",__FUNCTION__
);
999 int counter
= FLUSH_COUNT_READ_WRITE
;
1000 for(iter
= 0; iter
<count
/2; iter
++){
1002 dsp5680xx_context
.flush
= 1;
1003 counter
= FLUSH_COUNT_READ_WRITE
;
1005 data_16
=(data
[2*iter
]|(data
[2*iter
+1]<<8));
1006 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data_16
, pmem
);
1007 if(retval
!= ERROR_OK
){
1008 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
1009 dsp5680xx_context
.flush
= 1;
1012 dsp5680xx_context
.flush
= 0;
1014 dsp5680xx_context
.flush
= 1;
1016 // Only one byte left, let's not overwrite the other byte (mem is 16bit)
1017 // Need to retrieve the part we do not want to overwrite.
1019 if((count
==1)||(count
%2)){
1020 retval
= dsp5680xx_read(target
,address
+iter
,1,1,(uint8_t *)&data_old
);
1021 err_check_propagate(retval
);
1023 data_old
=(((data_old
&0xff)<<8)|data
[0]);// preserve upper byte
1025 data_old
=(((data_old
&0xff)<<8)|data
[2*iter
+1]);
1026 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data_old
, pmem
);
1027 err_check_propagate(retval
);
1032 static int dsp5680xx_write_16(struct target
* target
, uint32_t address
, uint32_t count
, const uint8_t * data
, int pmem
){
1033 int retval
= ERROR_OK
;
1034 if(target
->state
!= TARGET_HALTED
){
1035 retval
= ERROR_TARGET_NOT_HALTED
;
1036 err_check(retval
, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING
, "Target must be halted.");
1039 int counter
= FLUSH_COUNT_READ_WRITE
;
1041 for(iter
= 0; iter
<count
; iter
++){
1043 dsp5680xx_context
.flush
= 1;
1044 counter
= FLUSH_COUNT_READ_WRITE
;
1046 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data
[iter
], pmem
);
1047 if(retval
!= ERROR_OK
){
1048 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
1049 dsp5680xx_context
.flush
= 1;
1052 dsp5680xx_context
.flush
= 0;
1054 dsp5680xx_context
.flush
= 1;
1058 static int dsp5680xx_write_32(struct target
* target
, uint32_t address
, uint32_t count
, const uint8_t * data
, int pmem
){
1059 int retval
= ERROR_OK
;
1060 if(target
->state
!= TARGET_HALTED
){
1061 retval
= ERROR_TARGET_NOT_HALTED
;
1062 err_check(retval
, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING
, "Target must be halted.");
1065 int counter
= FLUSH_COUNT_READ_WRITE
;
1067 for(iter
= 0; iter
<count
; iter
++){
1069 dsp5680xx_context
.flush
= 1;
1070 counter
= FLUSH_COUNT_READ_WRITE
;
1072 retval
= dsp5680xx_write_32_single(target
,address
+(iter
<<1),data
[iter
], pmem
);
1073 if(retval
!= ERROR_OK
){
1074 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
1075 dsp5680xx_context
.flush
= 1;
1078 dsp5680xx_context
.flush
= 0;
1080 dsp5680xx_context
.flush
= 1;
1085 * Writes @buffer to memory.
1086 * The parameter @address determines whether @buffer should be written to P: (program) memory or X: (data) memory.
1090 * @param size Bytes (1), Half words (2), Words (4).
1091 * @param count In bytes.
1096 static int dsp5680xx_write(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t * buffer
){
1097 //TODO Cannot write 32bit to odd address, will write 0x12345678 as 0x5678 0x0012
1098 if(target
->state
!= TARGET_HALTED
){
1099 err_check(ERROR_FAIL
, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING
, "Target must be halted.");
1103 retval
= dsp5680xx_convert_address(&address
, &p_mem
);
1104 err_check_propagate(retval
);
1108 retval
= dsp5680xx_write_8(target
, address
, count
, buffer
, p_mem
);
1111 retval
= dsp5680xx_write_16(target
, address
, count
, buffer
, p_mem
);
1114 retval
= dsp5680xx_write_32(target
, address
, count
, buffer
, p_mem
);
1117 retval
= ERROR_TARGET_DATA_ABORT
;
1118 err_check(retval
, DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT
, "Invalid data size.");
1124 static int dsp5680xx_bulk_write_memory(struct target
* target
,uint32_t address
, uint32_t aligned
, const uint8_t * buffer
){
1125 LOG_ERROR("Not implemented yet.");
1129 static int dsp5680xx_write_buffer(struct target
* target
, uint32_t address
, uint32_t size
, const uint8_t * buffer
){
1130 if(target
->state
!= TARGET_HALTED
){
1131 LOG_USER("Target must be halted.");
1134 return dsp5680xx_write(target
, address
, 1, size
, buffer
);
1138 * This function is called by verify_image, it is used to read data from memory.
1141 * @param address Word addressing.
1142 * @param size In bytes.
1147 static int dsp5680xx_read_buffer(struct target
* target
, uint32_t address
, uint32_t size
, uint8_t * buffer
){
1148 if(target
->state
!= TARGET_HALTED
){
1149 LOG_USER("Target must be halted.");
1152 // The "/2" solves the byte/word addressing issue.
1153 return dsp5680xx_read(target
,address
,2,size
/2,buffer
);
1157 * This function is not implemented.
1158 * It returns an error in order to get OpenOCD to do read out the data and calculate the CRC, or try a binary comparison.
1161 * @param address Start address of the image.
1162 * @param size In bytes.
1167 static int dsp5680xx_checksum_memory(struct target
* target
, uint32_t address
, uint32_t size
, uint32_t * checksum
){
1172 * Calculates a signature over @word_count words in the data from @buff16. The algorithm used is the same the FM uses, so the @return may be used to compare with the one generated by the FM module, and check if flashing was successful.
1173 * This algorithm is based on the perl script available from the Freescale website at FAQ 25630.
1180 static int perl_crc(uint8_t * buff8
,uint32_t word_count
){
1181 uint16_t checksum
= 0xffff;
1182 uint16_t data
,fbmisr
;
1184 for(i
=0;i
<word_count
;i
++){
1185 data
= (buff8
[2*i
]|(buff8
[2*i
+1]<<8));
1186 fbmisr
= (checksum
& 2)>>1 ^ (checksum
& 4)>>2 ^ (checksum
& 16)>>4 ^ (checksum
& 0x8000)>>15;
1187 checksum
= (data
^ ((checksum
<< 1) | fbmisr
));
1190 for(;!(i
&0x80000000);i
--){
1191 data
= (buff8
[2*i
]|(buff8
[2*i
+1]<<8));
1192 fbmisr
= (checksum
& 2)>>1 ^ (checksum
& 4)>>2 ^ (checksum
& 16)>>4 ^ (checksum
& 0x8000)>>15;
1193 checksum
= (data
^ ((checksum
<< 1) | fbmisr
));
1199 * Resets the SIM. (System Integration Module).
1205 int dsp5680xx_f_SIM_reset(struct target
* target
){
1206 int retval
= ERROR_OK
;
1207 uint16_t sim_cmd
= SIM_CMD_RESET
;
1209 if(strcmp(target
->tap
->chip
,"dsp568013")==0){
1210 sim_addr
= MC568013_SIM_BASE_ADDR
+S_FILE_DATA_OFFSET
;
1211 retval
= dsp5680xx_write(target
,sim_addr
,1,2,(const uint8_t *)&sim_cmd
);
1212 err_check_propagate(retval
);
1218 * Halts the core and resets the SIM. (System Integration Module).
1224 static int dsp5680xx_soft_reset_halt(struct target
*target
){
1225 //TODO is this what this function is expected to do...?
1227 retval
= dsp5680xx_halt(target
);
1228 err_check_propagate(retval
);
1229 retval
= dsp5680xx_f_SIM_reset(target
);
1230 err_check_propagate(retval
);
1234 int dsp5680xx_f_protect_check(struct target
* target
, uint16_t * protected) {
1236 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1237 retval
= dsp5680xx_halt(target
);
1238 err_check_propagate(retval
);
1240 if(protected == NULL
){
1241 const char *msg
= "NULL pointer not valid.";
1242 err_check(ERROR_FAIL
, DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS
, msg
);
1244 retval
= dsp5680xx_read_16_single(target
,HFM_BASE_ADDR
|HFM_PROT
,(uint8_t *)protected,0);
1245 err_check_propagate(retval
);
1250 * Executes a command on the FM module. Some commands use the parameters @address and @data, others ignore them.
1253 * @param command Command to execute.
1254 * @param address Command parameter.
1255 * @param data Command parameter.
1256 * @param hfm_ustat FM status register.
1257 * @param pmem Address is P: (program) memory (@pmem==1) or X: (data) memory (@pmem==0)
1261 static int dsp5680xx_f_execute_command(struct target
* target
, uint16_t command
, uint32_t address
, uint32_t data
, uint16_t * hfm_ustat
, int pmem
){
1263 retval
= core_load_TX_RX_high_addr_to_r0(target
);
1264 err_check_propagate(retval
);
1265 retval
= core_move_long_to_r2(target
,HFM_BASE_ADDR
);
1266 err_check_propagate(retval
);
1270 retval
= core_move_at_r2_disp_to_y0(target
,HFM_USTAT
); // read HMF_USTAT
1271 err_check_propagate(retval
);
1272 retval
= core_move_y0_at_r0(target
);
1273 err_check_propagate(retval
);
1274 retval
= core_rx_upper_data(target
,i
);
1275 err_check_propagate(retval
);
1276 if((watchdog
--)==1){
1277 retval
= ERROR_TARGET_FAILURE
;
1278 const char *msg
= "Timed out waiting for FM to finish old command.";
1279 err_check(retval
, DSP5680XX_ERROR_FM_BUSY
, msg
);
1281 }while (!(i
[0]&0x40)); // wait until current command is complete
1283 dsp5680xx_context
.flush
= 0;
1285 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_CNFG
); // write to HFM_CNFG (lock=0, select bank) -- flash_desc.bank&0x03,0x01 == 0x00,0x01 ???
1286 err_check_propagate(retval
);
1287 retval
= core_move_value_at_r2_disp(target
,0x04,HFM_USTAT
); // write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
1288 err_check_propagate(retval
);
1289 retval
= core_move_value_at_r2_disp(target
,0x10,HFM_USTAT
); // clear only one bit at a time
1290 err_check_propagate(retval
);
1291 retval
= core_move_value_at_r2_disp(target
,0x20,HFM_USTAT
);
1292 err_check_propagate(retval
);
1293 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_PROT
); // write to HMF_PROT, clear protection
1294 err_check_propagate(retval
);
1295 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_PROTB
); // write to HMF_PROTB, clear protection
1296 err_check_propagate(retval
);
1297 retval
= core_move_value_to_y0(target
,data
);
1298 err_check_propagate(retval
);
1299 retval
= core_move_long_to_r3(target
,address
); // write to the flash block
1300 err_check_propagate(retval
);
1302 retval
= core_move_y0_at_pr3_inc(target
);
1303 err_check_propagate(retval
);
1305 retval
= core_move_y0_at_r3(target
);
1306 err_check_propagate(retval
);
1308 retval
= core_move_value_at_r2_disp(target
,command
,HFM_CMD
); // write command to the HFM_CMD reg
1309 err_check_propagate(retval
);
1310 retval
= core_move_value_at_r2_disp(target
,0x80,HFM_USTAT
); // start the command
1311 err_check_propagate(retval
);
1313 dsp5680xx_context
.flush
= 1;
1314 retval
= dsp5680xx_execute_queue();
1315 err_check_propagate(retval
);
1319 retval
= core_move_at_r2_disp_to_y0(target
,HFM_USTAT
); // read HMF_USTAT
1320 err_check_propagate(retval
);
1321 retval
= core_move_y0_at_r0(target
);
1322 err_check_propagate(retval
);
1323 retval
= core_rx_upper_data(target
,i
);
1324 err_check_propagate(retval
);
1325 if((watchdog
--)==1){
1326 retval
= ERROR_TARGET_FAILURE
;
1327 err_check(retval
, DSP5680XX_ERROR_FM_CMD_TIMED_OUT
, "FM execution did not finish.");
1329 }while (!(i
[0]&0x40)); // wait until the command is complete
1330 *hfm_ustat
= ((i
[0]<<8)|(i
[1]));
1331 if (i
[0]&HFM_USTAT_MASK_PVIOL_ACCER
){
1332 retval
= ERROR_TARGET_FAILURE
;
1333 const char *msg
= "pviol and/or accer bits set. HFM command execution error";
1334 err_check(retval
, DSP5680XX_ERROR_FM_EXEC
, msg
);
1340 * Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.)
1346 static int set_fm_ck_div(struct target
* target
){
1349 retval
= core_move_long_to_r2(target
,HFM_BASE_ADDR
);
1350 err_check_propagate(retval
);
1351 retval
= core_load_TX_RX_high_addr_to_r0(target
);
1352 err_check_propagate(retval
);
1353 retval
= core_move_at_r2_to_y0(target
);// read HFM_CLKD
1354 err_check_propagate(retval
);
1355 retval
= core_move_y0_at_r0(target
);
1356 err_check_propagate(retval
);
1357 retval
= core_rx_upper_data(target
,i
);
1358 err_check_propagate(retval
);
1359 unsigned int hfm_at_wrong_value
= 0;
1360 if ((i
[0]&0x7f)!=HFM_CLK_DEFAULT
) {
1361 LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",i
[0]&0x7f);
1362 hfm_at_wrong_value
= 1;
1364 LOG_DEBUG("HFM CLK divisor was already set to correct value (0x%02X).",i
[0]&0x7f);
1367 retval
= core_move_value_at_r2(target
,HFM_CLK_DEFAULT
); // write HFM_CLKD
1368 err_check_propagate(retval
);
1369 retval
= core_move_at_r2_to_y0(target
); // verify HFM_CLKD
1370 err_check_propagate(retval
);
1371 retval
= core_move_y0_at_r0(target
);
1372 err_check_propagate(retval
);
1373 retval
= core_rx_upper_data(target
,i
);
1374 err_check_propagate(retval
);
1375 if (i
[0]!=(0x80|(HFM_CLK_DEFAULT
&0x7f))) {
1376 retval
= ERROR_TARGET_FAILURE
;
1377 err_check(retval
, DSP5680XX_ERROR_FM_SET_CLK
, "Unable to set HFM CLK divisor.");
1379 if(hfm_at_wrong_value
)
1380 LOG_DEBUG("HFM CLK divisor set to 0x%02x.",i
[0]&0x7f);
1385 * Executes the FM calculate signature command. The FM will calculate over the data from @address to @address + @words -1. The result is written to a register, then read out by this function and returned in @signature. The value @signature may be compared to the the one returned by perl_crc to verify the flash was written correctly.
1388 * @param address Start of flash array where the signature should be calculated.
1389 * @param words Number of words over which the signature should be calculated.
1390 * @param signature Value calculated by the FM.
1394 static int dsp5680xx_f_signature(struct target
* target
, uint32_t address
, uint32_t words
, uint16_t * signature
){
1397 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1398 retval
= eonce_enter_debug_mode_without_reset(target
,NULL
);
1399 err_check_propagate(retval
);
1401 retval
= dsp5680xx_f_execute_command(target
,HFM_CALCULATE_DATA_SIGNATURE
,address
,words
,&hfm_ustat
,1);
1402 err_check_propagate(retval
);
1403 retval
= dsp5680xx_read_16_single(target
, HFM_BASE_ADDR
|HFM_DATA
, (uint8_t *)signature
, 0);
1407 int dsp5680xx_f_erase_check(struct target
* target
, uint8_t * erased
,uint32_t sector
){
1410 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1411 retval
= dsp5680xx_halt(target
);
1412 err_check_propagate(retval
);
1414 retval
= set_fm_ck_div(target
);
1415 err_check_propagate(retval
);
1416 // Check if chip is already erased.
1417 retval
= dsp5680xx_f_execute_command(target
,HFM_ERASE_VERIFY
,HFM_FLASH_BASE_ADDR
+sector
*HFM_SECTOR_SIZE
/2,0,&hfm_ustat
,1); // blank check
1418 err_check_propagate(retval
);
1420 *erased
= (uint8_t)(hfm_ustat
&HFM_USTAT_MASK_BLANK
);
1425 * Executes the FM page erase command.
1428 * @param sector Page to erase.
1429 * @param hfm_ustat FM module status register.
1433 static int erase_sector(struct target
* target
, int sector
, uint16_t * hfm_ustat
){
1435 retval
= dsp5680xx_f_execute_command(target
,HFM_PAGE_ERASE
,HFM_FLASH_BASE_ADDR
+sector
*HFM_SECTOR_SIZE
/2,0,hfm_ustat
,1);
1436 err_check_propagate(retval
);
1441 * Executes the FM mass erase command. Erases the flash array completely.
1444 * @param hfm_ustat FM module status register.
1448 static int mass_erase(struct target
* target
, uint16_t * hfm_ustat
){
1450 retval
= dsp5680xx_f_execute_command(target
,HFM_MASS_ERASE
,0,0,hfm_ustat
,1);
1454 int dsp5680xx_f_erase(struct target
* target
, int first
, int last
){
1456 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1457 retval
= dsp5680xx_halt(target
);
1458 err_check_propagate(retval
);
1460 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1462 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1463 retval
= dsp5680xx_f_SIM_reset(target
);
1464 err_check_propagate(retval
);
1465 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1467 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1468 retval
= set_fm_ck_div(target
);
1469 err_check_propagate(retval
);
1472 int do_mass_erase
= ((!(first
|last
)) || ((first
==0)&&(last
== (HFM_SECTOR_COUNT
-1))));
1475 retval
= mass_erase(target
,&hfm_ustat
);
1476 err_check_propagate(retval
);
1478 for(int i
= first
;i
<=last
;i
++){
1479 retval
= erase_sector(target
,i
,&hfm_ustat
);
1480 err_check_propagate(retval
);
1487 * Algorithm for programming normal p: flash
1488 * Follow state machine from "56F801x Peripheral Reference Manual"@163.
1489 * Registers to set up before calling:
1490 * r0: TX/RX high address.
1491 * r2: FM module base address.
1492 * r3: Destination address in flash.
1494 * hfm_wait: // wait for buffer empty
1495 * brclr #0x80,x:(r2+0x13),hfm_wait
1496 * rx_check: // wait for input buffer full
1497 * brclr #0x01,x:(r0-2),rx_check
1498 * move.w x:(r0),y0 // read from Rx buffer
1500 * move.w #0x20,x:(r2+0x14) // write PGM command
1501 * move.w #0x80,x:(r2+0x13) // start the command
1502 * move.w X:(R2+0x13),A // Read USTAT register
1503 * brclr #0x20,A,accerr_check // protection violation check
1504 * bfset #0x20,X:(R2+0x13) // clear pviol
1507 * brclr #0x10,A,hfm_wait // access error check
1508 * bfset #0x10,X:(R2+0x13) // clear accerr
1509 * bra hfm_wait // loop
1510 *0x00000000 0x8A460013807D brclr #0x80,X:(R2+0x13),*+0
1511 *0x00000003 0xE700 nop
1512 *0x00000004 0xE700 nop
1513 *0x00000005 0x8A44FFFE017B brclr #1,X:(R0-2),*-2
1514 *0x00000008 0xE700 nop
1515 *0x00000009 0xF514 move.w X:(R0),Y0
1516 *0x0000000A 0x8563 move.w Y0,P:(R3)+
1517 *0x0000000B 0x864600200014 move.w #32,X:(R2+0x14)
1518 *0x0000000E 0x864600800013 move.w #128,X:(R2+0x13)
1519 *0x00000011 0xF0420013 move.w X:(R2+0x13),A
1520 *0x00000013 0x8B402004 brclr #0x20,A,*+6
1521 *0x00000015 0x824600130020 bfset #0x20,X:(R2+0x13)
1522 *0x00000018 0xA967 bra *-24
1523 *0x00000019 0x8B401065 brclr #0x10,A,*-25
1524 *0x0000001B 0x824600130010 bfset #0x10,X:(R2+0x13)
1525 *0x0000001E 0xA961 bra *-30
1528 const uint16_t pgm_write_pflash
[] = {0x8A46, 0x0013, 0x807D, 0xE700,\
1529 0xE700, 0x8A44, 0xFFFE, 0x017B,\
1530 0xE700, 0xF514, 0x8563, 0x8646,\
1531 0x0020, 0x0014, 0x8646, 0x0080,\
1532 0x0013, 0xF042, 0x0013, 0x8B40,\
1533 0x2004, 0x8246, 0x0013, 0x0020,\
1534 0xA967, 0x8B40, 0x1065, 0x8246,\
1535 0x0013, 0x0010, 0xA961};
1536 const uint32_t pgm_write_pflash_length
= 31;
1538 int dsp5680xx_f_wr(struct target
* target
, uint8_t *buffer
, uint32_t address
, uint32_t count
, int is_flash_lock
){
1539 int retval
= ERROR_OK
;
1540 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1541 retval
= eonce_enter_debug_mode(target
,NULL
);
1542 err_check_propagate(retval
);
1544 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1545 // Download the pgm that flashes.
1546 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1547 uint32_t my_favourite_ram_address
= 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
1549 retval
= dsp5680xx_write(target
, my_favourite_ram_address
, 1, pgm_write_pflash_length
*2,(uint8_t *) pgm_write_pflash
);
1550 err_check_propagate(retval
);
1551 retval
= dsp5680xx_execute_queue();
1552 err_check_propagate(retval
);
1554 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1556 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1557 retval
= set_fm_ck_div(target
);
1558 err_check_propagate(retval
);
1559 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1560 // Setup registers needed by pgm_write_pflash
1561 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1563 dsp5680xx_context
.flush
= 0;
1565 retval
= core_move_long_to_r3(target
,address
); // Destination address to r3
1566 err_check_propagate(retval
);
1567 core_load_TX_RX_high_addr_to_r0(target
); // TX/RX reg address to r0
1568 err_check_propagate(retval
);
1569 retval
= core_move_long_to_r2(target
,HFM_BASE_ADDR
);// FM base address to r2
1570 err_check_propagate(retval
);
1571 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1572 // Run flashing program.
1573 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1574 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_CNFG
); // write to HFM_CNFG (lock=0, select bank)
1575 err_check_propagate(retval
);
1576 retval
= core_move_value_at_r2_disp(target
,0x04,HFM_USTAT
);// write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
1577 err_check_propagate(retval
);
1578 retval
= core_move_value_at_r2_disp(target
,0x10,HFM_USTAT
);// clear only one bit at a time
1579 err_check_propagate(retval
);
1580 retval
= core_move_value_at_r2_disp(target
,0x20,HFM_USTAT
);
1581 err_check_propagate(retval
);
1582 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_PROT
);// write to HMF_PROT, clear protection
1583 err_check_propagate(retval
);
1584 retval
= core_move_value_at_r2_disp(target
,0x00,HFM_PROTB
);// write to HMF_PROTB, clear protection
1585 err_check_propagate(retval
);
1587 //TODO implement handling of odd number of words.
1588 retval
= ERROR_FAIL
;
1589 const char *msg
= "Cannot handle odd number of words.";
1590 err_check(retval
, DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT
, msg
);
1593 dsp5680xx_context
.flush
= 1;
1594 retval
= dsp5680xx_execute_queue();
1595 err_check_propagate(retval
);
1597 uint32_t drscan_data
;
1598 uint16_t tmp
= (buffer
[0]|(buffer
[1]<<8));
1599 retval
= core_tx_upper_data(target
,tmp
,&drscan_data
);
1600 err_check_propagate(retval
);
1602 retval
= dsp5680xx_resume(target
,0,my_favourite_ram_address
,0,0);
1603 err_check_propagate(retval
);
1605 int counter
= FLUSH_COUNT_FLASH
;
1606 dsp5680xx_context
.flush
= 0;
1608 for(i
=1; (i
<count
/2)&&(i
<HFM_SIZE_WORDS
); i
++){
1610 dsp5680xx_context
.flush
= 1;
1611 counter
= FLUSH_COUNT_FLASH
;
1613 tmp
= (buffer
[2*i
]|(buffer
[2*i
+1]<<8));
1614 retval
= core_tx_upper_data(target
,tmp
,&drscan_data
);
1615 if(retval
!=ERROR_OK
){
1616 dsp5680xx_context
.flush
= 1;
1617 err_check_propagate(retval
);
1619 dsp5680xx_context
.flush
= 0;
1621 dsp5680xx_context
.flush
= 1;
1623 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1624 // Verify flash (skip when exec lock sequence)
1625 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1628 retval
= dsp5680xx_f_signature(target
,address
,i
,&signature
);
1629 err_check_propagate(retval
);
1630 pc_crc
= perl_crc(buffer
,i
);
1631 if(pc_crc
!= signature
){
1632 retval
= ERROR_FAIL
;
1633 const char *msg
= "Flashed data failed CRC check, flash again!";
1634 err_check(retval
, DSP5680XX_ERROR_FLASHING_CRC
, msg
);
1640 int dsp5680xx_f_unlock(struct target
* target
){
1641 int retval
= ERROR_OK
;
1642 uint16_t eonce_status
;
1647 struct jtag_tap
* tap_chp
;
1648 struct jtag_tap
* tap_cpu
;
1649 tap_chp
= jtag_tap_by_string("dsp568013.chp");
1650 if(tap_chp
== NULL
){
1651 retval
= ERROR_FAIL
;
1652 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER
, "Failed to get master tap.");
1654 tap_cpu
= jtag_tap_by_string("dsp568013.cpu");
1655 if(tap_cpu
== NULL
){
1656 retval
= ERROR_FAIL
;
1657 err_check(retval
, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE
, "Failed to get master tap.");
1660 retval
= eonce_enter_debug_mode(target
,&eonce_status
);
1661 if(retval
== ERROR_OK
){
1662 LOG_WARNING("Memory was not locked.");
1665 jtag_add_reset(0,1);
1666 jtag_add_sleep(TIME_DIV_FREESCALE
*200*1000);
1668 retval
= reset_jtag();
1669 err_check(retval
, DSP5680XX_ERROR_JTAG_RESET
, "Failed to reset JTAG state machine");
1670 jtag_add_sleep(150);
1673 tap_chp
->enabled
= true;
1674 retval
= switch_tap(target
,tap_chp
,tap_cpu
);
1675 err_check_propagate(retval
);
1677 instr
= JTAG_INSTR_DEBUG_REQUEST
;
1678 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
1679 err_check_propagate(retval
);
1680 jtag_add_sleep(TIME_DIV_FREESCALE
*100*1000);
1681 jtag_add_reset(0,0);
1682 jtag_add_sleep(TIME_DIV_FREESCALE
*300*1000);
1684 // Enable master tap
1685 tap_chp
->enabled
= false;
1686 retval
= switch_tap(target
,tap_chp
,tap_cpu
);
1687 err_check_propagate(retval
);
1689 // Execute mass erase to unlock
1690 instr
= MASTER_TAP_CMD_FLASH_ERASE
;
1691 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_MASTER_TAP_IRLEN
);
1692 err_check_propagate(retval
);
1694 instr
= HFM_CLK_DEFAULT
;
1695 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,16);
1696 err_check_propagate(retval
);
1698 jtag_add_sleep(TIME_DIV_FREESCALE
*150*1000);
1699 jtag_add_reset(0,1);
1700 jtag_add_sleep(TIME_DIV_FREESCALE
*200*1000);
1702 retval
= reset_jtag();
1703 err_check(retval
, DSP5680XX_ERROR_JTAG_RESET
, "Failed to reset JTAG state machine");
1704 jtag_add_sleep(150);
1707 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,32);
1708 err_check_propagate(retval
);
1712 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_MASTER_TAP_IRLEN
);
1713 err_check_propagate(retval
);
1715 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & ir_out
,4);
1716 err_check_propagate(retval
);
1718 tap_cpu
->enabled
= true;
1719 tap_chp
->enabled
= false;
1721 instr
= JTAG_INSTR_ENABLE_ONCE
;
1722 //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
1723 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
1724 err_check_propagate(retval
);
1725 instr
= JTAG_INSTR_DEBUG_REQUEST
;
1726 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
1727 err_check_propagate(retval
);
1729 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,8);
1730 err_check_propagate(retval
);
1732 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr_16
,(uint8_t *) & read_16
,8);
1733 err_check_propagate(retval
);
1734 jtag_add_sleep(TIME_DIV_FREESCALE
*100*1000);
1735 jtag_add_reset(0,0);
1736 jtag_add_sleep(TIME_DIV_FREESCALE
*300*1000);
1740 int dsp5680xx_f_lock(struct target
* target
){
1742 uint16_t lock_word
[] = {HFM_LOCK_FLASH
};
1743 retval
= dsp5680xx_f_wr(target
,(uint8_t *)(lock_word
),HFM_LOCK_ADDR_L
,2,1);
1744 err_check_propagate(retval
);
1746 jtag_add_reset(0,1);
1747 jtag_add_sleep(TIME_DIV_FREESCALE
*200*1000);
1749 retval
= reset_jtag();
1750 err_check(retval
, DSP5680XX_ERROR_JTAG_RESET
, "Failed to reset JTAG state machine");
1751 jtag_add_sleep(TIME_DIV_FREESCALE
*100*1000);
1752 jtag_add_reset(0,0);
1753 jtag_add_sleep(TIME_DIV_FREESCALE
*300*1000);
1758 static int dsp5680xx_step(struct target
* target
,int current
, uint32_t address
, int handle_breakpoints
){
1759 err_check(ERROR_FAIL
, DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP
, "Not implemented yet.");
1762 /** Holds methods for dsp5680xx targets. */
1763 struct target_type dsp5680xx_target
= {
1764 .name
= "dsp5680xx",
1766 .poll
= dsp5680xx_poll
,
1767 .arch_state
= dsp5680xx_arch_state
,
1769 .target_request_data
= NULL
,
1771 .halt
= dsp5680xx_halt
,
1772 .resume
= dsp5680xx_resume
,
1773 .step
= dsp5680xx_step
,
1775 .write_buffer
= dsp5680xx_write_buffer
,
1776 .read_buffer
= dsp5680xx_read_buffer
,
1778 .assert_reset
= dsp5680xx_assert_reset
,
1779 .deassert_reset
= dsp5680xx_deassert_reset
,
1780 .soft_reset_halt
= dsp5680xx_soft_reset_halt
,
1782 .read_memory
= dsp5680xx_read
,
1783 .write_memory
= dsp5680xx_write
,
1784 .bulk_write_memory
= dsp5680xx_bulk_write_memory
,
1786 .checksum_memory
= dsp5680xx_checksum_memory
,
1788 .target_create
= dsp5680xx_target_create
,
1789 .init_target
= dsp5680xx_init_target
,