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breakpoint_t -> struct breakpoint
[openocd/cmsis-dap.git] / src / target / cortex_m3.c
blob041f8061968f71c09b2ddcf4bb436bb105fd0ef1
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "cortex_m3.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38
39
40 /* NOTE: most of this should work fine for the Cortex-M1 and
41 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
42 */
43
44 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
45
46
47 /* forward declarations */
48 static int cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
49 static int cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
50 static void cortex_m3_enable_watchpoints(struct target_s *target);
51 static int cortex_m3_store_core_reg_u32(target_t *target,
52 enum armv7m_regtype type, uint32_t num, uint32_t value);
53
54 #ifdef ARMV7_GDB_HACKS
55 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
56 extern reg_t armv7m_gdb_dummy_cpsr_reg;
57 #endif
58
59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
60 uint32_t *value, int regnum)
61 {
62 int retval;
63 uint32_t dcrdr;
64
65 /* because the DCB_DCRDR is used for the emulated dcc channel
66 * we have to save/restore the DCB_DCRDR when used */
67
68 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
69
70 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
71
72 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
73 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
74 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
75
76 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
77 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
78 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
79
80 retval = swjdp_transaction_endcheck(swjdp);
81
82 /* restore DCB_DCRDR - this needs to be in a seperate
83 * transaction otherwise the emulated DCC channel breaks */
84 if (retval == ERROR_OK)
85 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
86
87 return retval;
88 }
89
90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
91 uint32_t value, int regnum)
92 {
93 int retval;
94 uint32_t dcrdr;
95
96 /* because the DCB_DCRDR is used for the emulated dcc channel
97 * we have to save/restore the DCB_DCRDR when used */
98
99 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
100
101 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
102
103 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
104 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
106
107 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
108 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
109 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
110
111 retval = swjdp_transaction_endcheck(swjdp);
112
113 /* restore DCB_DCRDR - this needs to be in a seperate
114 * transaction otherwise the emulated DCC channel breaks */
115 if (retval == ERROR_OK)
116 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
117
118 return retval;
119 }
120
121 static int cortex_m3_write_debug_halt_mask(target_t *target,
122 uint32_t mask_on, uint32_t mask_off)
123 {
124 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
125 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
126
127 /* mask off status bits */
128 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
129 /* create new register mask */
130 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
131
132 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
133 }
134
135 static int cortex_m3_clear_halt(target_t *target)
136 {
137 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
138 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
139
140 /* clear step if any */
141 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
142
143 /* Read Debug Fault Status Register */
144 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
148
149 return ERROR_OK;
150 }
151
152 static int cortex_m3_single_step_core(target_t *target)
153 {
154 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
155 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
156 uint32_t dhcsr_save;
157
158 /* backup dhcsr reg */
159 dhcsr_save = cortex_m3->dcb_dhcsr;
160
161 /* mask interrupts if not done already */
162 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
163 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
164 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
165 LOG_DEBUG(" ");
166
167 /* restore dhcsr reg */
168 cortex_m3->dcb_dhcsr = dhcsr_save;
169 cortex_m3_clear_halt(target);
170
171 return ERROR_OK;
172 }
173
174 static int cortex_m3_endreset_event(target_t *target)
175 {
176 int i;
177 uint32_t dcb_demcr;
178 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
179 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
180 cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
181 cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
182
183 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
184 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
185
186 /* this regsiter is used for emulated dcc channel */
187 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
188
189 /* Enable debug requests */
190 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
191 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
192 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
193
194 /* clear any interrupt masking */
195 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
196
197 /* Enable trace and dwt */
198 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
199 /* Monitor bus faults */
200 mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
201
202 /* Enable FPB */
203 target_write_u32(target, FP_CTRL, 3);
204 cortex_m3->fpb_enabled = 1;
205
206 /* Restore FPB registers */
207 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
208 {
209 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
210 }
211
212 /* Restore DWT registers */
213 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
214 {
215 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
216 dwt_list[i].comp);
217 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
218 dwt_list[i].mask);
219 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
220 dwt_list[i].function);
221 }
222 swjdp_transaction_endcheck(swjdp);
223
224 armv7m_invalidate_core_regs(target);
225
226 /* make sure we have latest dhcsr flags */
227 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
228
229 return ERROR_OK;
230 }
231
232 static int cortex_m3_examine_debug_reason(target_t *target)
233 {
234 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
235
236 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
237 /* only check the debug reason if we don't know it already */
238
239 if ((target->debug_reason != DBG_REASON_DBGRQ)
240 && (target->debug_reason != DBG_REASON_SINGLESTEP))
241 {
242 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
243 {
244 target->debug_reason = DBG_REASON_BREAKPOINT;
245 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
246 target->debug_reason = DBG_REASON_WPTANDBKPT;
247 }
248 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
249 target->debug_reason = DBG_REASON_WATCHPOINT;
250 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
251 target->debug_reason = DBG_REASON_BREAKPOINT;
252 else /* EXTERNAL, HALTED */
253 target->debug_reason = DBG_REASON_UNDEFINED;
254 }
255
256 return ERROR_OK;
257 }
258
259 static int cortex_m3_examine_exception_reason(target_t *target)
260 {
261 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
262 struct armv7m_common *armv7m = target_to_armv7m(target);
263 struct swjdp_common *swjdp = &armv7m->swjdp_info;
264
265 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
266 switch (armv7m->exception_number)
267 {
268 case 2: /* NMI */
269 break;
270 case 3: /* Hard Fault */
271 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
272 if (except_sr & 0x40000000)
273 {
274 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
275 }
276 break;
277 case 4: /* Memory Management */
278 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
279 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
280 break;
281 case 5: /* Bus Fault */
282 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
283 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
284 break;
285 case 6: /* Usage Fault */
286 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
287 break;
288 case 11: /* SVCall */
289 break;
290 case 12: /* Debug Monitor */
291 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
292 break;
293 case 14: /* PendSV */
294 break;
295 case 15: /* SysTick */
296 break;
297 default:
298 except_sr = 0;
299 break;
300 }
301 swjdp_transaction_endcheck(swjdp);
302 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
303 shcsr, except_sr, cfsr, except_ar);
304 return ERROR_OK;
305 }
306
307 static int cortex_m3_debug_entry(target_t *target)
308 {
309 int i;
310 uint32_t xPSR;
311 int retval;
312 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
313 struct armv7m_common *armv7m = &cortex_m3->armv7m;
314 struct swjdp_common *swjdp = &armv7m->swjdp_info;
315
316 LOG_DEBUG(" ");
317
318 cortex_m3_clear_halt(target);
319 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
320
321 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
322 return retval;
323
324 /* Examine target state and mode */
325 /* First load register acessible through core debug port*/
326 int num_regs = armv7m->core_cache->num_regs;
327
328 for (i = 0; i < num_regs; i++)
329 {
330 if (!armv7m->core_cache->reg_list[i].valid)
331 armv7m->read_core_reg(target, i);
332 }
333
334 xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
335
336 #ifdef ARMV7_GDB_HACKS
337 /* copy real xpsr reg for gdb, setting thumb bit */
338 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
339 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
340 armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
341 armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
342 #endif
343
344 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
345 if (xPSR & 0xf00)
346 {
347 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
348 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
349 }
350
351 /* Are we in an exception handler */
352 if (xPSR & 0x1FF)
353 {
354 armv7m->core_mode = ARMV7M_MODE_HANDLER;
355 armv7m->exception_number = (xPSR & 0x1FF);
356 }
357 else
358 {
359 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
360 armv7m->exception_number = 0;
361 }
362
363 if (armv7m->exception_number)
364 {
365 cortex_m3_examine_exception_reason(target);
366 }
367
368 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
369 armv7m_mode_strings[armv7m->core_mode],
370 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
371 target_state_name(target));
372
373 if (armv7m->post_debug_entry)
374 armv7m->post_debug_entry(target);
375
376 return ERROR_OK;
377 }
378
379 static int cortex_m3_poll(target_t *target)
380 {
381 int retval;
382 enum target_state prev_target_state = target->state;
383 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
384 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
385
386 /* Read from Debug Halting Control and Status Register */
387 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
388 if (retval != ERROR_OK)
389 {
390 target->state = TARGET_UNKNOWN;
391 return retval;
392 }
393
394 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
395 {
396 /* check if still in reset */
397 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
398
399 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
400 {
401 target->state = TARGET_RESET;
402 return ERROR_OK;
403 }
404 }
405
406 if (target->state == TARGET_RESET)
407 {
408 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
409 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
410 cortex_m3_endreset_event(target);
411 target->state = TARGET_RUNNING;
412 prev_target_state = TARGET_RUNNING;
413 }
414
415 if (cortex_m3->dcb_dhcsr & S_HALT)
416 {
417 target->state = TARGET_HALTED;
418
419 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
420 {
421 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
422 return retval;
423
424 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
425 }
426 if (prev_target_state == TARGET_DEBUG_RUNNING)
427 {
428 LOG_DEBUG(" ");
429 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
430 return retval;
431
432 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
433 }
434 }
435
436 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
437 * How best to model low power modes?
438 */
439
440 if (target->state == TARGET_UNKNOWN)
441 {
442 /* check if processor is retiring instructions */
443 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
444 {
445 target->state = TARGET_RUNNING;
446 return ERROR_OK;
447 }
448 }
449
450 return ERROR_OK;
451 }
452
453 static int cortex_m3_halt(target_t *target)
454 {
455 LOG_DEBUG("target->state: %s",
456 target_state_name(target));
457
458 if (target->state == TARGET_HALTED)
459 {
460 LOG_DEBUG("target was already halted");
461 return ERROR_OK;
462 }
463
464 if (target->state == TARGET_UNKNOWN)
465 {
466 LOG_WARNING("target was in unknown state when halt was requested");
467 }
468
469 if (target->state == TARGET_RESET)
470 {
471 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
472 {
473 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
474 return ERROR_TARGET_FAILURE;
475 }
476 else
477 {
478 /* we came here in a reset_halt or reset_init sequence
479 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
480 */
481 target->debug_reason = DBG_REASON_DBGRQ;
482
483 return ERROR_OK;
484 }
485 }
486
487 /* Write to Debug Halting Control and Status Register */
488 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
489
490 target->debug_reason = DBG_REASON_DBGRQ;
491
492 return ERROR_OK;
493 }
494
495 static int cortex_m3_soft_reset_halt(struct target_s *target)
496 {
497 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
498 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
499 uint32_t dcb_dhcsr = 0;
500 int retval, timeout = 0;
501
502 /* Enter debug state on reset, cf. end_reset_event() */
503 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
504
505 /* Request a reset */
506 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
507 target->state = TARGET_RESET;
508
509 /* registers are now invalid */
510 armv7m_invalidate_core_regs(target);
511
512 while (timeout < 100)
513 {
514 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
515 if (retval == ERROR_OK)
516 {
517 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
518 if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
519 {
520 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
521 cortex_m3_poll(target);
522 return ERROR_OK;
523 }
524 else
525 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
526 }
527 timeout++;
528 alive_sleep(1);
529 }
530
531 return ERROR_OK;
532 }
533
534 static void cortex_m3_enable_breakpoints(struct target_s *target)
535 {
536 struct breakpoint *breakpoint = target->breakpoints;
537
538 /* set any pending breakpoints */
539 while (breakpoint)
540 {
541 if (breakpoint->set == 0)
542 cortex_m3_set_breakpoint(target, breakpoint);
543 breakpoint = breakpoint->next;
544 }
545 }
546
547 static int cortex_m3_resume(struct target_s *target, int current,
548 uint32_t address, int handle_breakpoints, int debug_execution)
549 {
550 struct armv7m_common *armv7m = target_to_armv7m(target);
551 struct breakpoint *breakpoint = NULL;
552 uint32_t resume_pc;
553
554 if (target->state != TARGET_HALTED)
555 {
556 LOG_WARNING("target not halted");
557 return ERROR_TARGET_NOT_HALTED;
558 }
559
560 if (!debug_execution)
561 {
562 target_free_all_working_areas(target);
563 cortex_m3_enable_breakpoints(target);
564 cortex_m3_enable_watchpoints(target);
565 }
566
567 if (debug_execution)
568 {
569 /* Disable interrupts */
570 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
571 * This is probably the same issue as Cortex-M3 Errata 377493:
572 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
573 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
574 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
575 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
576
577 /* Make sure we are in Thumb mode */
578 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
579 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
580 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
581 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
582 }
583
584 /* current = 1: continue on current pc, otherwise continue at <address> */
585 if (!current)
586 {
587 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
588 armv7m->core_cache->reg_list[15].dirty = 1;
589 armv7m->core_cache->reg_list[15].valid = 1;
590 }
591
592 resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
593
594 armv7m_restore_context(target);
595
596 /* the front-end may request us not to handle breakpoints */
597 if (handle_breakpoints)
598 {
599 /* Single step past breakpoint at current address */
600 if ((breakpoint = breakpoint_find(target, resume_pc)))
601 {
602 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
603 breakpoint->address,
604 breakpoint->unique_id);
605 cortex_m3_unset_breakpoint(target, breakpoint);
606 cortex_m3_single_step_core(target);
607 cortex_m3_set_breakpoint(target, breakpoint);
608 }
609 }
610
611 /* Restart core */
612 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
613
614 target->debug_reason = DBG_REASON_NOTHALTED;
615
616 /* registers are now invalid */
617 armv7m_invalidate_core_regs(target);
618 if (!debug_execution)
619 {
620 target->state = TARGET_RUNNING;
621 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
622 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
623 }
624 else
625 {
626 target->state = TARGET_DEBUG_RUNNING;
627 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
628 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
629 }
630
631 return ERROR_OK;
632 }
633
634 /* int irqstepcount = 0; */
635 static int cortex_m3_step(struct target_s *target, int current,
636 uint32_t address, int handle_breakpoints)
637 {
638 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
639 struct armv7m_common *armv7m = &cortex_m3->armv7m;
640 struct swjdp_common *swjdp = &armv7m->swjdp_info;
641 struct breakpoint *breakpoint = NULL;
642
643 if (target->state != TARGET_HALTED)
644 {
645 LOG_WARNING("target not halted");
646 return ERROR_TARGET_NOT_HALTED;
647 }
648
649 /* current = 1: continue on current pc, otherwise continue at <address> */
650 if (!current)
651 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
652 0, 32, address);
653
654 /* the front-end may request us not to handle breakpoints */
655 if (handle_breakpoints) {
656 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
657 ->core_cache->reg_list[15].value, 0, 32));
658 if (breakpoint)
659 cortex_m3_unset_breakpoint(target, breakpoint);
660 }
661
662 target->debug_reason = DBG_REASON_SINGLESTEP;
663
664 armv7m_restore_context(target);
665
666 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
667
668 /* set step and clear halt */
669 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
670 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
671
672 /* registers are now invalid */
673 armv7m_invalidate_core_regs(target);
674
675 if (breakpoint)
676 cortex_m3_set_breakpoint(target, breakpoint);
677
678 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
679
680 cortex_m3_debug_entry(target);
681 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
682
683 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
684 return ERROR_OK;
685 }
686
687 static int cortex_m3_assert_reset(target_t *target)
688 {
689 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
690 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
691 int assert_srst = 1;
692
693 LOG_DEBUG("target->state: %s",
694 target_state_name(target));
695
696 enum reset_types jtag_reset_config = jtag_get_reset_config();
697
698 /*
699 * We can reset Cortex-M3 targets using just the NVIC without
700 * requiring SRST, getting a SoC reset (or a core-only reset)
701 * instead of a system reset.
702 */
703 if (!(jtag_reset_config & RESET_HAS_SRST))
704 assert_srst = 0;
705
706 /* Enable debug requests */
707 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
708 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
709 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
710
711 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
712
713 if (!target->reset_halt)
714 {
715 /* Set/Clear C_MASKINTS in a separate operation */
716 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
717 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
718
719 /* clear any debug flags before resuming */
720 cortex_m3_clear_halt(target);
721
722 /* clear C_HALT in dhcsr reg */
723 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
724
725 /* Enter debug state on reset, cf. end_reset_event() */
726 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
727 }
728 else
729 {
730 /* Enter debug state on reset, cf. end_reset_event() */
731 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
732 }
733
734 /*
735 * When nRST is asserted on most Stellaris devices, it clears some of
736 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
737 * and OpenOCD depends on those TRMs. So we won't use SRST on those
738 * chips. (Only power-on reset should affect debug state, beyond a
739 * few specified bits; not the chip's nRST input, wired to SRST.)
740 *
741 * REVISIT current errata specs don't seem to cover this issue.
742 * Do we have more details than this email?
743 * https://lists.berlios.de/pipermail
744 * /openocd-development/2008-August/003065.html
745 */
746 if (strcmp(target->variant, "lm3s") == 0)
747 {
748 /* Check for silicon revisions with the issue. */
749 uint32_t did0;
750
751 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
752 {
753 switch ((did0 >> 16) & 0xff)
754 {
755 case 0:
756 /* all Sandstorm suffer issue */
757 assert_srst = 0;
758 break;
759
760 case 1:
761 case 3:
762 /* Fury and DustDevil rev A have
763 * this nRST problem. It should
764 * be fixed in rev B silicon.
765 */
766 if (((did0 >> 8) & 0xff) == 0)
767 assert_srst = 0;
768 break;
769 case 4:
770 /* Tempest should be fine. */
771 break;
772 }
773 }
774 }
775
776 if (assert_srst)
777 {
778 /* default to asserting srst */
779 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
780 {
781 jtag_add_reset(1, 1);
782 }
783 else
784 {
785 jtag_add_reset(0, 1);
786 }
787 }
788 else
789 {
790 /* Use a standard Cortex-M3 software reset mechanism.
791 * SYSRESETREQ will reset SoC peripherals outside the
792 * core, like watchdog timers, if the SoC wires it up
793 * correctly. Else VECRESET can reset just the core.
794 */
795 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
796 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
797 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
798
799 {
800 /* I do not know why this is necessary, but it
801 * fixes strange effects (step/resume cause NMI
802 * after reset) on LM3S6918 -- Michael Schwingen
803 */
804 uint32_t tmp;
805 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
806 }
807 }
808
809 target->state = TARGET_RESET;
810 jtag_add_sleep(50000);
811
812 armv7m_invalidate_core_regs(target);
813
814 if (target->reset_halt)
815 {
816 int retval;
817 if ((retval = target_halt(target)) != ERROR_OK)
818 return retval;
819 }
820
821 return ERROR_OK;
822 }
823
824 static int cortex_m3_deassert_reset(target_t *target)
825 {
826 LOG_DEBUG("target->state: %s",
827 target_state_name(target));
828
829 /* deassert reset lines */
830 jtag_add_reset(0, 0);
831
832 return ERROR_OK;
833 }
834
835 static int
836 cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
837 {
838 int retval;
839 int fp_num = 0;
840 uint32_t hilo;
841 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
842 cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list;
843
844 if (breakpoint->set)
845 {
846 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
847 return ERROR_OK;
848 }
849
850 if (cortex_m3->auto_bp_type)
851 {
852 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
853 }
854
855 if (breakpoint->type == BKPT_HARD)
856 {
857 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
858 fp_num++;
859 if (fp_num >= cortex_m3->fp_num_code)
860 {
861 LOG_DEBUG("ERROR Can not find free FP Comparator");
862 LOG_WARNING("ERROR Can not find free FP Comparator");
863 exit(-1);
864 }
865 breakpoint->set = fp_num + 1;
866 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
867 comparator_list[fp_num].used = 1;
868 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
869 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
870 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
871 if (!cortex_m3->fpb_enabled)
872 {
873 LOG_DEBUG("FPB wasn't enabled, do it now");
874 target_write_u32(target, FP_CTRL, 3);
875 }
876 }
877 else if (breakpoint->type == BKPT_SOFT)
878 {
879 uint8_t code[4];
880 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
881 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
882 {
883 return retval;
884 }
885 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
886 {
887 return retval;
888 }
889 breakpoint->set = 0x11; /* Any nice value but 0 */
890 }
891
892 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
893 breakpoint->unique_id,
894 (int)(breakpoint->type),
895 breakpoint->address,
896 breakpoint->length,
897 breakpoint->set);
898
899 return ERROR_OK;
900 }
901
902 static int
903 cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
904 {
905 int retval;
906 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
907 cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
908
909 if (!breakpoint->set)
910 {
911 LOG_WARNING("breakpoint not set");
912 return ERROR_OK;
913 }
914
915 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
916 breakpoint->unique_id,
917 (int)(breakpoint->type),
918 breakpoint->address,
919 breakpoint->length,
920 breakpoint->set);
921
922 if (breakpoint->type == BKPT_HARD)
923 {
924 int fp_num = breakpoint->set - 1;
925 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
926 {
927 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
928 return ERROR_OK;
929 }
930 comparator_list[fp_num].used = 0;
931 comparator_list[fp_num].fpcr_value = 0;
932 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
933 }
934 else
935 {
936 /* restore original instruction (kept in target endianness) */
937 if (breakpoint->length == 4)
938 {
939 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
940 {
941 return retval;
942 }
943 }
944 else
945 {
946 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
947 {
948 return retval;
949 }
950 }
951 }
952 breakpoint->set = 0;
953
954 return ERROR_OK;
955 }
956
957 static int
958 cortex_m3_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
959 {
960 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
961
962 if (cortex_m3->auto_bp_type)
963 {
964 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
965 #ifdef ARMV7_GDB_HACKS
966 if (breakpoint->length != 2) {
967 /* XXX Hack: Replace all breakpoints with length != 2 with
968 * a hardware breakpoint. */
969 breakpoint->type = BKPT_HARD;
970 breakpoint->length = 2;
971 }
972 #endif
973 }
974
975 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
976 {
977 LOG_INFO("flash patch comparator requested outside code memory region");
978 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
979 }
980
981 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
982 {
983 LOG_INFO("soft breakpoint requested in code (flash) memory region");
984 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
985 }
986
987 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
988 {
989 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
990 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
991 }
992
993 if ((breakpoint->length != 2))
994 {
995 LOG_INFO("only breakpoints of two bytes length supported");
996 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
997 }
998
999 if (breakpoint->type == BKPT_HARD)
1000 cortex_m3->fp_code_available--;
1001 cortex_m3_set_breakpoint(target, breakpoint);
1002
1003 return ERROR_OK;
1004 }
1005
1006 static int
1007 cortex_m3_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
1008 {
1009 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1010
1011 /* REVISIT why check? FBP can be updated with core running ... */
1012 if (target->state != TARGET_HALTED)
1013 {
1014 LOG_WARNING("target not halted");
1015 return ERROR_TARGET_NOT_HALTED;
1016 }
1017
1018 if (cortex_m3->auto_bp_type)
1019 {
1020 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1021 }
1022
1023 if (breakpoint->set)
1024 {
1025 cortex_m3_unset_breakpoint(target, breakpoint);
1026 }
1027
1028 if (breakpoint->type == BKPT_HARD)
1029 cortex_m3->fp_code_available++;
1030
1031 return ERROR_OK;
1032 }
1033
1034 static int
1035 cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
1036 {
1037 int dwt_num = 0;
1038 uint32_t mask, temp;
1039 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1040
1041 /* watchpoint params were validated earlier */
1042 mask = 0;
1043 temp = watchpoint->length;
1044 while (temp) {
1045 temp >>= 1;
1046 mask++;
1047 }
1048 mask--;
1049
1050 /* REVISIT Don't fully trust these "not used" records ... users
1051 * may set up breakpoints by hand, e.g. dual-address data value
1052 * watchpoint using comparator #1; comparator #0 matching cycle
1053 * count; send data trace info through ITM and TPIU; etc
1054 */
1055 cortex_m3_dwt_comparator_t *comparator;
1056
1057 for (comparator = cortex_m3->dwt_comparator_list;
1058 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1059 comparator++, dwt_num++)
1060 continue;
1061 if (dwt_num >= cortex_m3->dwt_num_comp)
1062 {
1063 LOG_ERROR("Can not find free DWT Comparator");
1064 return ERROR_FAIL;
1065 }
1066 comparator->used = 1;
1067 watchpoint->set = dwt_num + 1;
1068
1069 comparator->comp = watchpoint->address;
1070 target_write_u32(target, comparator->dwt_comparator_address + 0,
1071 comparator->comp);
1072
1073 comparator->mask = mask;
1074 target_write_u32(target, comparator->dwt_comparator_address + 4,
1075 comparator->mask);
1076
1077 switch (watchpoint->rw) {
1078 case WPT_READ:
1079 comparator->function = 5;
1080 break;
1081 case WPT_WRITE:
1082 comparator->function = 6;
1083 break;
1084 case WPT_ACCESS:
1085 comparator->function = 7;
1086 break;
1087 }
1088 target_write_u32(target, comparator->dwt_comparator_address + 8,
1089 comparator->function);
1090
1091 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1092 watchpoint->unique_id, dwt_num,
1093 (unsigned) comparator->comp,
1094 (unsigned) comparator->mask,
1095 (unsigned) comparator->function);
1096 return ERROR_OK;
1097 }
1098
1099 static int
1100 cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
1101 {
1102 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1103 cortex_m3_dwt_comparator_t *comparator;
1104 int dwt_num;
1105
1106 if (!watchpoint->set)
1107 {
1108 LOG_WARNING("watchpoint (wpid: %d) not set",
1109 watchpoint->unique_id);
1110 return ERROR_OK;
1111 }
1112
1113 dwt_num = watchpoint->set - 1;
1114
1115 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1116 watchpoint->unique_id, dwt_num,
1117 (unsigned) watchpoint->address);
1118
1119 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1120 {
1121 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1122 return ERROR_OK;
1123 }
1124
1125 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1126 comparator->used = 0;
1127 comparator->function = 0;
1128 target_write_u32(target, comparator->dwt_comparator_address + 8,
1129 comparator->function);
1130
1131 watchpoint->set = 0;
1132
1133 return ERROR_OK;
1134 }
1135
1136 static int
1137 cortex_m3_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
1138 {
1139 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1140
1141 /* REVISIT why check? DWT can be updated with core running ... */
1142 if (target->state != TARGET_HALTED)
1143 {
1144 LOG_WARNING("target not halted");
1145 return ERROR_TARGET_NOT_HALTED;
1146 }
1147
1148 if (cortex_m3->dwt_comp_available < 1)
1149 {
1150 LOG_DEBUG("no comparators?");
1151 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1152 }
1153
1154 /* hardware doesn't support data value masking */
1155 if (watchpoint->mask != ~(uint32_t)0) {
1156 LOG_DEBUG("watchpoint value masks not supported");
1157 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1158 }
1159
1160 /* hardware allows address masks of up to 32K */
1161 unsigned mask;
1162
1163 for (mask = 0; mask < 16; mask++) {
1164 if ((1u << mask) == watchpoint->length)
1165 break;
1166 }
1167 if (mask == 16) {
1168 LOG_DEBUG("unsupported watchpoint length");
1169 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1170 }
1171 if (watchpoint->address & ((1 << mask) - 1)) {
1172 LOG_DEBUG("watchpoint address is unaligned");
1173 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1174 }
1175
1176 /* Caller doesn't seem to be able to describe watching for data
1177 * values of zero; that flags "no value".
1178 *
1179 * REVISIT This DWT may well be able to watch for specific data
1180 * values. Requires comparator #1 to set DATAVMATCH and match
1181 * the data, and another comparator (DATAVADDR0) matching addr.
1182 */
1183 if (watchpoint->value) {
1184 LOG_DEBUG("data value watchpoint not YET supported");
1185 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1186 }
1187
1188 cortex_m3->dwt_comp_available--;
1189 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1190
1191 return ERROR_OK;
1192 }
1193
1194 static int
1195 cortex_m3_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
1196 {
1197 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1198
1199 /* REVISIT why check? DWT can be updated with core running ... */
1200 if (target->state != TARGET_HALTED)
1201 {
1202 LOG_WARNING("target not halted");
1203 return ERROR_TARGET_NOT_HALTED;
1204 }
1205
1206 if (watchpoint->set)
1207 {
1208 cortex_m3_unset_watchpoint(target, watchpoint);
1209 }
1210
1211 cortex_m3->dwt_comp_available++;
1212 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1213
1214 return ERROR_OK;
1215 }
1216
1217 static void cortex_m3_enable_watchpoints(struct target_s *target)
1218 {
1219 struct watchpoint *watchpoint = target->watchpoints;
1220
1221 /* set any pending watchpoints */
1222 while (watchpoint)
1223 {
1224 if (watchpoint->set == 0)
1225 cortex_m3_set_watchpoint(target, watchpoint);
1226 watchpoint = watchpoint->next;
1227 }
1228 }
1229
1230 static int cortex_m3_load_core_reg_u32(struct target_s *target,
1231 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1232 {
1233 int retval;
1234 struct armv7m_common *armv7m = target_to_armv7m(target);
1235 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1236
1237 /* NOTE: we "know" here that the register identifiers used
1238 * in the v7m header match the Cortex-M3 Debug Core Register
1239 * Selector values for R0..R15, xPSR, MSP, and PSP.
1240 */
1241 switch (num) {
1242 case 0 ... 18:
1243 /* read a normal core register */
1244 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1245
1246 if (retval != ERROR_OK)
1247 {
1248 LOG_ERROR("JTAG failure %i",retval);
1249 return ERROR_JTAG_DEVICE_ERROR;
1250 }
1251 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1252 break;
1253
1254 case ARMV7M_PRIMASK:
1255 case ARMV7M_BASEPRI:
1256 case ARMV7M_FAULTMASK:
1257 case ARMV7M_CONTROL:
1258 /* Cortex-M3 packages these four registers as bitfields
1259 * in one Debug Core register. So say r0 and r2 docs;
1260 * it was removed from r1 docs, but still works.
1261 */
1262 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1263
1264 switch (num)
1265 {
1266 case ARMV7M_PRIMASK:
1267 *value = buf_get_u32((uint8_t*)value, 0, 1);
1268 break;
1269
1270 case ARMV7M_BASEPRI:
1271 *value = buf_get_u32((uint8_t*)value, 8, 8);
1272 break;
1273
1274 case ARMV7M_FAULTMASK:
1275 *value = buf_get_u32((uint8_t*)value, 16, 1);
1276 break;
1277
1278 case ARMV7M_CONTROL:
1279 *value = buf_get_u32((uint8_t*)value, 24, 2);
1280 break;
1281 }
1282
1283 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1284 break;
1285
1286 default:
1287 return ERROR_INVALID_ARGUMENTS;
1288 }
1289
1290 return ERROR_OK;
1291 }
1292
1293 static int cortex_m3_store_core_reg_u32(struct target_s *target,
1294 enum armv7m_regtype type, uint32_t num, uint32_t value)
1295 {
1296 int retval;
1297 uint32_t reg;
1298 struct armv7m_common *armv7m = target_to_armv7m(target);
1299 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1300
1301 #ifdef ARMV7_GDB_HACKS
1302 /* If the LR register is being modified, make sure it will put us
1303 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1304 * hack to deal with the fact that gdb will sometimes "forge"
1305 * return addresses, and doesn't set the LSB correctly (i.e., when
1306 * printing expressions containing function calls, it sets LR = 0.)
1307 * Valid exception return codes have bit 0 set too.
1308 */
1309 if (num == ARMV7M_R14)
1310 value |= 0x01;
1311 #endif
1312
1313 /* NOTE: we "know" here that the register identifiers used
1314 * in the v7m header match the Cortex-M3 Debug Core Register
1315 * Selector values for R0..R15, xPSR, MSP, and PSP.
1316 */
1317 switch (num) {
1318 case 0 ... 18:
1319 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1320 if (retval != ERROR_OK)
1321 {
1322 LOG_ERROR("JTAG failure %i", retval);
1323 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1324 return ERROR_JTAG_DEVICE_ERROR;
1325 }
1326 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1327 break;
1328
1329 case ARMV7M_PRIMASK:
1330 case ARMV7M_BASEPRI:
1331 case ARMV7M_FAULTMASK:
1332 case ARMV7M_CONTROL:
1333 /* Cortex-M3 packages these four registers as bitfields
1334 * in one Debug Core register. So say r0 and r2 docs;
1335 * it was removed from r1 docs, but still works.
1336 */
1337 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1338
1339 switch (num)
1340 {
1341 case ARMV7M_PRIMASK:
1342 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1343 break;
1344
1345 case ARMV7M_BASEPRI:
1346 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1347 break;
1348
1349 case ARMV7M_FAULTMASK:
1350 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1351 break;
1352
1353 case ARMV7M_CONTROL:
1354 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1355 break;
1356 }
1357
1358 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1359
1360 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1361 break;
1362
1363 default:
1364 return ERROR_INVALID_ARGUMENTS;
1365 }
1366
1367 return ERROR_OK;
1368 }
1369
1370 static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
1371 uint32_t size, uint32_t count, uint8_t *buffer)
1372 {
1373 struct armv7m_common *armv7m = target_to_armv7m(target);
1374 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1375 int retval;
1376
1377 /* sanitize arguments */
1378 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1379 return ERROR_INVALID_ARGUMENTS;
1380
1381 /* cortex_m3 handles unaligned memory access */
1382
1383 switch (size)
1384 {
1385 case 4:
1386 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1387 break;
1388 case 2:
1389 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1390 break;
1391 case 1:
1392 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1393 break;
1394 default:
1395 LOG_ERROR("BUG: we shouldn't get here");
1396 exit(-1);
1397 }
1398
1399 return retval;
1400 }
1401
1402 static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
1403 uint32_t size, uint32_t count, uint8_t *buffer)
1404 {
1405 struct armv7m_common *armv7m = target_to_armv7m(target);
1406 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1407 int retval;
1408
1409 /* sanitize arguments */
1410 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1411 return ERROR_INVALID_ARGUMENTS;
1412
1413 switch (size)
1414 {
1415 case 4:
1416 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1417 break;
1418 case 2:
1419 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1420 break;
1421 case 1:
1422 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1423 break;
1424 default:
1425 LOG_ERROR("BUG: we shouldn't get here");
1426 exit(-1);
1427 }
1428
1429 return retval;
1430 }
1431
1432 static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address,
1433 uint32_t count, uint8_t *buffer)
1434 {
1435 return cortex_m3_write_memory(target, address, 4, count, buffer);
1436 }
1437
1438 static int cortex_m3_init_target(struct command_context_s *cmd_ctx,
1439 struct target_s *target)
1440 {
1441 armv7m_build_reg_cache(target);
1442 return ERROR_OK;
1443 }
1444
1445 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1446 * on r/w if the core is not running, and clear on resume or reset ... or
1447 * at least, in a post_restore_context() method.
1448 */
1449
1450 struct dwt_reg_state {
1451 struct target_s *target;
1452 uint32_t addr;
1453 uint32_t value; /* scratch/cache */
1454 };
1455
1456 static int cortex_m3_dwt_get_reg(struct reg_s *reg)
1457 {
1458 struct dwt_reg_state *state = reg->arch_info;
1459
1460 return target_read_u32(state->target, state->addr, &state->value);
1461 }
1462
1463 static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf)
1464 {
1465 struct dwt_reg_state *state = reg->arch_info;
1466
1467 return target_write_u32(state->target, state->addr,
1468 buf_get_u32(buf, 0, reg->size));
1469 }
1470
1471 struct dwt_reg {
1472 uint32_t addr;
1473 char *name;
1474 unsigned size;
1475 };
1476
1477 static struct dwt_reg dwt_base_regs[] = {
1478 { DWT_CTRL, "dwt_ctrl", 32, },
1479 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1480 /* plus some 8 bit counters, useful for profiling with TPIU */
1481 };
1482
1483 static struct dwt_reg dwt_comp[] = {
1484 #define DWT_COMPARATOR(i) \
1485 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1486 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1487 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1488 DWT_COMPARATOR(0),
1489 DWT_COMPARATOR(1),
1490 DWT_COMPARATOR(2),
1491 DWT_COMPARATOR(3),
1492 #undef DWT_COMPARATOR
1493 };
1494
1495 static int dwt_reg_type = -1;
1496
1497 static void
1498 cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
1499 {
1500 struct dwt_reg_state *state;
1501
1502 state = calloc(1, sizeof *state);
1503 if (!state)
1504 return;
1505 state->addr = d->addr;
1506 state->target = t;
1507
1508 r->name = d->name;
1509 r->size = d->size;
1510 r->value = &state->value;
1511 r->arch_info = state;
1512 r->arch_type = dwt_reg_type;
1513 }
1514
1515 static void
1516 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
1517 {
1518 uint32_t dwtcr;
1519 struct reg_cache *cache;
1520 cortex_m3_dwt_comparator_t *comparator;
1521 int reg, i;
1522
1523 target_read_u32(target, DWT_CTRL, &dwtcr);
1524 if (!dwtcr) {
1525 LOG_DEBUG("no DWT");
1526 return;
1527 }
1528
1529 if (dwt_reg_type < 0)
1530 dwt_reg_type = register_reg_arch_type(cortex_m3_dwt_get_reg,
1531 cortex_m3_dwt_set_reg);
1532
1533 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1534 cm3->dwt_comp_available = cm3->dwt_num_comp;
1535 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1536 sizeof(cortex_m3_dwt_comparator_t));
1537 if (!cm3->dwt_comparator_list) {
1538 fail0:
1539 cm3->dwt_num_comp = 0;
1540 LOG_ERROR("out of mem");
1541 return;
1542 }
1543
1544 cache = calloc(1, sizeof *cache);
1545 if (!cache) {
1546 fail1:
1547 free(cm3->dwt_comparator_list);
1548 goto fail0;
1549 }
1550 cache->name = "cortex-m3 dwt registers";
1551 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1552 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1553 if (!cache->reg_list) {
1554 free(cache);
1555 goto fail1;
1556 }
1557
1558 for (reg = 0; reg < 2; reg++)
1559 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1560 dwt_base_regs + reg);
1561
1562 comparator = cm3->dwt_comparator_list;
1563 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1564 int j;
1565
1566 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1567 for (j = 0; j < 3; j++, reg++)
1568 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1569 dwt_comp + 3 * i + j);
1570 }
1571
1572 *register_get_last_cache_p(&target->reg_cache) = cache;
1573 cm3->dwt_cache = cache;
1574
1575 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1576 dwtcr, cm3->dwt_num_comp,
1577 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1578
1579 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1580 * implement single-address data value watchpoints ... so we
1581 * won't need to check it later, when asked to set one up.
1582 */
1583 }
1584
1585 static int cortex_m3_examine(struct target_s *target)
1586 {
1587 int retval;
1588 uint32_t cpuid, fpcr;
1589 int i;
1590 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1591 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1592
1593 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1594 return retval;
1595
1596 if (!target_was_examined(target))
1597 {
1598 target_set_examined(target);
1599
1600 /* Read from Device Identification Registers */
1601 retval = target_read_u32(target, CPUID, &cpuid);
1602 if (retval != ERROR_OK)
1603 return retval;
1604
1605 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1606 LOG_DEBUG("CORTEX-M3 processor detected");
1607 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1608
1609 /* NOTE: FPB and DWT are both optional. */
1610
1611 /* Setup FPB */
1612 target_read_u32(target, FP_CTRL, &fpcr);
1613 cortex_m3->auto_bp_type = 1;
1614 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1615 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1616 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1617 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
1618 cortex_m3->fpb_enabled = fpcr & 1;
1619 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1620 {
1621 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1622 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1623 }
1624 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1625
1626 /* Setup DWT */
1627 cortex_m3_dwt_setup(cortex_m3, target);
1628 }
1629
1630 return ERROR_OK;
1631 }
1632
1633 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1634 {
1635 uint16_t dcrdr;
1636
1637 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1638 *ctrl = (uint8_t)dcrdr;
1639 *value = (uint8_t)(dcrdr >> 8);
1640
1641 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1642
1643 /* write ack back to software dcc register
1644 * signify we have read data */
1645 if (dcrdr & (1 << 0))
1646 {
1647 dcrdr = 0;
1648 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1649 }
1650
1651 return ERROR_OK;
1652 }
1653
1654 static int cortex_m3_target_request_data(target_t *target,
1655 uint32_t size, uint8_t *buffer)
1656 {
1657 struct armv7m_common *armv7m = target_to_armv7m(target);
1658 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1659 uint8_t data;
1660 uint8_t ctrl;
1661 uint32_t i;
1662
1663 for (i = 0; i < (size * 4); i++)
1664 {
1665 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1666 buffer[i] = data;
1667 }
1668
1669 return ERROR_OK;
1670 }
1671
1672 static int cortex_m3_handle_target_request(void *priv)
1673 {
1674 target_t *target = priv;
1675 if (!target_was_examined(target))
1676 return ERROR_OK;
1677 struct armv7m_common *armv7m = target_to_armv7m(target);
1678 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1679
1680 if (!target->dbg_msg_enabled)
1681 return ERROR_OK;
1682
1683 if (target->state == TARGET_RUNNING)
1684 {
1685 uint8_t data;
1686 uint8_t ctrl;
1687
1688 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1689
1690 /* check if we have data */
1691 if (ctrl & (1 << 0))
1692 {
1693 uint32_t request;
1694
1695 /* we assume target is quick enough */
1696 request = data;
1697 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1698 request |= (data << 8);
1699 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1700 request |= (data << 16);
1701 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1702 request |= (data << 24);
1703 target_request(target, request);
1704 }
1705 }
1706
1707 return ERROR_OK;
1708 }
1709
1710 static int cortex_m3_init_arch_info(target_t *target,
1711 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1712 {
1713 int retval;
1714 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1715
1716 armv7m_init_arch_info(target, armv7m);
1717
1718 /* prepare JTAG information for the new target */
1719 cortex_m3->jtag_info.tap = tap;
1720 cortex_m3->jtag_info.scann_size = 4;
1721
1722 armv7m->swjdp_info.dp_select_value = -1;
1723 armv7m->swjdp_info.ap_csw_value = -1;
1724 armv7m->swjdp_info.ap_tar_value = -1;
1725 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1726 armv7m->swjdp_info.memaccess_tck = 8;
1727 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1728
1729 /* register arch-specific functions */
1730 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1731
1732 armv7m->post_debug_entry = NULL;
1733
1734 armv7m->pre_restore_context = NULL;
1735 armv7m->post_restore_context = NULL;
1736
1737 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1738 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1739
1740 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1741
1742 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1743 {
1744 return retval;
1745 }
1746
1747 return ERROR_OK;
1748 }
1749
1750 static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
1751 {
1752 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1753
1754 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1755 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1756
1757 return ERROR_OK;
1758 }
1759
1760 /*--------------------------------------------------------------------------*/
1761
1762 static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx,
1763 struct cortex_m3_common *cm3)
1764 {
1765 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1766 command_print(cmd_ctx, "target is not a Cortex-M3");
1767 return ERROR_TARGET_INVALID;
1768 }
1769 return ERROR_OK;
1770 }
1771
1772 /*
1773 * Only stuff below this line should need to verify that its target
1774 * is a Cortex-M3. Everything else should have indirected through the
1775 * cortexm3_target structure, which is only used with CM3 targets.
1776 */
1777
1778 /*
1779 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1780 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1781 * that *only* Thumb2 disassembly matters. There are also some small
1782 * additions to Thumb2 that are specific to ARMv7-M.
1783 */
1784 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1785 {
1786 int retval;
1787 target_t *target = get_current_target(cmd_ctx);
1788 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1789 uint32_t address;
1790 unsigned long count = 1;
1791 struct arm_instruction cur_instruction;
1792
1793 retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
1794 if (retval != ERROR_OK)
1795 return retval;
1796
1797 errno = 0;
1798 switch (argc) {
1799 case 2:
1800 COMMAND_PARSE_NUMBER(ulong, args[1], count);
1801 /* FALL THROUGH */
1802 case 1:
1803 COMMAND_PARSE_NUMBER(u32, args[0], address);
1804 break;
1805 default:
1806 command_print(cmd_ctx,
1807 "usage: cortex_m3 disassemble <address> [<count>]");
1808 return ERROR_OK;
1809 }
1810
1811 while (count--) {
1812 retval = thumb2_opcode(target, address, &cur_instruction);
1813 if (retval != ERROR_OK)
1814 return retval;
1815 command_print(cmd_ctx, "%s", cur_instruction.text);
1816 address += cur_instruction.instruction_size;
1817 }
1818
1819 return ERROR_OK;
1820 }
1821
1822 static const struct {
1823 char name[10];
1824 unsigned mask;
1825 } vec_ids[] = {
1826 { "hard_err", VC_HARDERR, },
1827 { "int_err", VC_INTERR, },
1828 { "bus_err", VC_BUSERR, },
1829 { "state_err", VC_STATERR, },
1830 { "chk_err", VC_CHKERR, },
1831 { "nocp_err", VC_NOCPERR, },
1832 { "mm_err", VC_MMERR, },
1833 { "reset", VC_CORERESET, },
1834 };
1835
1836 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1837 {
1838 target_t *target = get_current_target(cmd_ctx);
1839 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1840 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1841 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1842 uint32_t demcr = 0;
1843 int retval;
1844 int i;
1845
1846 retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
1847 if (retval != ERROR_OK)
1848 return retval;
1849
1850 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1851
1852 if (argc > 0) {
1853 unsigned catch = 0;
1854
1855 if (argc == 1) {
1856 if (strcmp(args[0], "all") == 0) {
1857 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1858 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1859 | VC_MMERR | VC_CORERESET;
1860 goto write;
1861 } else if (strcmp(args[0], "none") == 0) {
1862 goto write;
1863 }
1864 }
1865 while (argc-- > 0) {
1866 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1867 if (strcmp(args[argc], vec_ids[i].name) != 0)
1868 continue;
1869 catch |= vec_ids[i].mask;
1870 break;
1871 }
1872 if (i == ARRAY_SIZE(vec_ids)) {
1873 LOG_ERROR("No CM3 vector '%s'", args[argc]);
1874 return ERROR_INVALID_ARGUMENTS;
1875 }
1876 }
1877 write:
1878 demcr &= ~0xffff;
1879 demcr |= catch;
1880
1881 /* write, but don't assume it stuck */
1882 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1883 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1884 }
1885
1886 for (i = 0; i < ARRAY_SIZE(vec_ids); i++)
1887 command_print(cmd_ctx, "%9s: %s", vec_ids[i].name,
1888 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1889
1890 return ERROR_OK;
1891 }
1892
1893 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1894 {
1895 target_t *target = get_current_target(cmd_ctx);
1896 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1897 int retval;
1898
1899 retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
1900 if (retval != ERROR_OK)
1901 return retval;
1902
1903 if (target->state != TARGET_HALTED)
1904 {
1905 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
1906 return ERROR_OK;
1907 }
1908
1909 if (argc > 0)
1910 {
1911 if (!strcmp(args[0], "on"))
1912 {
1913 cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1914 }
1915 else if (!strcmp(args[0], "off"))
1916 {
1917 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
1918 }
1919 else
1920 {
1921 command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']");
1922 }
1923 }
1924
1925 command_print(cmd_ctx, "cortex_m3 interrupt mask %s",
1926 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1927
1928 return ERROR_OK;
1929 }
1930
1931 static int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
1932 {
1933 int retval;
1934 command_t *cortex_m3_cmd;
1935
1936 retval = armv7m_register_commands(cmd_ctx);
1937
1938 cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
1939 NULL, COMMAND_ANY, "cortex_m3 specific commands");
1940
1941 register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
1942 handle_cortex_m3_disassemble_command, COMMAND_EXEC,
1943 "disassemble Thumb2 instructions <address> [<count>]");
1944 register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
1945 handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
1946 "mask cortex_m3 interrupts ['on'|'off']");
1947 register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
1948 handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
1949 "catch hardware vectors ['all'|'none'|<list>]");
1950
1951 return retval;
1952 }
1953
1954 target_type_t cortexm3_target =
1955 {
1956 .name = "cortex_m3",
1957
1958 .poll = cortex_m3_poll,
1959 .arch_state = armv7m_arch_state,
1960
1961 .target_request_data = cortex_m3_target_request_data,
1962
1963 .halt = cortex_m3_halt,
1964 .resume = cortex_m3_resume,
1965 .step = cortex_m3_step,
1966
1967 .assert_reset = cortex_m3_assert_reset,
1968 .deassert_reset = cortex_m3_deassert_reset,
1969 .soft_reset_halt = cortex_m3_soft_reset_halt,
1970
1971 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1972
1973 .read_memory = cortex_m3_read_memory,
1974 .write_memory = cortex_m3_write_memory,
1975 .bulk_write_memory = cortex_m3_bulk_write_memory,
1976 .checksum_memory = armv7m_checksum_memory,
1977 .blank_check_memory = armv7m_blank_check_memory,
1978
1979 .run_algorithm = armv7m_run_algorithm,
1980
1981 .add_breakpoint = cortex_m3_add_breakpoint,
1982 .remove_breakpoint = cortex_m3_remove_breakpoint,
1983 .add_watchpoint = cortex_m3_add_watchpoint,
1984 .remove_watchpoint = cortex_m3_remove_watchpoint,
1985
1986 .register_commands = cortex_m3_register_commands,
1987 .target_create = cortex_m3_target_create,
1988 .init_target = cortex_m3_init_target,
1989 .examine = cortex_m3_examine,
1990 };
Add cmsis-dap support