armv7a ,cortex a : add L1, L2 cache support, va to pa support
[openocd/cmsis-dap.git] / src / target / armv7m.h
blob8ef380088b4094d09e6efd2847562c183f4518c1
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
29 #include "arm_adi_v5.h"
30 #include "arm.h"
32 /* define for enabling armv7 gdb workarounds */
33 #if 1
34 #define ARMV7_GDB_HACKS
35 #endif
37 #ifdef ARMV7_GDB_HACKS
38 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
39 extern struct reg armv7m_gdb_dummy_cpsr_reg;
40 #endif
43 enum armv7m_mode
45 ARMV7M_MODE_THREAD = 0,
46 ARMV7M_MODE_USER_THREAD = 1,
47 ARMV7M_MODE_HANDLER = 2,
48 ARMV7M_MODE_ANY = -1
51 extern char *armv7m_mode_strings[];
53 enum armv7m_regtype
55 ARMV7M_REGISTER_CORE_GP,
56 ARMV7M_REGISTER_CORE_SP,
57 ARMV7M_REGISTER_MEMMAP
60 char *armv7m_exception_string(int number);
62 /* offsets into armv7m core register cache */
63 enum
65 /* for convenience, the first set of indices match
66 * the Cortex-M3 DCRSR selectors
68 ARMV7M_R0,
69 ARMV7M_R1,
70 ARMV7M_R2,
71 ARMV7M_R3,
73 ARMV7M_R4,
74 ARMV7M_R5,
75 ARMV7M_R6,
76 ARMV7M_R7,
78 ARMV7M_R8,
79 ARMV7M_R9,
80 ARMV7M_R10,
81 ARMV7M_R11,
83 ARMV7M_R12,
84 ARMV7M_R13,
85 ARMV7M_R14,
86 ARMV7M_PC = 15,
88 ARMV7M_xPSR = 16,
89 ARMV7M_MSP,
90 ARMV7M_PSP,
92 /* this next set of indices is arbitrary */
93 ARMV7M_PRIMASK,
94 ARMV7M_BASEPRI,
95 ARMV7M_FAULTMASK,
96 ARMV7M_CONTROL,
99 #define ARMV7M_COMMON_MAGIC 0x2A452A45
101 struct armv7m_common
103 struct arm arm;
105 int common_magic;
106 struct reg_cache *core_cache;
107 enum armv7m_mode core_mode;
108 int exception_number;
109 struct adiv5_dap dap;
111 uint32_t demcr;
113 /* Direct processor core register read and writes */
114 int (*load_core_reg_u32)(struct target *target,
115 enum armv7m_regtype type, uint32_t num, uint32_t *value);
116 int (*store_core_reg_u32)(struct target *target,
117 enum armv7m_regtype type, uint32_t num, uint32_t value);
119 /* register cache to processor synchronization */
120 int (*read_core_reg)(struct target *target, unsigned num);
121 int (*write_core_reg)(struct target *target, unsigned num);
123 int (*examine_debug_reason)(struct target *target);
124 int (*post_debug_entry)(struct target *target);
126 void (*pre_restore_context)(struct target *target);
129 static inline struct armv7m_common *
130 target_to_armv7m(struct target *target)
132 return container_of(target->arch_info, struct armv7m_common, arm);
135 static inline bool is_armv7m(struct armv7m_common *armv7m)
137 return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
140 struct armv7m_algorithm
142 int common_magic;
144 enum armv7m_mode core_mode;
147 struct armv7m_core_reg
149 uint32_t num;
150 enum armv7m_regtype type;
151 struct target *target;
152 struct armv7m_common *armv7m_common;
155 struct reg_cache *armv7m_build_reg_cache(struct target *target);
156 enum armv7m_mode armv7m_number_to_mode(int number);
157 int armv7m_mode_to_number(enum armv7m_mode mode);
159 int armv7m_arch_state(struct target *target);
160 int armv7m_get_gdb_reg_list(struct target *target,
161 struct reg **reg_list[], int *reg_list_size);
163 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
165 int armv7m_run_algorithm(struct target *target,
166 int num_mem_params, struct mem_param *mem_params,
167 int num_reg_params, struct reg_param *reg_params,
168 uint32_t entry_point, uint32_t exit_point,
169 int timeout_ms, void *arch_info);
171 int armv7m_invalidate_core_regs(struct target *target);
173 int armv7m_restore_context(struct target *target);
175 int armv7m_checksum_memory(struct target *target,
176 uint32_t address, uint32_t count, uint32_t* checksum);
177 int armv7m_blank_check_memory(struct target *target,
178 uint32_t address, uint32_t count, uint32_t* blank);
180 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
182 extern const struct command_registration armv7m_command_handlers[];
184 #endif /* ARMV7M_H */