1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
26 * Freescale iMX OpenOCD NAND Flash controller support.
27 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; mxc_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
46 #include <target/target.h>
48 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
49 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
50 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX35)
52 /* This permits to print (in LOG_INFO) how much bytes
53 * has been written after a page read or write.
54 * This is useful when OpenOCD is used with a graphical
55 * front-end to estimate progression of the global read/write
57 #undef _MXC_PRINT_STAT
58 /* #define _MXC_PRINT_STAT */
60 static const char target_not_halted_err_msg
[] =
61 "target must be halted to use mxc NAND flash controller";
62 static const char data_block_size_err_msg
[] =
63 "minimal granularity is one half-word, %" PRId32
" is incorrect";
64 static const char sram_buffer_bounds_err_msg
[] =
65 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
66 static const char get_status_register_err_msg
[] = "can't get NAND status";
67 static uint32_t in_sram_address
;
68 static unsigned char sign_of_sequental_byte_read
;
70 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
);
71 static int initialize_nf_controller(struct nand_device
*nand
);
72 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
);
73 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
);
74 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
);
75 static int validate_target_state(struct nand_device
*nand
);
76 static int do_data_output(struct nand_device
*nand
);
78 static int mxc_command(struct nand_device
*nand
, uint8_t command
);
79 static int mxc_address(struct nand_device
*nand
, uint8_t address
);
81 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command
)
83 struct mxc_nf_controller
*mxc_nf_info
;
87 mxc_nf_info
= malloc(sizeof(struct mxc_nf_controller
));
88 if (mxc_nf_info
== NULL
) {
89 LOG_ERROR("no memory for nand controller");
92 nand
->controller_priv
= mxc_nf_info
;
95 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
102 if (strcmp(CMD_ARGV
[2], "mx27") == 0) {
103 mxc_nf_info
->mxc_version
= MXC_VERSION_MX27
;
104 mxc_nf_info
->mxc_base_addr
= 0xD8000000;
105 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
106 } else if (strcmp(CMD_ARGV
[2], "mx31") == 0) {
107 mxc_nf_info
->mxc_version
= MXC_VERSION_MX31
;
108 mxc_nf_info
->mxc_base_addr
= 0xB8000000;
109 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
110 } else if (strcmp(CMD_ARGV
[2], "mx35") == 0) {
111 mxc_nf_info
->mxc_version
= MXC_VERSION_MX35
;
112 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
113 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x1E00;
117 * check hwecc requirements
119 hwecc_needed
= strcmp(CMD_ARGV
[3], "hwecc");
120 if (hwecc_needed
== 0)
121 mxc_nf_info
->flags
.hw_ecc_enabled
= 1;
123 mxc_nf_info
->flags
.hw_ecc_enabled
= 0;
125 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
126 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
127 mxc_nf_info
->flags
.target_little_endian
=
128 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
131 * should factory bad block indicator be swaped
132 * as a workaround for how the nfc handles pages.
134 if (CMD_ARGC
> 4 && strcmp(CMD_ARGV
[4], "biswap") == 0) {
135 LOG_DEBUG("BI-swap enabled");
136 mxc_nf_info
->flags
.biswap_enabled
= 1;
140 * testing host endianness
143 if (*(char *) &x
== 1)
144 mxc_nf_info
->flags
.host_little_endian
= 1;
146 mxc_nf_info
->flags
.host_little_endian
= 0;
150 COMMAND_HANDLER(handle_mxc_biswap_command
)
152 struct nand_device
*nand
= NULL
;
153 struct mxc_nf_controller
*mxc_nf_info
= NULL
;
155 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
156 return ERROR_COMMAND_SYNTAX_ERROR
;
158 int retval
= CALL_COMMAND_HANDLER(nand_command_get_device
, 0, &nand
);
159 if (retval
!= ERROR_OK
) {
160 command_print(CMD_CTX
, "invalid nand device number or name: %s", CMD_ARGV
[0]);
161 return ERROR_COMMAND_ARGUMENT_INVALID
;
164 mxc_nf_info
= nand
->controller_priv
;
166 if (strcmp(CMD_ARGV
[1], "enable") == 0)
167 mxc_nf_info
->flags
.biswap_enabled
= true;
169 mxc_nf_info
->flags
.biswap_enabled
= false;
171 if (mxc_nf_info
->flags
.biswap_enabled
)
172 command_print(CMD_CTX
, "BI-swapping enabled on %s", nand
->name
);
174 command_print(CMD_CTX
, "BI-swapping disabled on %s", nand
->name
);
179 static const struct command_registration mxc_sub_command_handlers
[] = {
182 .handler
= handle_mxc_biswap_command
,
183 .help
= "Turns on/off bad block information swaping from main area, "
184 "without parameter query status.",
185 .usage
= "bank_id ['enable'|'disable']",
187 COMMAND_REGISTRATION_DONE
190 static const struct command_registration mxc_nand_command_handler
[] = {
194 .help
= "MXC NAND flash controller commands",
195 .chain
= mxc_sub_command_handlers
197 COMMAND_REGISTRATION_DONE
200 static int mxc_init(struct nand_device
*nand
)
202 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
203 struct target
*target
= nand
->target
;
205 int validate_target_result
;
206 uint16_t buffsize_register_content
;
207 uint32_t sreg_content
;
208 uint32_t SREG
= MX2_FMCR
;
209 uint32_t SEL_16BIT
= MX2_FMCR_NF_16BIT_SEL
;
210 uint32_t SEL_FMS
= MX2_FMCR_NF_FMS
;
212 uint16_t nand_status_content
;
214 * validate target state
216 validate_target_result
= validate_target_state(nand
);
217 if (validate_target_result
!= ERROR_OK
)
218 return validate_target_result
;
221 target_read_u16(target
, MXC_NF_BUFSIZ
, &buffsize_register_content
);
222 mxc_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
224 mxc_nf_info
->flags
.one_kb_sram
= 0;
226 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX31
) {
228 SEL_16BIT
= MX3_PCSR_NF_16BIT_SEL
;
229 SEL_FMS
= MX3_PCSR_NF_FMS
;
230 } else if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX35
) {
232 SEL_16BIT
= MX35_RCSR_NF_16BIT_SEL
;
233 SEL_FMS
= MX35_RCSR_NF_FMS
;
236 target_read_u32(target
, SREG
, &sreg_content
);
237 if (!nand
->bus_width
) {
238 /* bus_width not yet defined. Read it from MXC_FMCR */
239 nand
->bus_width
= (sreg_content
& SEL_16BIT
) ? 16 : 8;
241 /* bus_width forced in soft. Sync it to MXC_FMCR */
242 sreg_content
|= ((nand
->bus_width
== 16) ? SEL_16BIT
: 0x00000000);
243 target_write_u32(target
, SREG
, sreg_content
);
245 if (nand
->bus_width
== 16)
246 LOG_DEBUG("MXC_NF : bus is 16-bit width");
248 LOG_DEBUG("MXC_NF : bus is 8-bit width");
250 if (!nand
->page_size
) {
251 nand
->page_size
= (sreg_content
& SEL_FMS
) ? 2048 : 512;
253 sreg_content
|= ((nand
->page_size
== 2048) ? SEL_FMS
: 0x00000000);
254 target_write_u32(target
, SREG
, sreg_content
);
256 if (mxc_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
257 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
258 "pagesize 2048 is incompatible with it");
260 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
263 if (nfc_is_v2() && sreg_content
& MX35_RCSR_NF_4K
)
264 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
266 initialize_nf_controller(nand
);
269 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
270 retval
|= mxc_address(nand
, 0x00);
271 retval
|= do_data_output(nand
);
272 if (retval
!= ERROR_OK
) {
273 LOG_ERROR(get_status_register_err_msg
);
276 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
277 if (!(nand_status_content
& 0x0080)) {
278 LOG_INFO("NAND read-only");
279 mxc_nf_info
->flags
.nand_readonly
= 1;
281 mxc_nf_info
->flags
.nand_readonly
= 0;
286 static int mxc_read_data(struct nand_device
*nand
, void *data
)
288 int validate_target_result
;
289 int try_data_output_from_nand_chip
;
291 * validate target state
293 validate_target_result
= validate_target_state(nand
);
294 if (validate_target_result
!= ERROR_OK
)
295 return validate_target_result
;
298 * get data from nand chip
300 try_data_output_from_nand_chip
= do_data_output(nand
);
301 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
302 LOG_ERROR("mxc_read_data : read data failed : '%x'",
303 try_data_output_from_nand_chip
);
304 return try_data_output_from_nand_chip
;
307 if (nand
->bus_width
== 16)
308 get_next_halfword_from_sram_buffer(nand
, data
);
310 get_next_byte_from_sram_buffer(nand
, data
);
315 static int mxc_write_data(struct nand_device
*nand
, uint16_t data
)
317 LOG_ERROR("write_data() not implemented");
318 return ERROR_NAND_OPERATION_FAILED
;
321 static int mxc_reset(struct nand_device
*nand
)
324 * validate target state
326 int validate_target_result
;
327 validate_target_result
= validate_target_state(nand
);
328 if (validate_target_result
!= ERROR_OK
)
329 return validate_target_result
;
330 initialize_nf_controller(nand
);
334 static int mxc_command(struct nand_device
*nand
, uint8_t command
)
336 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
337 struct target
*target
= nand
->target
;
338 int validate_target_result
;
341 * validate target state
343 validate_target_result
= validate_target_state(nand
);
344 if (validate_target_result
!= ERROR_OK
)
345 return validate_target_result
;
348 case NAND_CMD_READOOB
:
349 command
= NAND_CMD_READ0
;
350 /* set read point for data_read() and read_block_data() to
351 * spare area in SRAM buffer
354 in_sram_address
= MXC_NF_V1_SPARE_BUFFER0
;
356 in_sram_address
= MXC_NF_V2_SPARE_BUFFER0
;
359 command
= NAND_CMD_READ0
;
361 * offset == one half of page size
363 in_sram_address
= MXC_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
366 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
370 target_write_u16(target
, MXC_NF_FCMD
, command
);
372 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
374 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FCI
);
375 poll_result
= poll_for_complete_op(nand
, "command");
376 if (poll_result
!= ERROR_OK
)
379 * reset cursor to begin of the buffer
381 sign_of_sequental_byte_read
= 0;
382 /* Handle special read command and adjust NF_CFG2(FDO) */
384 case NAND_CMD_READID
:
385 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDID
;
386 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
388 case NAND_CMD_STATUS
:
389 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
390 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
391 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
395 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
396 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
399 /* Ohter command use the default 'One page data out' FDO */
400 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
406 static int mxc_address(struct nand_device
*nand
, uint8_t address
)
408 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
409 struct target
*target
= nand
->target
;
410 int validate_target_result
;
413 * validate target state
415 validate_target_result
= validate_target_state(nand
);
416 if (validate_target_result
!= ERROR_OK
)
417 return validate_target_result
;
419 target_write_u16(target
, MXC_NF_FADDR
, address
);
421 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
423 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FAI
);
424 poll_result
= poll_for_complete_op(nand
, "address");
425 if (poll_result
!= ERROR_OK
)
431 static int mxc_nand_ready(struct nand_device
*nand
, int tout
)
433 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
434 struct target
*target
= nand
->target
;
435 uint16_t poll_complete_status
;
436 int validate_target_result
;
439 * validate target state
441 validate_target_result
= validate_target_state(nand
);
442 if (validate_target_result
!= ERROR_OK
)
443 return validate_target_result
;
446 target_read_u16(target
, MXC_NF_CFG2
, &poll_complete_status
);
447 if (poll_complete_status
& MXC_NF_BIT_OP_DONE
)
456 static int mxc_write_page(struct nand_device
*nand
, uint32_t page
,
457 uint8_t *data
, uint32_t data_size
,
458 uint8_t *oob
, uint32_t oob_size
)
460 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
461 struct target
*target
= nand
->target
;
463 uint16_t nand_status_content
;
464 uint16_t swap1
, swap2
, new_swap1
;
469 LOG_ERROR(data_block_size_err_msg
, data_size
);
470 return ERROR_NAND_OPERATION_FAILED
;
473 LOG_ERROR(data_block_size_err_msg
, oob_size
);
474 return ERROR_NAND_OPERATION_FAILED
;
477 LOG_ERROR("nothing to program");
478 return ERROR_NAND_OPERATION_FAILED
;
482 * validate target state
484 retval
= validate_target_state(nand
);
485 if (retval
!= ERROR_OK
)
488 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
489 sign_of_sequental_byte_read
= 0;
491 retval
|= mxc_command(nand
, NAND_CMD_SEQIN
);
492 retval
|= mxc_address(nand
, 0); /* col */
493 retval
|= mxc_address(nand
, 0); /* col */
494 retval
|= mxc_address(nand
, page
& 0xff); /* page address */
495 retval
|= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
496 retval
|= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
498 target_write_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
500 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
502 * part of spare block will be overrided by hardware
505 LOG_DEBUG("part of spare block will be overrided "
506 "by hardware ECC generator");
509 target_write_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
511 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
512 while (oob_size
> 0) {
513 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
514 target_write_buffer(target
, addr
, len
, oob
);
515 addr
= align_address_v2(nand
, addr
+ len
);
522 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
523 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
524 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
526 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
527 return ERROR_NAND_OPERATION_FAILED
;
529 swap2
= 0xffff; /* Spare buffer unused forced to 0xffff */
530 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
531 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
532 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
534 target_write_u16(target
, MXC_NF_V1_SPARE_BUFFER3
, swap2
);
536 target_write_u16(target
, MXC_NF_V2_SPARE_BUFFER3
, swap2
);
540 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
542 if (nfc_is_v1() && nand
->page_size
> 512)
547 for (uint8_t i
= 0 ; i
< bufs
; ++i
) {
548 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
549 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
550 poll_result
= poll_for_complete_op(nand
, "data input");
551 if (poll_result
!= ERROR_OK
)
555 retval
|= mxc_command(nand
, NAND_CMD_PAGEPROG
);
556 if (retval
!= ERROR_OK
)
560 * check status register
563 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
564 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
565 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
566 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
567 retval
|= do_data_output(nand
);
568 if (retval
!= ERROR_OK
) {
569 LOG_ERROR(get_status_register_err_msg
);
572 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
573 if (nand_status_content
& 0x0001) {
575 * page not correctly written
577 return ERROR_NAND_OPERATION_FAILED
;
579 #ifdef _MXC_PRINT_STAT
580 LOG_INFO("%d bytes newly written", data_size
);
585 static int mxc_read_page(struct nand_device
*nand
, uint32_t page
,
586 uint8_t *data
, uint32_t data_size
,
587 uint8_t *oob
, uint32_t oob_size
)
589 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
590 struct target
*target
= nand
->target
;
593 uint16_t swap1
, swap2
, new_swap1
;
596 LOG_ERROR(data_block_size_err_msg
, data_size
);
597 return ERROR_NAND_OPERATION_FAILED
;
600 LOG_ERROR(data_block_size_err_msg
, oob_size
);
601 return ERROR_NAND_OPERATION_FAILED
;
605 * validate target state
607 retval
= validate_target_state(nand
);
608 if (retval
!= ERROR_OK
) {
611 /* Reset address_cycles before mxc_command ?? */
612 retval
= mxc_command(nand
, NAND_CMD_READ0
);
613 if (retval
!= ERROR_OK
) return retval
;
614 retval
= mxc_address(nand
, 0); /* col */
615 if (retval
!= ERROR_OK
) return retval
;
616 retval
= mxc_address(nand
, 0); /* col */
617 if (retval
!= ERROR_OK
) return retval
;
618 retval
= mxc_address(nand
, page
& 0xff); /* page address */
619 if (retval
!= ERROR_OK
) return retval
;
620 retval
= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
621 if (retval
!= ERROR_OK
) return retval
;
622 retval
= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
623 if (retval
!= ERROR_OK
) return retval
;
624 retval
= mxc_command(nand
, NAND_CMD_READSTART
);
625 if (retval
!= ERROR_OK
) return retval
;
627 if (nfc_is_v1() && nand
->page_size
> 512)
632 for (uint8_t i
= 0 ; i
< bufs
; ++i
) {
633 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
634 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
635 retval
= do_data_output(nand
);
636 if (retval
!= ERROR_OK
) {
637 LOG_ERROR("MXC_NF : Error reading page %d", i
);
642 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
643 uint32_t SPARE_BUFFER3
;
644 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
645 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
647 SPARE_BUFFER3
= MXC_NF_V1_SPARE_BUFFER3
;
649 SPARE_BUFFER3
= MXC_NF_V2_SPARE_BUFFER3
;
650 target_read_u16(target
, SPARE_BUFFER3
, &swap2
);
651 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
652 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
653 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
654 target_write_u16(target
, SPARE_BUFFER3
, swap2
);
658 target_read_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
661 target_read_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
663 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
664 while (oob_size
> 0) {
665 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
666 target_read_buffer(target
, addr
, len
, oob
);
667 addr
= align_address_v2(nand
, addr
+ len
);
674 #ifdef _MXC_PRINT_STAT
676 /* When Operation Status is read (when page is erased),
677 * this function is used but data_size is null.
679 LOG_INFO("%d bytes newly read", data_size
);
685 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
)
687 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
689 if (addr
> MXC_NF_V2_SPARE_BUFFER0
&&
690 (addr
& 0x1F) == MXC_NF_SPARE_BUFFER_LEN
) {
691 ret
+= MXC_NF_SPARE_BUFFER_MAX
- MXC_NF_SPARE_BUFFER_LEN
;
692 } else if (addr
>= (mxc_nf_info
->mxc_base_addr
+ (uint32_t)nand
->page_size
))
693 ret
= MXC_NF_V2_SPARE_BUFFER0
;
697 static int initialize_nf_controller(struct nand_device
*nand
)
699 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
700 struct target
*target
= nand
->target
;
701 uint16_t work_mode
= 0;
704 * resets NAND flash controller in zero time ? I dont know.
706 target_write_u16(target
, MXC_NF_CFG1
, MXC_NF_BIT_RESET_EN
);
707 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX27
)
708 work_mode
= MXC_NF_BIT_INT_DIS
; /* disable interrupt */
710 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
711 LOG_DEBUG("MXC_NF : work in Big Endian mode");
712 work_mode
|= MXC_NF_BIT_BE_EN
;
714 LOG_DEBUG("MXC_NF : work in Little Endian mode");
716 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
717 LOG_DEBUG("MXC_NF : work with ECC mode");
718 work_mode
|= MXC_NF_BIT_ECC_EN
;
720 LOG_DEBUG("MXC_NF : work without ECC mode");
723 if (nand
->page_size
) {
724 uint16_t pages_per_block
= nand
->erase_size
/ nand
->page_size
;
725 work_mode
|= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block
) - 6);
727 work_mode
|= MXC_NF_BIT_ECC_4BIT
;
729 target_write_u16(target
, MXC_NF_CFG1
, work_mode
);
732 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
734 target_write_u16(target
, MXC_NF_BUFCFG
, 2);
735 target_read_u16(target
, MXC_NF_FWP
, &temp
);
736 if ((temp
& 0x0007) == 1) {
737 LOG_ERROR("NAND flash is tight-locked, reset needed");
742 * unlock NAND flash for write
745 target_write_u16(target
, MXC_NF_V1_UNLOCKSTART
, 0x0000);
746 target_write_u16(target
, MXC_NF_V1_UNLOCKEND
, 0xFFFF);
748 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART0
, 0x0000);
749 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART1
, 0x0000);
750 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART2
, 0x0000);
751 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART3
, 0x0000);
752 target_write_u16(target
, MXC_NF_V2_UNLOCKEND0
, 0xFFFF);
753 target_write_u16(target
, MXC_NF_V2_UNLOCKEND1
, 0xFFFF);
754 target_write_u16(target
, MXC_NF_V2_UNLOCKEND2
, 0xFFFF);
755 target_write_u16(target
, MXC_NF_V2_UNLOCKEND3
, 0xFFFF);
757 target_write_u16(target
, MXC_NF_FWP
, 4);
760 * 0x0000 means that first SRAM buffer @base_addr will be used
762 target_write_u16(target
, MXC_NF_BUFADDR
, 0x0000);
764 * address of SRAM buffer
766 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
767 sign_of_sequental_byte_read
= 0;
771 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
)
773 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
774 struct target
*target
= nand
->target
;
775 static uint8_t even_byte
= 0;
780 if (sign_of_sequental_byte_read
== 0)
783 if (in_sram_address
>
784 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
785 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
787 sign_of_sequental_byte_read
= 0;
789 return ERROR_NAND_OPERATION_FAILED
;
792 in_sram_address
= align_address_v2(nand
, in_sram_address
);
794 target_read_u16(target
, in_sram_address
, &temp
);
798 in_sram_address
+= 2;
800 *value
= temp
& 0xff;
804 sign_of_sequental_byte_read
= 1;
808 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
)
810 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
811 struct target
*target
= nand
->target
;
813 if (in_sram_address
>
814 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
815 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
817 return ERROR_NAND_OPERATION_FAILED
;
820 in_sram_address
= align_address_v2(nand
, in_sram_address
);
822 target_read_u16(target
, in_sram_address
, value
);
823 in_sram_address
+= 2;
828 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
)
830 if (mxc_nand_ready(nand
, 1000) == -1) {
831 LOG_ERROR("%s sending timeout", text
);
832 return ERROR_NAND_OPERATION_FAILED
;
837 static int validate_target_state(struct nand_device
*nand
)
839 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
840 struct target
*target
= nand
->target
;
842 if (target
->state
!= TARGET_HALTED
) {
843 LOG_ERROR(target_not_halted_err_msg
);
844 return ERROR_NAND_OPERATION_FAILED
;
847 if (mxc_nf_info
->flags
.target_little_endian
!=
848 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
850 * endianness changed after NAND controller probed
852 return ERROR_NAND_OPERATION_FAILED
;
857 int ecc_status_v1(struct nand_device
*nand
)
859 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
860 struct target
*target
= nand
->target
;
863 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
864 switch (ecc_status
& 0x000c) {
866 LOG_INFO("main area read with 1 (correctable) error");
869 LOG_INFO("main area read with more than 1 (incorrectable) error");
870 return ERROR_NAND_OPERATION_FAILED
;
873 switch (ecc_status
& 0x0003) {
875 LOG_INFO("spare area read with 1 (correctable) error");
878 LOG_INFO("main area read with more than 1 (incorrectable) error");
879 return ERROR_NAND_OPERATION_FAILED
;
885 int ecc_status_v2(struct nand_device
*nand
)
887 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
888 struct target
*target
= nand
->target
;
893 no_subpages
= nand
->page_size
>> 9;
895 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
897 err
= ecc_status
& 0xF;
899 LOG_INFO("UnCorrectable RS-ECC Error");
900 return ERROR_NAND_OPERATION_FAILED
;
902 LOG_INFO("%d Symbol Correctable RS-ECC Error", err
);
904 } while (--no_subpages
);
908 static int do_data_output(struct nand_device
*nand
)
910 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
911 struct target
*target
= nand
->target
;
913 switch (mxc_nf_info
->fin
) {
914 case MXC_NF_FIN_DATAOUT
:
916 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
918 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info
->optype
));
919 poll_result
= poll_for_complete_op(nand
, "data output");
920 if (poll_result
!= ERROR_OK
)
923 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
927 if (mxc_nf_info
->optype
== MXC_NF_DATAOUT_PAGE
&&
928 mxc_nf_info
->flags
.hw_ecc_enabled
) {
931 ecc_status
= ecc_status_v1(nand
);
933 ecc_status
= ecc_status_v2(nand
);
934 if (ecc_status
!= ERROR_OK
)
938 case MXC_NF_FIN_NONE
:
944 struct nand_flash_controller mxc_nand_flash_controller
= {
946 .nand_device_command
= &mxc_nand_device_command
,
947 .commands
= mxc_nand_command_handler
,
950 .command
= &mxc_command
,
951 .address
= &mxc_address
,
952 .write_data
= &mxc_write_data
,
953 .read_data
= &mxc_read_data
,
954 .write_page
= &mxc_write_page
,
955 .read_page
= &mxc_read_page
,
956 .nand_ready
= &mxc_nand_ready
,