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Documentation for mxc NAND flash controller
[openocd/andreasf.git] / src / flash / nand / mx2.c
bloba4e6eb1a1e86cba9ff1a38419fd10a36d99b7a1c
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 /*
26 * Freescale iMX OpenOCD NAND Flash controller support.
27 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
28 */
29
30 /*
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
34 *
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; mxc_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
39 */
40 #ifdef HAVE_CONFIG_H
41 #include "config.h"
42 #endif
43
44 #include "imp.h"
45 #include "mx2.h"
46 #include <target/target.h>
47
48 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
49 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
50 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX35)
51
52 /* This permits to print (in LOG_INFO) how much bytes
53 * has been written after a page read or write.
54 * This is useful when OpenOCD is used with a graphical
55 * front-end to estimate progression of the global read/write
56 */
57 #undef _MXC_PRINT_STAT
58 /* #define _MXC_PRINT_STAT */
59
60 static const char target_not_halted_err_msg[] =
61 "target must be halted to use mxc NAND flash controller";
62 static const char data_block_size_err_msg[] =
63 "minimal granularity is one half-word, %" PRId32 " is incorrect";
64 static const char sram_buffer_bounds_err_msg[] =
65 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
66 static const char get_status_register_err_msg[] = "can't get NAND status";
67 static uint32_t in_sram_address;
68 static unsigned char sign_of_sequental_byte_read;
69
70 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
71 static int initialize_nf_controller(struct nand_device *nand);
72 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
73 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
74 static int poll_for_complete_op(struct nand_device *nand, const char *text);
75 static int validate_target_state(struct nand_device *nand);
76 static int do_data_output(struct nand_device *nand);
77
78 static int mxc_command(struct nand_device *nand, uint8_t command);
79 static int mxc_address(struct nand_device *nand, uint8_t address);
80
81 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
82 {
83 struct mxc_nf_controller *mxc_nf_info;
84 int hwecc_needed;
85 int x;
86
87 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
88 if (mxc_nf_info == NULL) {
89 LOG_ERROR("no memory for nand controller");
90 return ERROR_FAIL;
91 }
92 nand->controller_priv = mxc_nf_info;
93
94 if (CMD_ARGC < 4) {
95 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
96 return ERROR_FAIL;
97 }
98
99 /*
100 * check board type
101 */
102 if (strcmp(CMD_ARGV[2], "mx27") == 0) {
103 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
104 mxc_nf_info->mxc_base_addr = 0xD8000000;
105 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
106 } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
107 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
108 mxc_nf_info->mxc_base_addr = 0xB8000000;
109 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
110 } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
111 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
112 mxc_nf_info->mxc_base_addr = 0xBB000000;
113 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
114 }
115
116 /*
117 * check hwecc requirements
118 */
119 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
120 if (hwecc_needed == 0)
121 mxc_nf_info->flags.hw_ecc_enabled = 1;
122 else
123 mxc_nf_info->flags.hw_ecc_enabled = 0;
124
125 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
126 mxc_nf_info->fin = MXC_NF_FIN_NONE;
127 mxc_nf_info->flags.target_little_endian =
128 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
129
130 /*
131 * should factory bad block indicator be swaped
132 * as a workaround for how the nfc handles pages.
133 */
134 if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
135 LOG_DEBUG("BI-swap enabled");
136 mxc_nf_info->flags.biswap_enabled = 1;
137 }
138
139 /*
140 * testing host endianness
141 */
142 x = 1;
143 if (*(char *) &x == 1)
144 mxc_nf_info->flags.host_little_endian = 1;
145 else
146 mxc_nf_info->flags.host_little_endian = 0;
147 return ERROR_OK;
148 }
149
150 COMMAND_HANDLER(handle_mxc_biswap_command)
151 {
152 struct nand_device *nand = NULL;
153 struct mxc_nf_controller *mxc_nf_info = NULL;
154
155 if (CMD_ARGC < 1 || CMD_ARGC > 2)
156 return ERROR_COMMAND_SYNTAX_ERROR;
157
158 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
159 if (retval != ERROR_OK) {
160 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
161 return ERROR_COMMAND_ARGUMENT_INVALID;
162 }
163
164 mxc_nf_info = nand->controller_priv;
165 if (CMD_ARGC == 2) {
166 if (strcmp(CMD_ARGV[1], "enable") == 0)
167 mxc_nf_info->flags.biswap_enabled = true;
168 else
169 mxc_nf_info->flags.biswap_enabled = false;
170 }
171 if (mxc_nf_info->flags.biswap_enabled)
172 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
173 else
174 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
175
176 return ERROR_OK;
177 }
178
179 static const struct command_registration mxc_sub_command_handlers[] = {
180 {
181 .name = "biswap",
182 .handler = handle_mxc_biswap_command ,
183 .help = "Turns on/off bad block information swaping from main area, "
184 "without parameter query status.",
185 .usage = "bank_id ['enable'|'disable']",
186 },
187 COMMAND_REGISTRATION_DONE
188 };
189
190 static const struct command_registration mxc_nand_command_handler[] = {
191 {
192 .name = "mxc",
193 .mode = COMMAND_ANY,
194 .help = "MXC NAND flash controller commands",
195 .chain = mxc_sub_command_handlers
196 },
197 COMMAND_REGISTRATION_DONE
198 };
199
200 static int mxc_init(struct nand_device *nand)
201 {
202 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
203 struct target *target = nand->target;
204
205 int validate_target_result;
206 uint16_t buffsize_register_content;
207 uint32_t sreg_content;
208 uint32_t SREG = MX2_FMCR;
209 uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
210 uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
211 int retval;
212 uint16_t nand_status_content;
213 /*
214 * validate target state
215 */
216 validate_target_result = validate_target_state(nand);
217 if (validate_target_result != ERROR_OK)
218 return validate_target_result;
219
220 if (nfc_is_v1()) {
221 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
222 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
223 } else
224 mxc_nf_info->flags.one_kb_sram = 0;
225
226 if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
227 SREG = MX3_PCSR;
228 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
229 SEL_FMS = MX3_PCSR_NF_FMS;
230 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
231 SREG = MX35_RCSR;
232 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
233 SEL_FMS = MX35_RCSR_NF_FMS;
234 }
235
236 target_read_u32(target, SREG, &sreg_content);
237 if (!nand->bus_width) {
238 /* bus_width not yet defined. Read it from MXC_FMCR */
239 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
240 } else {
241 /* bus_width forced in soft. Sync it to MXC_FMCR */
242 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
243 target_write_u32(target, SREG, sreg_content);
244 }
245 if (nand->bus_width == 16)
246 LOG_DEBUG("MXC_NF : bus is 16-bit width");
247 else
248 LOG_DEBUG("MXC_NF : bus is 8-bit width");
249
250 if (!nand->page_size) {
251 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
252 } else {
253 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
254 target_write_u32(target, SREG, sreg_content);
255 }
256 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
257 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
258 "pagesize 2048 is incompatible with it");
259 } else {
260 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
261 }
262
263 if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
264 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
265
266 initialize_nf_controller(nand);
267
268 retval = ERROR_OK;
269 retval |= mxc_command(nand, NAND_CMD_STATUS);
270 retval |= mxc_address(nand, 0x00);
271 retval |= do_data_output(nand);
272 if (retval != ERROR_OK) {
273 LOG_ERROR(get_status_register_err_msg);
274 return ERROR_FAIL;
275 }
276 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
277 if (!(nand_status_content & 0x0080)) {
278 LOG_INFO("NAND read-only");
279 mxc_nf_info->flags.nand_readonly = 1;
280 } else {
281 mxc_nf_info->flags.nand_readonly = 0;
282 }
283 return ERROR_OK;
284 }
285
286 static int mxc_read_data(struct nand_device *nand, void *data)
287 {
288 int validate_target_result;
289 int try_data_output_from_nand_chip;
290 /*
291 * validate target state
292 */
293 validate_target_result = validate_target_state(nand);
294 if (validate_target_result != ERROR_OK)
295 return validate_target_result;
296
297 /*
298 * get data from nand chip
299 */
300 try_data_output_from_nand_chip = do_data_output(nand);
301 if (try_data_output_from_nand_chip != ERROR_OK) {
302 LOG_ERROR("mxc_read_data : read data failed : '%x'",
303 try_data_output_from_nand_chip);
304 return try_data_output_from_nand_chip;
305 }
306
307 if (nand->bus_width == 16)
308 get_next_halfword_from_sram_buffer(nand, data);
309 else
310 get_next_byte_from_sram_buffer(nand, data);
311
312 return ERROR_OK;
313 }
314
315 static int mxc_write_data(struct nand_device *nand, uint16_t data)
316 {
317 LOG_ERROR("write_data() not implemented");
318 return ERROR_NAND_OPERATION_FAILED;
319 }
320
321 static int mxc_reset(struct nand_device *nand)
322 {
323 /*
324 * validate target state
325 */
326 int validate_target_result;
327 validate_target_result = validate_target_state(nand);
328 if (validate_target_result != ERROR_OK)
329 return validate_target_result;
330 initialize_nf_controller(nand);
331 return ERROR_OK;
332 }
333
334 static int mxc_command(struct nand_device *nand, uint8_t command)
335 {
336 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
337 struct target *target = nand->target;
338 int validate_target_result;
339 int poll_result;
340 /*
341 * validate target state
342 */
343 validate_target_result = validate_target_state(nand);
344 if (validate_target_result != ERROR_OK)
345 return validate_target_result;
346
347 switch (command) {
348 case NAND_CMD_READOOB:
349 command = NAND_CMD_READ0;
350 /* set read point for data_read() and read_block_data() to
351 * spare area in SRAM buffer
352 */
353 if (nfc_is_v1())
354 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
355 else
356 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
357 break;
358 case NAND_CMD_READ1:
359 command = NAND_CMD_READ0;
360 /*
361 * offset == one half of page size
362 */
363 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
364 break;
365 default:
366 in_sram_address = MXC_NF_MAIN_BUFFER0;
367 break;
368 }
369
370 target_write_u16(target, MXC_NF_FCMD, command);
371 /*
372 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
373 */
374 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
375 poll_result = poll_for_complete_op(nand, "command");
376 if (poll_result != ERROR_OK)
377 return poll_result;
378 /*
379 * reset cursor to begin of the buffer
380 */
381 sign_of_sequental_byte_read = 0;
382 /* Handle special read command and adjust NF_CFG2(FDO) */
383 switch (command) {
384 case NAND_CMD_READID:
385 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
386 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
387 break;
388 case NAND_CMD_STATUS:
389 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
390 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
391 target_write_u16 (target, MXC_NF_BUFADDR, 0);
392 in_sram_address = 0;
393 break;
394 case NAND_CMD_READ0:
395 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
396 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
397 break;
398 default:
399 /* Ohter command use the default 'One page data out' FDO */
400 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
401 break;
402 }
403 return ERROR_OK;
404 }
405
406 static int mxc_address(struct nand_device *nand, uint8_t address)
407 {
408 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
409 struct target *target = nand->target;
410 int validate_target_result;
411 int poll_result;
412 /*
413 * validate target state
414 */
415 validate_target_result = validate_target_state(nand);
416 if (validate_target_result != ERROR_OK)
417 return validate_target_result;
418
419 target_write_u16(target, MXC_NF_FADDR, address);
420 /*
421 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
422 */
423 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
424 poll_result = poll_for_complete_op(nand, "address");
425 if (poll_result != ERROR_OK)
426 return poll_result;
427
428 return ERROR_OK;
429 }
430
431 static int mxc_nand_ready(struct nand_device *nand, int tout)
432 {
433 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
434 struct target *target = nand->target;
435 uint16_t poll_complete_status;
436 int validate_target_result;
437
438 /*
439 * validate target state
440 */
441 validate_target_result = validate_target_state(nand);
442 if (validate_target_result != ERROR_OK)
443 return validate_target_result;
444
445 do {
446 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
447 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
448 return tout;
449
450 alive_sleep(1);
451 }
452 while (tout-- > 0);
453 return tout;
454 }
455
456 static int mxc_write_page(struct nand_device *nand, uint32_t page,
457 uint8_t *data, uint32_t data_size,
458 uint8_t *oob, uint32_t oob_size)
459 {
460 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
461 struct target *target = nand->target;
462 int retval;
463 uint16_t nand_status_content;
464 uint16_t swap1, swap2, new_swap1;
465 uint8_t bufs;
466 int poll_result;
467
468 if (data_size % 2) {
469 LOG_ERROR(data_block_size_err_msg, data_size);
470 return ERROR_NAND_OPERATION_FAILED;
471 }
472 if (oob_size % 2) {
473 LOG_ERROR(data_block_size_err_msg, oob_size);
474 return ERROR_NAND_OPERATION_FAILED;
475 }
476 if (!data) {
477 LOG_ERROR("nothing to program");
478 return ERROR_NAND_OPERATION_FAILED;
479 }
480
481 /*
482 * validate target state
483 */
484 retval = validate_target_state(nand);
485 if (retval != ERROR_OK)
486 return retval;
487
488 in_sram_address = MXC_NF_MAIN_BUFFER0;
489 sign_of_sequental_byte_read = 0;
490 retval = ERROR_OK;
491 retval |= mxc_command(nand, NAND_CMD_SEQIN);
492 retval |= mxc_address(nand, 0); /* col */
493 retval |= mxc_address(nand, 0); /* col */
494 retval |= mxc_address(nand, page & 0xff); /* page address */
495 retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
496 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
497
498 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
499 if (oob) {
500 if (mxc_nf_info->flags.hw_ecc_enabled) {
501 /*
502 * part of spare block will be overrided by hardware
503 * ECC generator
504 */
505 LOG_DEBUG("part of spare block will be overrided "
506 "by hardware ECC generator");
507 }
508 if (nfc_is_v1())
509 target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
510 else {
511 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
512 while (oob_size > 0) {
513 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
514 target_write_buffer(target, addr, len, oob);
515 addr = align_address_v2(nand, addr + len);
516 oob += len;
517 oob_size -= len;
518 }
519 }
520 }
521
522 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
523 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
524 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
525 if (oob) {
526 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
527 return ERROR_NAND_OPERATION_FAILED;
528 }
529 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
530 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
531 swap2 = (swap1 << 8) | (swap2 & 0xFF);
532 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
533 if (nfc_is_v1())
534 target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3, swap2);
535 else
536 target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
537 }
538
539 /*
540 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
541 */
542 if (nfc_is_v1() && nand->page_size > 512)
543 bufs = 4;
544 else
545 bufs = 1;
546
547 for (uint8_t i = 0 ; i < bufs ; ++i) {
548 target_write_u16(target, MXC_NF_BUFADDR, i);
549 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
550 poll_result = poll_for_complete_op(nand, "data input");
551 if (poll_result != ERROR_OK)
552 return poll_result;
553 }
554
555 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
556 if (retval != ERROR_OK)
557 return retval;
558
559 /*
560 * check status register
561 */
562 retval = ERROR_OK;
563 retval |= mxc_command(nand, NAND_CMD_STATUS);
564 target_write_u16 (target, MXC_NF_BUFADDR, 0);
565 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
566 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
567 retval |= do_data_output(nand);
568 if (retval != ERROR_OK) {
569 LOG_ERROR(get_status_register_err_msg);
570 return retval;
571 }
572 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
573 if (nand_status_content & 0x0001) {
574 /*
575 * page not correctly written
576 */
577 return ERROR_NAND_OPERATION_FAILED;
578 }
579 #ifdef _MXC_PRINT_STAT
580 LOG_INFO("%d bytes newly written", data_size);
581 #endif
582 return ERROR_OK;
583 }
584
585 static int mxc_read_page(struct nand_device *nand, uint32_t page,
586 uint8_t *data, uint32_t data_size,
587 uint8_t *oob, uint32_t oob_size)
588 {
589 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
590 struct target *target = nand->target;
591 int retval;
592 uint8_t bufs;
593 uint16_t swap1, swap2, new_swap1;
594
595 if (data_size % 2) {
596 LOG_ERROR(data_block_size_err_msg, data_size);
597 return ERROR_NAND_OPERATION_FAILED;
598 }
599 if (oob_size % 2) {
600 LOG_ERROR(data_block_size_err_msg, oob_size);
601 return ERROR_NAND_OPERATION_FAILED;
602 }
603
604 /*
605 * validate target state
606 */
607 retval = validate_target_state(nand);
608 if (retval != ERROR_OK) {
609 return retval;
610 }
611 /* Reset address_cycles before mxc_command ?? */
612 retval = mxc_command(nand, NAND_CMD_READ0);
613 if (retval != ERROR_OK) return retval;
614 retval = mxc_address(nand, 0); /* col */
615 if (retval != ERROR_OK) return retval;
616 retval = mxc_address(nand, 0); /* col */
617 if (retval != ERROR_OK) return retval;
618 retval = mxc_address(nand, page & 0xff); /* page address */
619 if (retval != ERROR_OK) return retval;
620 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
621 if (retval != ERROR_OK) return retval;
622 retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
623 if (retval != ERROR_OK) return retval;
624 retval = mxc_command(nand, NAND_CMD_READSTART);
625 if (retval != ERROR_OK) return retval;
626
627 if (nfc_is_v1() && nand->page_size > 512)
628 bufs = 4;
629 else
630 bufs = 1;
631
632 for (uint8_t i = 0 ; i < bufs ; ++i) {
633 target_write_u16(target, MXC_NF_BUFADDR, i);
634 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
635 retval = do_data_output(nand);
636 if (retval != ERROR_OK) {
637 LOG_ERROR("MXC_NF : Error reading page %d", i);
638 return retval;
639 }
640 }
641
642 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
643 uint32_t SPARE_BUFFER3;
644 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
645 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
646 if (nfc_is_v1())
647 SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3;
648 else
649 SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
650 target_read_u16(target, SPARE_BUFFER3, &swap2);
651 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
652 swap2 = (swap1 << 8) | (swap2 & 0xFF);
653 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
654 target_write_u16(target, SPARE_BUFFER3, swap2);
655 }
656
657 if (data)
658 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
659 if (oob) {
660 if (nfc_is_v1())
661 target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
662 else {
663 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
664 while (oob_size > 0) {
665 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
666 target_read_buffer(target, addr, len, oob);
667 addr = align_address_v2(nand, addr + len);
668 oob += len;
669 oob_size -= len;
670 }
671 }
672 }
673
674 #ifdef _MXC_PRINT_STAT
675 if (data_size > 0) {
676 /* When Operation Status is read (when page is erased),
677 * this function is used but data_size is null.
678 */
679 LOG_INFO("%d bytes newly read", data_size);
680 }
681 #endif
682 return ERROR_OK;
683 }
684
685 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
686 {
687 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
688 uint32_t ret = addr;
689 if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
690 (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN) {
691 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
692 } else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
693 ret = MXC_NF_V2_SPARE_BUFFER0;
694 return ret;
695 }
696
697 static int initialize_nf_controller(struct nand_device *nand)
698 {
699 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
700 struct target *target = nand->target;
701 uint16_t work_mode = 0;
702 uint16_t temp;
703 /*
704 * resets NAND flash controller in zero time ? I dont know.
705 */
706 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
707 if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
708 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
709
710 if (target->endianness == TARGET_BIG_ENDIAN) {
711 LOG_DEBUG("MXC_NF : work in Big Endian mode");
712 work_mode |= MXC_NF_BIT_BE_EN;
713 } else {
714 LOG_DEBUG("MXC_NF : work in Little Endian mode");
715 }
716 if (mxc_nf_info->flags.hw_ecc_enabled) {
717 LOG_DEBUG("MXC_NF : work with ECC mode");
718 work_mode |= MXC_NF_BIT_ECC_EN;
719 } else {
720 LOG_DEBUG("MXC_NF : work without ECC mode");
721 }
722 if (nfc_is_v2()) {
723 if (nand->page_size) {
724 uint16_t pages_per_block = nand->erase_size / nand->page_size;
725 work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
726 }
727 work_mode |= MXC_NF_BIT_ECC_4BIT;
728 }
729 target_write_u16(target, MXC_NF_CFG1, work_mode);
730
731 /*
732 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
733 */
734 target_write_u16(target, MXC_NF_BUFCFG, 2);
735 target_read_u16(target, MXC_NF_FWP, &temp);
736 if ((temp & 0x0007) == 1) {
737 LOG_ERROR("NAND flash is tight-locked, reset needed");
738 return ERROR_FAIL;
739 }
740
741 /*
742 * unlock NAND flash for write
743 */
744 if (nfc_is_v1()) {
745 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
746 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
747 } else {
748 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
749 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
750 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
751 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
752 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
753 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
754 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
755 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
756 }
757 target_write_u16(target, MXC_NF_FWP, 4);
758
759 /*
760 * 0x0000 means that first SRAM buffer @base_addr will be used
761 */
762 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
763 /*
764 * address of SRAM buffer
765 */
766 in_sram_address = MXC_NF_MAIN_BUFFER0;
767 sign_of_sequental_byte_read = 0;
768 return ERROR_OK;
769 }
770
771 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
772 {
773 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
774 struct target *target = nand->target;
775 static uint8_t even_byte = 0;
776 uint16_t temp;
777 /*
778 * host-big_endian ??
779 */
780 if (sign_of_sequental_byte_read == 0)
781 even_byte = 0;
782
783 if (in_sram_address >
784 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
785 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
786 *value = 0;
787 sign_of_sequental_byte_read = 0;
788 even_byte = 0;
789 return ERROR_NAND_OPERATION_FAILED;
790 } else {
791 if (nfc_is_v2())
792 in_sram_address = align_address_v2(nand, in_sram_address);
793
794 target_read_u16(target, in_sram_address, &temp);
795 if (even_byte) {
796 *value = temp >> 8;
797 even_byte = 0;
798 in_sram_address += 2;
799 } else {
800 *value = temp & 0xff;
801 even_byte = 1;
802 }
803 }
804 sign_of_sequental_byte_read = 1;
805 return ERROR_OK;
806 }
807
808 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
809 {
810 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
811 struct target *target = nand->target;
812
813 if (in_sram_address >
814 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
815 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
816 *value = 0;
817 return ERROR_NAND_OPERATION_FAILED;
818 } else {
819 if (nfc_is_v2())
820 in_sram_address = align_address_v2(nand, in_sram_address);
821
822 target_read_u16(target, in_sram_address, value);
823 in_sram_address += 2;
824 }
825 return ERROR_OK;
826 }
827
828 static int poll_for_complete_op(struct nand_device *nand, const char *text)
829 {
830 if (mxc_nand_ready(nand, 1000) == -1) {
831 LOG_ERROR("%s sending timeout", text);
832 return ERROR_NAND_OPERATION_FAILED;
833 }
834 return ERROR_OK;
835 }
836
837 static int validate_target_state(struct nand_device *nand)
838 {
839 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
840 struct target *target = nand->target;
841
842 if (target->state != TARGET_HALTED) {
843 LOG_ERROR(target_not_halted_err_msg);
844 return ERROR_NAND_OPERATION_FAILED;
845 }
846
847 if (mxc_nf_info->flags.target_little_endian !=
848 (target->endianness == TARGET_LITTLE_ENDIAN)) {
849 /*
850 * endianness changed after NAND controller probed
851 */
852 return ERROR_NAND_OPERATION_FAILED;
853 }
854 return ERROR_OK;
855 }
856
857 int ecc_status_v1(struct nand_device *nand)
858 {
859 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
860 struct target *target = nand->target;
861 uint16_t ecc_status;
862
863 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
864 switch (ecc_status & 0x000c) {
865 case 1 << 2:
866 LOG_INFO("main area read with 1 (correctable) error");
867 break;
868 case 2 << 2:
869 LOG_INFO("main area read with more than 1 (incorrectable) error");
870 return ERROR_NAND_OPERATION_FAILED;
871 break;
872 }
873 switch (ecc_status & 0x0003) {
874 case 1:
875 LOG_INFO("spare area read with 1 (correctable) error");
876 break;
877 case 2:
878 LOG_INFO("main area read with more than 1 (incorrectable) error");
879 return ERROR_NAND_OPERATION_FAILED;
880 break;
881 }
882 return ERROR_OK;
883 }
884
885 int ecc_status_v2(struct nand_device *nand)
886 {
887 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
888 struct target *target = nand->target;
889 uint16_t ecc_status;
890 uint8_t no_subpages;
891 uint8_t err;
892
893 no_subpages = nand->page_size >> 9;
894
895 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
896 do {
897 err = ecc_status & 0xF;
898 if (err > 4) {
899 LOG_INFO("UnCorrectable RS-ECC Error");
900 return ERROR_NAND_OPERATION_FAILED;
901 } else if (err > 0)
902 LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
903 ecc_status >>= 4;
904 } while (--no_subpages);
905 return ERROR_OK;
906 }
907
908 static int do_data_output(struct nand_device *nand)
909 {
910 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
911 struct target *target = nand->target;
912 int poll_result;
913 switch (mxc_nf_info->fin) {
914 case MXC_NF_FIN_DATAOUT:
915 /*
916 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
917 */
918 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
919 poll_result = poll_for_complete_op(nand, "data output");
920 if (poll_result != ERROR_OK)
921 return poll_result;
922
923 mxc_nf_info->fin = MXC_NF_FIN_NONE;
924 /*
925 * ECC stuff
926 */
927 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE &&
928 mxc_nf_info->flags.hw_ecc_enabled) {
929 int ecc_status;
930 if (nfc_is_v1())
931 ecc_status = ecc_status_v1(nand);
932 else
933 ecc_status = ecc_status_v2(nand);
934 if (ecc_status != ERROR_OK)
935 return ecc_status;
936 }
937 break;
938 case MXC_NF_FIN_NONE:
939 break;
940 }
941 return ERROR_OK;
942 }
943
944 struct nand_flash_controller mxc_nand_flash_controller = {
945 .name = "mxc",
946 .nand_device_command = &mxc_nand_device_command,
947 .commands = mxc_nand_command_handler,
948 .init = &mxc_init,
949 .reset = &mxc_reset,
950 .command = &mxc_command,
951 .address = &mxc_address,
952 .write_data = &mxc_write_data,
953 .read_data = &mxc_read_data,
954 .write_page = &mxc_write_page,
955 .read_page = &mxc_read_page,
956 .nand_ready = &mxc_nand_ready,
957 };
Andreas' development fork