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FLASH/NOR: Remove useless file stm32x.h
[openocd/andreasf.git] / src / flash / nor / stm32x.c
blob0edadfd2ae82e90b98eedcd24d8d2f5265b41120
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
31
32
33 /* stm32x register locations */
34
35 #define STM32_FLASH_ACR 0x40022000
36 #define STM32_FLASH_KEYR 0x40022004
37 #define STM32_FLASH_OPTKEYR 0x40022008
38 #define STM32_FLASH_SR 0x4002200C
39 #define STM32_FLASH_CR 0x40022010
40 #define STM32_FLASH_AR 0x40022014
41 #define STM32_FLASH_OBR 0x4002201C
42 #define STM32_FLASH_WRPR 0x40022020
43
44 /* option byte location */
45
46 #define STM32_OB_RDP 0x1FFFF800
47 #define STM32_OB_USER 0x1FFFF802
48 #define STM32_OB_DATA0 0x1FFFF804
49 #define STM32_OB_DATA1 0x1FFFF806
50 #define STM32_OB_WRP0 0x1FFFF808
51 #define STM32_OB_WRP1 0x1FFFF80A
52 #define STM32_OB_WRP2 0x1FFFF80C
53 #define STM32_OB_WRP3 0x1FFFF80E
54
55 /* FLASH_CR register bits */
56
57 #define FLASH_PG (1 << 0)
58 #define FLASH_PER (1 << 1)
59 #define FLASH_MER (1 << 2)
60 #define FLASH_OPTPG (1 << 4)
61 #define FLASH_OPTER (1 << 5)
62 #define FLASH_STRT (1 << 6)
63 #define FLASH_LOCK (1 << 7)
64 #define FLASH_OPTWRE (1 << 9)
65
66 /* FLASH_SR register bits */
67
68 #define FLASH_BSY (1 << 0)
69 #define FLASH_PGERR (1 << 2)
70 #define FLASH_WRPRTERR (1 << 4)
71 #define FLASH_EOP (1 << 5)
72
73 /* STM32_FLASH_OBR bit definitions (reading) */
74
75 #define OPT_ERROR 0
76 #define OPT_READOUT 1
77 #define OPT_RDWDGSW 2
78 #define OPT_RDRSTSTOP 3
79 #define OPT_RDRSTSTDBY 4
80
81 /* register unlock keys */
82
83 #define KEY1 0x45670123
84 #define KEY2 0xCDEF89AB
85
86
87 struct stm32x_options
88 {
89 uint16_t RDP;
90 uint16_t user_options;
91 uint16_t protection[4];
92 };
93
94 struct stm32x_flash_bank
95 {
96 struct stm32x_options option_bytes;
97 struct working_area *write_algorithm;
98 int ppage_size;
99 int probed;
100 };
101
102 struct stm32x_mem_layout {
103 uint32_t sector_start;
104 uint32_t sector_size;
105 };
106
107 static int stm32x_mass_erase(struct flash_bank *bank);
108
109 /* flash bank stm32x <base> <size> 0 0 <target#>
110 */
111 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
112 {
113 struct stm32x_flash_bank *stm32x_info;
114
115 if (CMD_ARGC < 6)
116 {
117 LOG_WARNING("incomplete flash_bank stm32x configuration");
118 return ERROR_FLASH_BANK_INVALID;
119 }
120
121 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
122 bank->driver_priv = stm32x_info;
123
124 stm32x_info->write_algorithm = NULL;
125 stm32x_info->probed = 0;
126
127 return ERROR_OK;
128 }
129
130 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
131 {
132 struct target *target = bank->target;
133 return target_read_u32(target, STM32_FLASH_SR, status);
134 }
135
136 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
137 {
138 struct target *target = bank->target;
139 uint32_t status;
140 int retval = ERROR_OK;
141
142 /* wait for busy to clear */
143 for (;;)
144 {
145 retval = stm32x_get_flash_status(bank, &status);
146 if (retval != ERROR_OK)
147 return retval;
148 LOG_DEBUG("status: 0x%" PRIx32 "", status);
149 if ((status & FLASH_BSY) == 0)
150 break;
151 if (timeout-- <= 0)
152 {
153 LOG_ERROR("timed out waiting for flash");
154 return ERROR_FAIL;
155 }
156 alive_sleep(1);
157 }
158
159 if (status & FLASH_WRPRTERR)
160 {
161 LOG_ERROR("stm32x device protected");
162 retval = ERROR_FAIL;
163 }
164
165 if (status & FLASH_PGERR)
166 {
167 LOG_ERROR("stm32x device programming failed");
168 retval = ERROR_FAIL;
169 }
170
171 /* Clear but report errors */
172 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
173 {
174 /* If this operation fails, we ignore it and report the original
175 * retval
176 */
177 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
178 }
179 return retval;
180 }
181
182 static int stm32x_read_options(struct flash_bank *bank)
183 {
184 uint32_t optiondata;
185 struct stm32x_flash_bank *stm32x_info = NULL;
186 struct target *target = bank->target;
187
188 stm32x_info = bank->driver_priv;
189
190 /* read current option bytes */
191 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
192 if (retval != ERROR_OK)
193 return retval;
194
195 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
196 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
197
198 if (optiondata & (1 << OPT_READOUT))
199 LOG_INFO("Device Security Bit Set");
200
201 /* each bit refers to a 4bank protection */
202 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
203 if (retval != ERROR_OK)
204 return retval;
205
206 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
207 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
208 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
209 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
210
211 return ERROR_OK;
212 }
213
214 static int stm32x_erase_options(struct flash_bank *bank)
215 {
216 struct stm32x_flash_bank *stm32x_info = NULL;
217 struct target *target = bank->target;
218
219 stm32x_info = bank->driver_priv;
220
221 /* read current options */
222 stm32x_read_options(bank);
223
224 /* unlock flash registers */
225 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
226 if (retval != ERROR_OK)
227 return retval;
228
229 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* unlock option flash registers */
234 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
235 if (retval != ERROR_OK)
236 return retval;
237 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
238 if (retval != ERROR_OK)
239 return retval;
240
241 /* erase option bytes */
242 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
243 if (retval != ERROR_OK)
244 return retval;
245 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
246 if (retval != ERROR_OK)
247 return retval;
248
249 retval = stm32x_wait_status_busy(bank, 10);
250 if (retval != ERROR_OK)
251 return retval;
252
253 /* clear readout protection and complementary option bytes
254 * this will also force a device unlock if set */
255 stm32x_info->option_bytes.RDP = 0x5AA5;
256
257 return ERROR_OK;
258 }
259
260 static int stm32x_write_options(struct flash_bank *bank)
261 {
262 struct stm32x_flash_bank *stm32x_info = NULL;
263 struct target *target = bank->target;
264
265 stm32x_info = bank->driver_priv;
266
267 /* unlock flash registers */
268 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
269 if (retval != ERROR_OK)
270 return retval;
271 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
272 if (retval != ERROR_OK)
273 return retval;
274
275 /* unlock option flash registers */
276 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
277 if (retval != ERROR_OK)
278 return retval;
279 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
280 if (retval != ERROR_OK)
281 return retval;
282
283 /* program option bytes */
284 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
285 if (retval != ERROR_OK)
286 return retval;
287
288 /* write user option byte */
289 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
290 if (retval != ERROR_OK)
291 return retval;
292
293 retval = stm32x_wait_status_busy(bank, 10);
294 if (retval != ERROR_OK)
295 return retval;
296
297 /* write protection byte 1 */
298 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
299 if (retval != ERROR_OK)
300 return retval;
301
302 retval = stm32x_wait_status_busy(bank, 10);
303 if (retval != ERROR_OK)
304 return retval;
305
306 /* write protection byte 2 */
307 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
308 if (retval != ERROR_OK)
309 return retval;
310
311 retval = stm32x_wait_status_busy(bank, 10);
312 if (retval != ERROR_OK)
313 return retval;
314
315 /* write protection byte 3 */
316 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
317 if (retval != ERROR_OK)
318 return retval;
319
320 retval = stm32x_wait_status_busy(bank, 10);
321 if (retval != ERROR_OK)
322 return retval;
323
324 /* write protection byte 4 */
325 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
326 if (retval != ERROR_OK)
327 return retval;
328
329 retval = stm32x_wait_status_busy(bank, 10);
330 if (retval != ERROR_OK)
331 return retval;
332
333 /* write readout protection bit */
334 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
335 if (retval != ERROR_OK)
336 return retval;
337
338 retval = stm32x_wait_status_busy(bank, 10);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
343 if (retval != ERROR_OK)
344 return retval;
345
346 return ERROR_OK;
347 }
348
349 static int stm32x_protect_check(struct flash_bank *bank)
350 {
351 struct target *target = bank->target;
352 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
353
354 uint32_t protection;
355 int i, s;
356 int num_bits;
357 int set;
358
359 if (target->state != TARGET_HALTED)
360 {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 /* medium density - each bit refers to a 4bank protection
366 * high density - each bit refers to a 2bank protection */
367 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
368 if (retval != ERROR_OK)
369 return retval;
370
371 /* medium density - each protection bit is for 4 * 1K pages
372 * high density - each protection bit is for 2 * 2K pages */
373 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
374
375 if (stm32x_info->ppage_size == 2)
376 {
377 /* high density flash/connectivity line protection */
378
379 set = 1;
380
381 if (protection & (1 << 31))
382 set = 0;
383
384 /* bit 31 controls sector 62 - 255 protection for high density
385 * bit 31 controls sector 62 - 127 protection for connectivity line */
386 for (s = 62; s < bank->num_sectors; s++)
387 {
388 bank->sectors[s].is_protected = set;
389 }
390
391 if (bank->num_sectors > 61)
392 num_bits = 31;
393
394 for (i = 0; i < num_bits; i++)
395 {
396 set = 1;
397
398 if (protection & (1 << i))
399 set = 0;
400
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403 }
404 }
405 else
406 {
407 /* low/medium density flash protection */
408 for (i = 0; i < num_bits; i++)
409 {
410 set = 1;
411
412 if (protection & (1 << i))
413 set = 0;
414
415 for (s = 0; s < stm32x_info->ppage_size; s++)
416 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
417 }
418 }
419
420 return ERROR_OK;
421 }
422
423 static int stm32x_erase(struct flash_bank *bank, int first, int last)
424 {
425 struct target *target = bank->target;
426 int i;
427
428 if (bank->target->state != TARGET_HALTED)
429 {
430 LOG_ERROR("Target not halted");
431 return ERROR_TARGET_NOT_HALTED;
432 }
433
434 if ((first == 0) && (last == (bank->num_sectors - 1)))
435 {
436 return stm32x_mass_erase(bank);
437 }
438
439 /* unlock flash registers */
440 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
441 if (retval != ERROR_OK)
442 return retval;
443 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
444 if (retval != ERROR_OK)
445 return retval;
446
447 for (i = first; i <= last; i++)
448 {
449 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
453 if (retval != ERROR_OK)
454 return retval;
455 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
456 if (retval != ERROR_OK)
457 return retval;
458
459 retval = stm32x_wait_status_busy(bank, 100);
460 if (retval != ERROR_OK)
461 return retval;
462
463 bank->sectors[i].is_erased = 1;
464 }
465
466 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
467 if (retval != ERROR_OK)
468 return retval;
469
470 return ERROR_OK;
471 }
472
473 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
474 {
475 struct stm32x_flash_bank *stm32x_info = NULL;
476 struct target *target = bank->target;
477 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
478 int i, reg, bit;
479 int status;
480 uint32_t protection;
481
482 stm32x_info = bank->driver_priv;
483
484 if (target->state != TARGET_HALTED)
485 {
486 LOG_ERROR("Target not halted");
487 return ERROR_TARGET_NOT_HALTED;
488 }
489
490 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
491 (last + 1) % stm32x_info->ppage_size))
492 {
493 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
494 stm32x_info->ppage_size);
495 return ERROR_FLASH_SECTOR_INVALID;
496 }
497
498 /* medium density - each bit refers to a 4bank protection
499 * high density - each bit refers to a 2bank protection */
500 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
501 if (retval != ERROR_OK)
502 return retval;
503
504 prot_reg[0] = (uint16_t)protection;
505 prot_reg[1] = (uint16_t)(protection >> 8);
506 prot_reg[2] = (uint16_t)(protection >> 16);
507 prot_reg[3] = (uint16_t)(protection >> 24);
508
509 if (stm32x_info->ppage_size == 2)
510 {
511 /* high density flash */
512
513 /* bit 7 controls sector 62 - 255 protection */
514 if (last > 61)
515 {
516 if (set)
517 prot_reg[3] &= ~(1 << 7);
518 else
519 prot_reg[3] |= (1 << 7);
520 }
521
522 if (first > 61)
523 first = 62;
524 if (last > 61)
525 last = 61;
526
527 for (i = first; i <= last; i++)
528 {
529 reg = (i / stm32x_info->ppage_size) / 8;
530 bit = (i / stm32x_info->ppage_size) - (reg * 8);
531
532 if (set)
533 prot_reg[reg] &= ~(1 << bit);
534 else
535 prot_reg[reg] |= (1 << bit);
536 }
537 }
538 else
539 {
540 /* medium density flash */
541 for (i = first; i <= last; i++)
542 {
543 reg = (i / stm32x_info->ppage_size) / 8;
544 bit = (i / stm32x_info->ppage_size) - (reg * 8);
545
546 if (set)
547 prot_reg[reg] &= ~(1 << bit);
548 else
549 prot_reg[reg] |= (1 << bit);
550 }
551 }
552
553 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
554 return status;
555
556 stm32x_info->option_bytes.protection[0] = prot_reg[0];
557 stm32x_info->option_bytes.protection[1] = prot_reg[1];
558 stm32x_info->option_bytes.protection[2] = prot_reg[2];
559 stm32x_info->option_bytes.protection[3] = prot_reg[3];
560
561 return stm32x_write_options(bank);
562 }
563
564 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
565 uint32_t offset, uint32_t count)
566 {
567 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
568 struct target *target = bank->target;
569 uint32_t buffer_size = 16384;
570 struct working_area *source;
571 uint32_t address = bank->base + offset;
572 struct reg_param reg_params[4];
573 struct armv7m_algorithm armv7m_info;
574 int retval = ERROR_OK;
575
576 /* see contib/loaders/flash/stm32x.s for src */
577
578 static const uint8_t stm32x_flash_write_code[] = {
579 /* #define STM32_FLASH_CR_OFFSET 0x10 */
580 /* #define STM32_FLASH_SR_OFFSET 0x0C */
581 /* write: */
582 0xdf, 0xf8, 0x20, 0x40, /* ldr r4, STM32_FLASH_BASE */
583 /* write_half_word: */
584 0x01, 0x23, /* movs r3, #0x01 */
585 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
586 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
587 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
588 /* busy: */
589 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
590 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
591 0xfb, 0xd0, /* beq busy */
592 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
593 0x01, 0xd1, /* bne exit */
594 0x01, 0x3a, /* subs r2, r2, #0x01 */
595 0xf0, 0xd1, /* bne write_half_word */
596 /* exit: */
597 0x00, 0xbe, /* bkpt #0x00 */
598 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
599 };
600
601 /* flash write code */
602 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
603 &stm32x_info->write_algorithm) != ERROR_OK)
604 {
605 LOG_WARNING("no working area available, can't do block memory writes");
606 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
607 };
608
609 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
610 sizeof(stm32x_flash_write_code),
611 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
612 return retval;
613
614 /* memory buffer */
615 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
616 {
617 buffer_size /= 2;
618 if (buffer_size <= 256)
619 {
620 /* if we already allocated the writing code, but failed to get a
621 * buffer, free the algorithm */
622 if (stm32x_info->write_algorithm)
623 target_free_working_area(target, stm32x_info->write_algorithm);
624
625 LOG_WARNING("no large enough working area available, can't do block memory writes");
626 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
627 }
628 };
629
630 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
631 armv7m_info.core_mode = ARMV7M_MODE_ANY;
632
633 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
634 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
635 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
636 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
637
638 while (count > 0)
639 {
640 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
641 (buffer_size / 2) : count;
642
643 if ((retval = target_write_buffer(target, source->address,
644 thisrun_count * 2, buffer)) != ERROR_OK)
645 break;
646
647 buf_set_u32(reg_params[0].value, 0, 32, source->address);
648 buf_set_u32(reg_params[1].value, 0, 32, address);
649 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
650
651 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
652 stm32x_info->write_algorithm->address,
653 0,
654 10000, &armv7m_info)) != ERROR_OK)
655 {
656 LOG_ERROR("error executing stm32x flash write algorithm");
657 break;
658 }
659
660 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
661 {
662 LOG_ERROR("flash memory not erased before writing");
663 /* Clear but report errors */
664 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
665 retval = ERROR_FAIL;
666 break;
667 }
668
669 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
670 {
671 LOG_ERROR("flash memory write protected");
672 /* Clear but report errors */
673 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
674 retval = ERROR_FAIL;
675 break;
676 }
677
678 buffer += thisrun_count * 2;
679 address += thisrun_count * 2;
680 count -= thisrun_count;
681 }
682
683 target_free_working_area(target, source);
684 target_free_working_area(target, stm32x_info->write_algorithm);
685
686 destroy_reg_param(&reg_params[0]);
687 destroy_reg_param(&reg_params[1]);
688 destroy_reg_param(&reg_params[2]);
689 destroy_reg_param(&reg_params[3]);
690
691 return retval;
692 }
693
694 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
695 uint32_t offset, uint32_t count)
696 {
697 struct target *target = bank->target;
698 uint32_t words_remaining = (count / 2);
699 uint32_t bytes_remaining = (count & 0x00000001);
700 uint32_t address = bank->base + offset;
701 uint32_t bytes_written = 0;
702 int retval;
703
704 if (bank->target->state != TARGET_HALTED)
705 {
706 LOG_ERROR("Target not halted");
707 return ERROR_TARGET_NOT_HALTED;
708 }
709
710 if (offset & 0x1)
711 {
712 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
713 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
714 }
715
716 /* unlock flash registers */
717 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
718 if (retval != ERROR_OK)
719 return retval;
720 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
721 if (retval != ERROR_OK)
722 return retval;
723
724 /* multiple half words (2-byte) to be programmed? */
725 if (words_remaining > 0)
726 {
727 /* try using a block write */
728 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
729 {
730 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
731 {
732 /* if block write failed (no sufficient working area),
733 * we use normal (slow) single dword accesses */
734 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
735 }
736 }
737 else
738 {
739 buffer += words_remaining * 2;
740 address += words_remaining * 2;
741 words_remaining = 0;
742 }
743 }
744
745 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
746 return retval;
747
748 while (words_remaining > 0)
749 {
750 uint16_t value;
751 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
752
753 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
754 if (retval != ERROR_OK)
755 return retval;
756 retval = target_write_u16(target, address, value);
757 if (retval != ERROR_OK)
758 return retval;
759
760 retval = stm32x_wait_status_busy(bank, 5);
761 if (retval != ERROR_OK)
762 return retval;
763
764 bytes_written += 2;
765 words_remaining--;
766 address += 2;
767 }
768
769 if (bytes_remaining)
770 {
771 uint16_t value = 0xffff;
772 memcpy(&value, buffer + bytes_written, bytes_remaining);
773
774 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
775 if (retval != ERROR_OK)
776 return retval;
777 retval = target_write_u16(target, address, value);
778 if (retval != ERROR_OK)
779 return retval;
780
781 retval = stm32x_wait_status_busy(bank, 5);
782 if (retval != ERROR_OK)
783 return retval;
784 }
785
786 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
787 }
788
789 static int stm32x_probe(struct flash_bank *bank)
790 {
791 struct target *target = bank->target;
792 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
793 int i;
794 uint16_t num_pages;
795 uint32_t device_id;
796 int page_size;
797
798 stm32x_info->probed = 0;
799
800 /* read stm32 device id register */
801 int retval = target_read_u32(target, 0xE0042000, &device_id);
802 if (retval != ERROR_OK)
803 return retval;
804 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
805
806 /* get flash size from target. */
807 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
808 if (retval != ERROR_OK)
809 {
810 LOG_WARNING("failed reading flash size, default to max target family");
811 /* failed reading flash size, default to max target family */
812 num_pages = 0xffff;
813 }
814
815 if ((device_id & 0x7ff) == 0x410)
816 {
817 /* medium density - we have 1k pages
818 * 4 pages for a protection area */
819 page_size = 1024;
820 stm32x_info->ppage_size = 4;
821
822 /* check for early silicon */
823 if (num_pages == 0xffff)
824 {
825 /* number of sectors incorrect on revA */
826 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
827 num_pages = 128;
828 }
829 }
830 else if ((device_id & 0x7ff) == 0x412)
831 {
832 /* low density - we have 1k pages
833 * 4 pages for a protection area */
834 page_size = 1024;
835 stm32x_info->ppage_size = 4;
836
837 /* check for early silicon */
838 if (num_pages == 0xffff)
839 {
840 /* number of sectors incorrect on revA */
841 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
842 num_pages = 32;
843 }
844 }
845 else if ((device_id & 0x7ff) == 0x414)
846 {
847 /* high density - we have 2k pages
848 * 2 pages for a protection area */
849 page_size = 2048;
850 stm32x_info->ppage_size = 2;
851
852 /* check for early silicon */
853 if (num_pages == 0xffff)
854 {
855 /* number of sectors incorrect on revZ */
856 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
857 num_pages = 512;
858 }
859 }
860 else if ((device_id & 0x7ff) == 0x418)
861 {
862 /* connectivity line density - we have 2k pages
863 * 2 pages for a protection area */
864 page_size = 2048;
865 stm32x_info->ppage_size = 2;
866
867 /* check for early silicon */
868 if (num_pages == 0xffff)
869 {
870 /* number of sectors incorrect on revZ */
871 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
872 num_pages = 256;
873 }
874 }
875 else if ((device_id & 0x7ff) == 0x420)
876 {
877 /* value line density - we have 1k pages
878 * 4 pages for a protection area */
879 page_size = 1024;
880 stm32x_info->ppage_size = 4;
881
882 /* check for early silicon */
883 if (num_pages == 0xffff)
884 {
885 /* number of sectors may be incorrrect on early silicon */
886 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
887 num_pages = 128;
888 }
889 }
890 else
891 {
892 LOG_WARNING("Cannot identify target as a STM32 family.");
893 return ERROR_FAIL;
894 }
895
896 LOG_INFO("flash size = %dkbytes", num_pages);
897
898 /* calculate numbers of pages */
899 num_pages /= (page_size / 1024);
900
901 if (bank->sectors)
902 {
903 free(bank->sectors);
904 bank->sectors = NULL;
905 }
906
907 bank->base = 0x08000000;
908 bank->size = (num_pages * page_size);
909 bank->num_sectors = num_pages;
910 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
911
912 for (i = 0; i < num_pages; i++)
913 {
914 bank->sectors[i].offset = i * page_size;
915 bank->sectors[i].size = page_size;
916 bank->sectors[i].is_erased = -1;
917 bank->sectors[i].is_protected = 1;
918 }
919
920 stm32x_info->probed = 1;
921
922 return ERROR_OK;
923 }
924
925 static int stm32x_auto_probe(struct flash_bank *bank)
926 {
927 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
928 if (stm32x_info->probed)
929 return ERROR_OK;
930 return stm32x_probe(bank);
931 }
932
933 #if 0
934 COMMAND_HANDLER(stm32x_handle_part_id_command)
935 {
936 return ERROR_OK;
937 }
938 #endif
939
940 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
941 {
942 struct target *target = bank->target;
943 uint32_t device_id;
944 int printed;
945
946 /* read stm32 device id register */
947 int retval = target_read_u32(target, 0xE0042000, &device_id);
948 if (retval != ERROR_OK)
949 return retval;
950
951 if ((device_id & 0x7ff) == 0x410)
952 {
953 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
954 buf += printed;
955 buf_size -= printed;
956
957 switch (device_id >> 16)
958 {
959 case 0x0000:
960 snprintf(buf, buf_size, "A");
961 break;
962
963 case 0x2000:
964 snprintf(buf, buf_size, "B");
965 break;
966
967 case 0x2001:
968 snprintf(buf, buf_size, "Z");
969 break;
970
971 case 0x2003:
972 snprintf(buf, buf_size, "Y");
973 break;
974
975 default:
976 snprintf(buf, buf_size, "unknown");
977 break;
978 }
979 }
980 else if ((device_id & 0x7ff) == 0x412)
981 {
982 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
983 buf += printed;
984 buf_size -= printed;
985
986 switch (device_id >> 16)
987 {
988 case 0x1000:
989 snprintf(buf, buf_size, "A");
990 break;
991
992 default:
993 snprintf(buf, buf_size, "unknown");
994 break;
995 }
996 }
997 else if ((device_id & 0x7ff) == 0x414)
998 {
999 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1000 buf += printed;
1001 buf_size -= printed;
1002
1003 switch (device_id >> 16)
1004 {
1005 case 0x1000:
1006 snprintf(buf, buf_size, "A");
1007 break;
1008
1009 case 0x1001:
1010 snprintf(buf, buf_size, "Z");
1011 break;
1012
1013 default:
1014 snprintf(buf, buf_size, "unknown");
1015 break;
1016 }
1017 }
1018 else if ((device_id & 0x7ff) == 0x418)
1019 {
1020 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1021 buf += printed;
1022 buf_size -= printed;
1023
1024 switch (device_id >> 16)
1025 {
1026 case 0x1000:
1027 snprintf(buf, buf_size, "A");
1028 break;
1029
1030 case 0x1001:
1031 snprintf(buf, buf_size, "Z");
1032 break;
1033
1034 default:
1035 snprintf(buf, buf_size, "unknown");
1036 break;
1037 }
1038 }
1039 else if ((device_id & 0x7ff) == 0x420)
1040 {
1041 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1042 buf += printed;
1043 buf_size -= printed;
1044
1045 switch (device_id >> 16)
1046 {
1047 case 0x1000:
1048 snprintf(buf, buf_size, "A");
1049 break;
1050
1051 case 0x1001:
1052 snprintf(buf, buf_size, "Z");
1053 break;
1054
1055 default:
1056 snprintf(buf, buf_size, "unknown");
1057 break;
1058 }
1059 }
1060 else
1061 {
1062 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1063 return ERROR_FAIL;
1064 }
1065
1066 return ERROR_OK;
1067 }
1068
1069 COMMAND_HANDLER(stm32x_handle_lock_command)
1070 {
1071 struct target *target = NULL;
1072 struct stm32x_flash_bank *stm32x_info = NULL;
1073
1074 if (CMD_ARGC < 1)
1075 {
1076 command_print(CMD_CTX, "stm32x lock <bank>");
1077 return ERROR_OK;
1078 }
1079
1080 struct flash_bank *bank;
1081 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1082 if (ERROR_OK != retval)
1083 return retval;
1084
1085 stm32x_info = bank->driver_priv;
1086
1087 target = bank->target;
1088
1089 if (target->state != TARGET_HALTED)
1090 {
1091 LOG_ERROR("Target not halted");
1092 return ERROR_TARGET_NOT_HALTED;
1093 }
1094
1095 if (stm32x_erase_options(bank) != ERROR_OK)
1096 {
1097 command_print(CMD_CTX, "stm32x failed to erase options");
1098 return ERROR_OK;
1099 }
1100
1101 /* set readout protection */
1102 stm32x_info->option_bytes.RDP = 0;
1103
1104 if (stm32x_write_options(bank) != ERROR_OK)
1105 {
1106 command_print(CMD_CTX, "stm32x failed to lock device");
1107 return ERROR_OK;
1108 }
1109
1110 command_print(CMD_CTX, "stm32x locked");
1111
1112 return ERROR_OK;
1113 }
1114
1115 COMMAND_HANDLER(stm32x_handle_unlock_command)
1116 {
1117 struct target *target = NULL;
1118 struct stm32x_flash_bank *stm32x_info = NULL;
1119
1120 if (CMD_ARGC < 1)
1121 {
1122 command_print(CMD_CTX, "stm32x unlock <bank>");
1123 return ERROR_OK;
1124 }
1125
1126 struct flash_bank *bank;
1127 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1128 if (ERROR_OK != retval)
1129 return retval;
1130
1131 stm32x_info = bank->driver_priv;
1132
1133 target = bank->target;
1134
1135 if (target->state != TARGET_HALTED)
1136 {
1137 LOG_ERROR("Target not halted");
1138 return ERROR_TARGET_NOT_HALTED;
1139 }
1140
1141 if (stm32x_erase_options(bank) != ERROR_OK)
1142 {
1143 command_print(CMD_CTX, "stm32x failed to unlock device");
1144 return ERROR_OK;
1145 }
1146
1147 if (stm32x_write_options(bank) != ERROR_OK)
1148 {
1149 command_print(CMD_CTX, "stm32x failed to lock device");
1150 return ERROR_OK;
1151 }
1152
1153 command_print(CMD_CTX, "stm32x unlocked.\n"
1154 "INFO: a reset or power cycle is required "
1155 "for the new settings to take effect.");
1156
1157 return ERROR_OK;
1158 }
1159
1160 COMMAND_HANDLER(stm32x_handle_options_read_command)
1161 {
1162 uint32_t optionbyte;
1163 struct target *target = NULL;
1164 struct stm32x_flash_bank *stm32x_info = NULL;
1165
1166 if (CMD_ARGC < 1)
1167 {
1168 command_print(CMD_CTX, "stm32x options_read <bank>");
1169 return ERROR_OK;
1170 }
1171
1172 struct flash_bank *bank;
1173 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1174 if (ERROR_OK != retval)
1175 return retval;
1176
1177 stm32x_info = bank->driver_priv;
1178
1179 target = bank->target;
1180
1181 if (target->state != TARGET_HALTED)
1182 {
1183 LOG_ERROR("Target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1185 }
1186
1187 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1188 if (retval != ERROR_OK)
1189 return retval;
1190 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1191
1192 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1193 command_print(CMD_CTX, "Option Byte Complement Error");
1194
1195 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1196 command_print(CMD_CTX, "Readout Protection On");
1197 else
1198 command_print(CMD_CTX, "Readout Protection Off");
1199
1200 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1201 command_print(CMD_CTX, "Software Watchdog");
1202 else
1203 command_print(CMD_CTX, "Hardware Watchdog");
1204
1205 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1206 command_print(CMD_CTX, "Stop: No reset generated");
1207 else
1208 command_print(CMD_CTX, "Stop: Reset generated");
1209
1210 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1211 command_print(CMD_CTX, "Standby: No reset generated");
1212 else
1213 command_print(CMD_CTX, "Standby: Reset generated");
1214
1215 return ERROR_OK;
1216 }
1217
1218 COMMAND_HANDLER(stm32x_handle_options_write_command)
1219 {
1220 struct target *target = NULL;
1221 struct stm32x_flash_bank *stm32x_info = NULL;
1222 uint16_t optionbyte = 0xF8;
1223
1224 if (CMD_ARGC < 4)
1225 {
1226 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1227 return ERROR_OK;
1228 }
1229
1230 struct flash_bank *bank;
1231 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1232 if (ERROR_OK != retval)
1233 return retval;
1234
1235 stm32x_info = bank->driver_priv;
1236
1237 target = bank->target;
1238
1239 if (target->state != TARGET_HALTED)
1240 {
1241 LOG_ERROR("Target not halted");
1242 return ERROR_TARGET_NOT_HALTED;
1243 }
1244
1245 /* REVISIT: ignores some options which we will display...
1246 * and doesn't insist on the specified syntax.
1247 */
1248
1249 /* OPT_RDWDGSW */
1250 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1251 {
1252 optionbyte |= (1 << 0);
1253 }
1254 else /* REVISIT must be "HWWDG" then ... */
1255 {
1256 optionbyte &= ~(1 << 0);
1257 }
1258
1259 /* OPT_RDRSTSTDBY */
1260 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1261 {
1262 optionbyte |= (1 << 1);
1263 }
1264 else /* REVISIT must be "RSTSTNDBY" then ... */
1265 {
1266 optionbyte &= ~(1 << 1);
1267 }
1268
1269 /* OPT_RDRSTSTOP */
1270 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1271 {
1272 optionbyte |= (1 << 2);
1273 }
1274 else /* REVISIT must be "RSTSTOP" then ... */
1275 {
1276 optionbyte &= ~(1 << 2);
1277 }
1278
1279 if (stm32x_erase_options(bank) != ERROR_OK)
1280 {
1281 command_print(CMD_CTX, "stm32x failed to erase options");
1282 return ERROR_OK;
1283 }
1284
1285 stm32x_info->option_bytes.user_options = optionbyte;
1286
1287 if (stm32x_write_options(bank) != ERROR_OK)
1288 {
1289 command_print(CMD_CTX, "stm32x failed to write options");
1290 return ERROR_OK;
1291 }
1292
1293 command_print(CMD_CTX, "stm32x write options complete.\n"
1294 "INFO: a reset or power cycle is required "
1295 "for the new settings to take effect.");
1296
1297 return ERROR_OK;
1298 }
1299
1300 static int stm32x_mass_erase(struct flash_bank *bank)
1301 {
1302 struct target *target = bank->target;
1303
1304 if (target->state != TARGET_HALTED)
1305 {
1306 LOG_ERROR("Target not halted");
1307 return ERROR_TARGET_NOT_HALTED;
1308 }
1309
1310 /* unlock option flash registers */
1311 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1312 if (retval != ERROR_OK)
1313 return retval;
1314 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1315 if (retval != ERROR_OK)
1316 return retval;
1317
1318 /* mass erase flash memory */
1319 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1320 if (retval != ERROR_OK)
1321 return retval;
1322 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1323 if (retval != ERROR_OK)
1324 return retval;
1325
1326 retval = stm32x_wait_status_busy(bank, 100);
1327 if (retval != ERROR_OK)
1328 return retval;
1329
1330 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1331 if (retval != ERROR_OK)
1332 return retval;
1333
1334 return ERROR_OK;
1335 }
1336
1337 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1338 {
1339 int i;
1340
1341 if (CMD_ARGC < 1)
1342 {
1343 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1344 return ERROR_OK;
1345 }
1346
1347 struct flash_bank *bank;
1348 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1349 if (ERROR_OK != retval)
1350 return retval;
1351
1352 retval = stm32x_mass_erase(bank);
1353 if (retval == ERROR_OK)
1354 {
1355 /* set all sectors as erased */
1356 for (i = 0; i < bank->num_sectors; i++)
1357 {
1358 bank->sectors[i].is_erased = 1;
1359 }
1360
1361 command_print(CMD_CTX, "stm32x mass erase complete");
1362 }
1363 else
1364 {
1365 command_print(CMD_CTX, "stm32x mass erase failed");
1366 }
1367
1368 return retval;
1369 }
1370
1371 static const struct command_registration stm32x_exec_command_handlers[] = {
1372 {
1373 .name = "lock",
1374 .handler = stm32x_handle_lock_command,
1375 .mode = COMMAND_EXEC,
1376 .usage = "bank_id",
1377 .help = "Lock entire flash device.",
1378 },
1379 {
1380 .name = "unlock",
1381 .handler = stm32x_handle_unlock_command,
1382 .mode = COMMAND_EXEC,
1383 .usage = "bank_id",
1384 .help = "Unlock entire protected flash device.",
1385 },
1386 {
1387 .name = "mass_erase",
1388 .handler = stm32x_handle_mass_erase_command,
1389 .mode = COMMAND_EXEC,
1390 .usage = "bank_id",
1391 .help = "Erase entire flash device.",
1392 },
1393 {
1394 .name = "options_read",
1395 .handler = stm32x_handle_options_read_command,
1396 .mode = COMMAND_EXEC,
1397 .usage = "bank_id",
1398 .help = "Read and display device option byte.",
1399 },
1400 {
1401 .name = "options_write",
1402 .handler = stm32x_handle_options_write_command,
1403 .mode = COMMAND_EXEC,
1404 .usage = "bank_id ('SWWDG'|'HWWDG') "
1405 "('RSTSTNDBY'|'NORSTSTNDBY') "
1406 "('RSTSTOP'|'NORSTSTOP')",
1407 .help = "Replace bits in device option byte.",
1408 },
1409 COMMAND_REGISTRATION_DONE
1410 };
1411
1412 static const struct command_registration stm32x_command_handlers[] = {
1413 {
1414 .name = "stm32x",
1415 .mode = COMMAND_ANY,
1416 .help = "stm32x flash command group",
1417 .chain = stm32x_exec_command_handlers,
1418 },
1419 COMMAND_REGISTRATION_DONE
1420 };
1421
1422 struct flash_driver stm32x_flash = {
1423 .name = "stm32x",
1424 .commands = stm32x_command_handlers,
1425 .flash_bank_command = stm32x_flash_bank_command,
1426 .erase = stm32x_erase,
1427 .protect = stm32x_protect,
1428 .write = stm32x_write,
1429 .read = default_flash_read,
1430 .probe = stm32x_probe,
1431 .auto_probe = stm32x_auto_probe,
1432 .erase_check = default_flash_mem_blank_check,
1433 .protect_check = stm32x_protect_check,
1434 .info = get_stm32x_info,
1435 };
Andreas' development fork