target/arm_adi_v5: fix sync CSW cache on apreg write
[openocd.git] / tcl / target / marvell / 
treef61b3c395194bc7a893e83457de7a486f23bd8c4
drwxr-xr-x   ..
-rw-r--r-- 77 88f3710.cfg
-rw-r--r-- 77 88f3720.cfg
-rw-r--r-- 2018 88f37x0.cfg