src/target/quark_x10xx.c

   1 /*
   2  * Copyright(c) 2013-2016 Intel Corporation.
   3  *
   4  * Adrian Burns (adrian.burns@intel.com)
   5  * Thomas Faust (thomas.faust@intel.com)
   6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
   7  * Julien Carreno (julien.carreno@intel.com)
   8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  23  *
  24  * Contact Information:
  25  * Intel Corporation
  26  */
  27
  28 /*
  29  * @file
  30  * Debugger for Intel Quark SoC X1000
  31  * Intel Quark X10xx is the first product in the Quark family of SoCs.
  32  * It is an IA-32 (Pentium x86 ISA) compatible SoC. The core CPU in the
  33  * X10xx is codenamed Lakemont. Lakemont version 1 (LMT1) is used in X10xx.
  34  * The CPU TAP (Lakemont TAP) is used for software debug and the CLTAP is
  35  * used for SoC level operations.
  36  * Useful docs are here: https://communities.intel.com/community/makers/documentation
  37  * Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
  38  * Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
  39  * Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
  40  *
  41  * This file implements any Quark SoC specific features such as resetbreak (TODO)
  42  */
  43
  44 #ifdef HAVE_CONFIG_H
  45 #include "config.h"
  46 #endif
  47
  48 #include <helper/log.h>
  49
  50 #include "target.h"
  51 #include "target_type.h"
  52 #include "lakemont.h"
  53 #include "x86_32_common.h"
  54
  55 int quark_x10xx_target_create(struct target *t, Jim_Interp *interp)
  56 {
  57         struct x86_32_common *x86_32 = calloc(1, sizeof(struct x86_32_common));
  58         if (x86_32 == NULL) {
  59                 LOG_ERROR("%s out of memory", __func__);
  60                 return ERROR_FAIL;
  61         }
  62         x86_32_common_init_arch_info(t, x86_32);
  63         lakemont_init_arch_info(t, x86_32);
  64         x86_32->core_type = LMT1;
  65         return ERROR_OK;
  66 }
  67
  68 int quark_x10xx_init_target(struct command_context *cmd_ctx, struct target *t)
  69 {
  70         return lakemont_init_target(cmd_ctx, t);
  71 }
  72
  73 struct target_type quark_x10xx_target = {
  74         .name = "quark_x10xx",
  75         /* Quark X1000 SoC */
  76         .target_create = quark_x10xx_target_create,
  77         .init_target = quark_x10xx_init_target,
  78         /* lakemont probemode specific code */
  79         .poll = lakemont_poll,
  80         .arch_state = lakemont_arch_state,
  81         .halt = lakemont_halt,
  82         .resume = lakemont_resume,
  83         .step = lakemont_step,
  84         .assert_reset = lakemont_reset_assert,
  85         .deassert_reset = lakemont_reset_deassert,
  86         /* common x86 code */
  87         .commands = x86_32_command_handlers,
  88         .get_gdb_reg_list = x86_32_get_gdb_reg_list,
  89         .read_memory = x86_32_common_read_memory,
  90         .write_memory = x86_32_common_write_memory,
  91         .add_breakpoint = x86_32_common_add_breakpoint,
  92         .remove_breakpoint = x86_32_common_remove_breakpoint,
  93         .add_watchpoint = x86_32_common_add_watchpoint,
  94         .remove_watchpoint = x86_32_common_remove_watchpoint,
  95         .virt2phys = x86_32_common_virt2phys,
  96         .read_phys_memory = x86_32_common_read_phys_mem,
  97         .write_phys_memory = x86_32_common_write_phys_mem,
  98         .mmu = x86_32_common_mmu,
  99 };