target/cortex_a: remove buggy memory AP accesses
[openocd.git] / src / target / esirisc_jtag.h
blob8189ddc6c905debf4494090feeec0260f047f4a2
1 /***************************************************************************
2 * Copyright (C) 2018 by Square, Inc. *
3 * Steven Stallion <stallion@squareup.com> *
4 * James Zhao <hjz@squareup.com> *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
20 #ifndef OPENOCD_TARGET_ESIRISC_JTAG_H
21 #define OPENOCD_TARGET_ESIRISC_JTAG_H
23 #include <jtag/jtag.h>
25 /* TAP Instructions */
26 #define INSTR_IDCODE 0x8
27 #define INSTR_DEBUG 0x9
28 #define INSTR_BYPASS 0xf
29 #define INSTR_LENGTH 4
31 /* eSi-Debug Commands */
32 #define DEBUG_NOP 0x00
33 #define DEBUG_READ_BYTE 0x10
34 #define DEBUG_READ_HWORD 0x20
35 #define DEBUG_READ_WORD 0x30
36 #define DEBUG_WRITE_BYTE 0x60
37 #define DEBUG_WRITE_HWORD 0x70
38 #define DEBUG_WRITE_WORD 0x80
39 #define DEBUG_READ_REG 0xb0
40 #define DEBUG_WRITE_REG 0xc0
41 #define DEBUG_READ_CSR 0xd0
42 #define DEBUG_WRITE_CSR 0xe0
43 #define DEBUG_ENABLE_DEBUG 0xf0
44 #define DEBUG_DISABLE_DEBUG 0xf2
45 #define DEBUG_ASSERT_RESET 0xf4
46 #define DEBUG_DEASSERT_RESET 0xf6
47 #define DEBUG_BREAK 0xf8
48 #define DEBUG_CONTINUE 0xfa
49 #define DEBUG_FLUSH_CACHES 0xfc
51 /* Exception IDs */
52 #define EID_OVERFLOW 0x3d
53 #define EID_CANT_DEBUG 0x3e
54 #define EID_NONE 0x3f
56 /* Byte Stuffing */
57 #define STUFF_MARKER 0x55
58 #define PAD_BYTE 0xaa
60 struct esirisc_jtag {
61 struct jtag_tap *tap;
62 uint8_t status;
65 bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info);
66 bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info);
67 uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info);
69 int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info,
70 uint32_t address, uint8_t *data);
71 int esirisc_jtag_read_hword(struct esirisc_jtag *jtag_info,
72 uint32_t address, uint16_t *data);
73 int esirisc_jtag_read_word(struct esirisc_jtag *jtag_info,
74 uint32_t address, uint32_t *data);
76 int esirisc_jtag_write_byte(struct esirisc_jtag *jtag_info,
77 uint32_t address, uint8_t data);
78 int esirisc_jtag_write_hword(struct esirisc_jtag *jtag_info,
79 uint32_t address, uint16_t data);
80 int esirisc_jtag_write_word(struct esirisc_jtag *jtag_info,
81 uint32_t address, uint32_t data);
83 int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info,
84 uint8_t reg, uint32_t *data);
85 int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info,
86 uint8_t reg, uint32_t data);
88 int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info,
89 uint8_t bank, uint8_t csr, uint32_t *data);
90 int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info,
91 uint8_t bank, uint8_t csr, uint32_t data);
93 int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info);
94 int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info);
96 int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info);
97 int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info);
99 int esirisc_jtag_break(struct esirisc_jtag *jtag_info);
100 int esirisc_jtag_continue(struct esirisc_jtag *jtag_info);
102 int esirisc_jtag_flush_caches(struct esirisc_jtag *jtag_info);
104 #endif /* OPENOCD_TARGET_ESIRISC_JTAG_H */