4 reset_config trst_and_srst srst_gates_jtag
6 if { [info exists CHIPNAME] } {
7 set _CHIPNAME $CHIPNAME
12 if { [info exists ENDIAN] } {
18 if { [info exists CPUTAPID ] } {
19 set _CPUTAPID $CPUTAPID
21 set _CPUTAPID 0x07b3601d
24 if { [info exists SDMATAPID ] } {
25 set _SDMATAPID $SDMATAPID
27 set _SDMATAPID 0x2190101d
30 #========================================
31 # The "system jtag controller"
32 # IMX31 reference manual, page 6-28 - figure 6-14
33 if { [info exists SJCTAPID ] } {
34 set _SJCTAPID $SJCTAPID
36 set _SJCTAPID 0x2b900f0f
38 jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
40 # The "SDMA" - <S>mart <DMA> controller debug tap
41 # Based on some IO pins - this can be disabled & removed
44 # SJC_MOD - controls multiplexer - disables ARM1136
45 # SDMA_BYPASS - disables SDMA -
47 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
48 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
50 # No IDCODE for this TAP
51 jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
53 # Per section 40.17.1, table 40-85 the IR register is 4 bits
54 # But this conflicts with Diagram 6-13, "3bits ir and drs"
55 jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
57 set _TARGETNAME $_CHIPNAME.cpu
58 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
61 proc power_restore {} { puts "Sensed power restore. No action." }
62 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }