1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "target_type.h"
29 #include "arm7_9_common.h"
30 #include "arm_simulator.h"
31 #include "arm_disassembler.h"
32 #include "time_support.h"
36 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
38 /* forward declarations */
39 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
);
40 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
41 int xscale_quit(void);
43 int xscale_arch_state(struct target_s
*target
);
44 int xscale_poll(target_t
*target
);
45 int xscale_halt(target_t
*target
);
46 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
47 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
48 int xscale_debug_entry(target_t
*target
);
49 int xscale_restore_context(target_t
*target
);
51 int xscale_assert_reset(target_t
*target
);
52 int xscale_deassert_reset(target_t
*target
);
53 int xscale_soft_reset_halt(struct target_s
*target
);
55 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
57 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
58 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
60 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
61 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
62 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
64 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
65 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
66 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
67 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
68 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
69 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
70 void xscale_enable_watchpoints(struct target_s
*target
);
71 void xscale_enable_breakpoints(struct target_s
*target
);
72 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
73 static int xscale_mmu(struct target_s
*target
, int *enabled
);
75 int xscale_read_trace(target_t
*target
);
77 target_type_t xscale_target
=
82 .arch_state
= xscale_arch_state
,
84 .target_request_data
= NULL
,
87 .resume
= xscale_resume
,
90 .assert_reset
= xscale_assert_reset
,
91 .deassert_reset
= xscale_deassert_reset
,
92 .soft_reset_halt
= xscale_soft_reset_halt
,
94 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
96 .read_memory
= xscale_read_memory
,
97 .write_memory
= xscale_write_memory
,
98 .bulk_write_memory
= xscale_bulk_write_memory
,
99 .checksum_memory
= arm7_9_checksum_memory
,
100 .blank_check_memory
= arm7_9_blank_check_memory
,
102 .run_algorithm
= armv4_5_run_algorithm
,
104 .add_breakpoint
= xscale_add_breakpoint
,
105 .remove_breakpoint
= xscale_remove_breakpoint
,
106 .add_watchpoint
= xscale_add_watchpoint
,
107 .remove_watchpoint
= xscale_remove_watchpoint
,
109 .register_commands
= xscale_register_commands
,
110 .target_create
= xscale_target_create
,
111 .init_target
= xscale_init_target
,
114 .virt2phys
= xscale_virt2phys
,
118 char* xscale_reg_list
[] =
120 "XSCALE_MAINID", /* 0 */
130 "XSCALE_IBCR0", /* 10 */
140 "XSCALE_RX", /* 20 */
144 xscale_reg_t xscale_reg_arch_info
[] =
146 {XSCALE_MAINID
, NULL
},
147 {XSCALE_CACHETYPE
, NULL
},
149 {XSCALE_AUXCTRL
, NULL
},
155 {XSCALE_CPACCESS
, NULL
},
156 {XSCALE_IBCR0
, NULL
},
157 {XSCALE_IBCR1
, NULL
},
160 {XSCALE_DBCON
, NULL
},
161 {XSCALE_TBREG
, NULL
},
162 {XSCALE_CHKPT0
, NULL
},
163 {XSCALE_CHKPT1
, NULL
},
164 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
165 {-1, NULL
}, /* TX accessed via JTAG */
166 {-1, NULL
}, /* RX accessed via JTAG */
167 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
170 int xscale_reg_arch_type
= -1;
172 int xscale_get_reg(reg_t
*reg
);
173 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
175 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
177 armv4_5_common_t
*armv4_5
= target
->arch_info
;
178 xscale_common_t
*xscale
= armv4_5
->arch_info
;
180 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
182 LOG_ERROR("target isn't an XScale target");
186 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
188 LOG_ERROR("target isn't an XScale target");
192 *armv4_5_p
= armv4_5
;
198 int xscale_jtag_set_instr(jtag_tap_t
*tap
, u32 new_instr
)
203 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
208 field
.num_bits
= tap
->ir_length
;
209 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
210 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
213 field
.in_value
= tmp
;
215 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
217 /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
218 jtag_check_value_mask(&field
, tap
->expected
, tap
->expected_mask
);
220 free(field
.out_value
);
226 int xscale_read_dcsr(target_t
*target
)
228 armv4_5_common_t
*armv4_5
= target
->arch_info
;
229 xscale_common_t
*xscale
= armv4_5
->arch_info
;
233 scan_field_t fields
[3];
235 u8 field0_check_value
= 0x2;
236 u8 field0_check_mask
= 0x7;
238 u8 field2_check_value
= 0x0;
239 u8 field2_check_mask
= 0x1;
241 jtag_add_end_state(TAP_DRPAUSE
);
242 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
244 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
245 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
247 fields
[0].tap
= xscale
->jtag_info
.tap
;
248 fields
[0].num_bits
= 3;
249 fields
[0].out_value
= &field0
;
251 fields
[0].in_value
= &tmp
;
253 fields
[1].tap
= xscale
->jtag_info
.tap
;
254 fields
[1].num_bits
= 32;
255 fields
[1].out_value
= NULL
;
256 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
259 fields
[2].tap
= xscale
->jtag_info
.tap
;
260 fields
[2].num_bits
= 1;
261 fields
[2].out_value
= &field2
;
263 fields
[2].in_value
= &tmp2
;
265 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
267 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
268 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
270 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
272 LOG_ERROR("JTAG error while reading DCSR");
276 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
277 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
279 /* write the register with the value we just read
280 * on this second pass, only the first bit of field0 is guaranteed to be 0)
282 field0_check_mask
= 0x1;
283 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
284 fields
[1].in_value
= NULL
;
286 jtag_add_end_state(TAP_IDLE
);
288 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
290 /* DANGER!!! this must be here. It will make sure that the arguments
291 * to jtag_set_check_value() does not go out of scope! */
292 return jtag_execute_queue();
296 static void xscale_getbuf(u8
*in
)
298 *((u32
*)in
)=buf_get_u32(in
, 0, 32);
301 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
304 return ERROR_INVALID_ARGUMENTS
;
307 armv4_5_common_t
*armv4_5
= target
->arch_info
;
308 xscale_common_t
*xscale
= armv4_5
->arch_info
;
311 scan_field_t fields
[3];
313 u8
*field0
= malloc(num_words
* 1);
314 u8 field0_check_value
= 0x2;
315 u8 field0_check_mask
= 0x6;
316 u32
*field1
= malloc(num_words
* 4);
317 u8 field2_check_value
= 0x0;
318 u8 field2_check_mask
= 0x1;
320 int words_scheduled
= 0;
324 path
[0] = TAP_DRSELECT
;
325 path
[1] = TAP_DRCAPTURE
;
326 path
[2] = TAP_DRSHIFT
;
328 fields
[0].tap
= xscale
->jtag_info
.tap
;
329 fields
[0].num_bits
= 3;
330 fields
[0].out_value
= NULL
;
331 fields
[0].in_value
= NULL
;
332 fields
[0].check_value
= &field0_check_value
;
333 fields
[0].check_mask
= &field0_check_mask
;
335 fields
[1].tap
= xscale
->jtag_info
.tap
;
336 fields
[1].num_bits
= 32;
337 fields
[1].out_value
= NULL
;
338 fields
[1].check_value
= NULL
;
339 fields
[1].check_mask
= NULL
;
341 fields
[2].tap
= xscale
->jtag_info
.tap
;
342 fields
[2].num_bits
= 1;
343 fields
[2].out_value
= NULL
;
344 fields
[2].in_value
= NULL
;
345 fields
[2].check_value
= &field2_check_value
;
346 fields
[2].check_mask
= &field2_check_mask
;
348 jtag_add_end_state(TAP_IDLE
);
349 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
350 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
352 /* repeat until all words have been collected */
354 while (words_done
< num_words
)
358 for (i
= words_done
; i
< num_words
; i
++)
360 fields
[0].in_value
= &field0
[i
];
362 jtag_add_pathmove(3, path
);
364 fields
[1].in_value
= (u8
*)(field1
+i
);
366 jtag_add_dr_scan_check(3, fields
, jtag_add_end_state(TAP_IDLE
));
368 jtag_add_callback(xscale_getbuf
, (u8
*)(field1
+i
));
373 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
375 LOG_ERROR("JTAG error while receiving data from debug handler");
379 /* examine results */
380 for (i
= words_done
; i
< num_words
; i
++)
382 if (!(field0
[0] & 1))
384 /* move backwards if necessary */
386 for (j
= i
; j
< num_words
- 1; j
++)
388 field0
[j
] = field0
[j
+1];
389 field1
[j
] = field1
[j
+1];
394 if (words_scheduled
==0)
396 if (attempts
++==1000)
398 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
399 retval
=ERROR_TARGET_TIMEOUT
;
404 words_done
+= words_scheduled
;
407 for (i
= 0; i
< num_words
; i
++)
408 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
415 int xscale_read_tx(target_t
*target
, int consume
)
417 armv4_5_common_t
*armv4_5
= target
->arch_info
;
418 xscale_common_t
*xscale
= armv4_5
->arch_info
;
420 tap_state_t noconsume_path
[6];
423 struct timeval timeout
, now
;
425 scan_field_t fields
[3];
427 u8 field0_check_value
= 0x2;
428 u8 field0_check_mask
= 0x6;
429 u8 field2_check_value
= 0x0;
430 u8 field2_check_mask
= 0x1;
432 jtag_add_end_state(TAP_IDLE
);
434 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
436 path
[0] = TAP_DRSELECT
;
437 path
[1] = TAP_DRCAPTURE
;
438 path
[2] = TAP_DRSHIFT
;
440 noconsume_path
[0] = TAP_DRSELECT
;
441 noconsume_path
[1] = TAP_DRCAPTURE
;
442 noconsume_path
[2] = TAP_DREXIT1
;
443 noconsume_path
[3] = TAP_DRPAUSE
;
444 noconsume_path
[4] = TAP_DREXIT2
;
445 noconsume_path
[5] = TAP_DRSHIFT
;
447 fields
[0].tap
= xscale
->jtag_info
.tap
;
448 fields
[0].num_bits
= 3;
449 fields
[0].out_value
= NULL
;
450 fields
[0].in_value
= &field0_in
;
452 fields
[1].tap
= xscale
->jtag_info
.tap
;
453 fields
[1].num_bits
= 32;
454 fields
[1].out_value
= NULL
;
455 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
458 fields
[2].tap
= xscale
->jtag_info
.tap
;
459 fields
[2].num_bits
= 1;
460 fields
[2].out_value
= NULL
;
462 fields
[2].in_value
= &tmp
;
464 gettimeofday(&timeout
, NULL
);
465 timeval_add_time(&timeout
, 1, 0);
469 /* if we want to consume the register content (i.e. clear TX_READY),
470 * we have to go straight from Capture-DR to Shift-DR
471 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
474 jtag_add_pathmove(3, path
);
477 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
480 jtag_add_dr_scan(3, fields
, jtag_add_end_state(TAP_IDLE
));
482 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
483 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
485 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
487 LOG_ERROR("JTAG error while reading TX");
488 return ERROR_TARGET_TIMEOUT
;
491 gettimeofday(&now
, NULL
);
492 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
494 LOG_ERROR("time out reading TX register");
495 return ERROR_TARGET_TIMEOUT
;
497 if (!((!(field0_in
& 1)) && consume
))
503 LOG_DEBUG("waiting 100ms");
504 alive_sleep(100); /* avoid flooding the logs */
512 if (!(field0_in
& 1))
513 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
518 int xscale_write_rx(target_t
*target
)
520 armv4_5_common_t
*armv4_5
= target
->arch_info
;
521 xscale_common_t
*xscale
= armv4_5
->arch_info
;
524 struct timeval timeout
, now
;
526 scan_field_t fields
[3];
529 u8 field0_check_value
= 0x2;
530 u8 field0_check_mask
= 0x6;
532 u8 field2_check_value
= 0x0;
533 u8 field2_check_mask
= 0x1;
535 jtag_add_end_state(TAP_IDLE
);
537 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
539 fields
[0].tap
= xscale
->jtag_info
.tap
;
540 fields
[0].num_bits
= 3;
541 fields
[0].out_value
= &field0_out
;
542 fields
[0].in_value
= &field0_in
;
544 fields
[1].tap
= xscale
->jtag_info
.tap
;
545 fields
[1].num_bits
= 32;
546 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
547 fields
[1].in_value
= NULL
;
550 fields
[2].tap
= xscale
->jtag_info
.tap
;
551 fields
[2].num_bits
= 1;
552 fields
[2].out_value
= &field2
;
554 fields
[2].in_value
= &tmp
;
556 gettimeofday(&timeout
, NULL
);
557 timeval_add_time(&timeout
, 1, 0);
559 /* poll until rx_read is low */
560 LOG_DEBUG("polling RX");
563 jtag_add_dr_scan(3, fields
, jtag_add_end_state(TAP_IDLE
));
565 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
566 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
568 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
570 LOG_ERROR("JTAG error while writing RX");
574 gettimeofday(&now
, NULL
);
575 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
577 LOG_ERROR("time out writing RX register");
578 return ERROR_TARGET_TIMEOUT
;
580 if (!(field0_in
& 1))
584 LOG_DEBUG("waiting 100ms");
585 alive_sleep(100); /* avoid flooding the logs */
595 jtag_add_dr_scan(3, fields
, jtag_add_end_state(TAP_IDLE
));
597 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
599 LOG_ERROR("JTAG error while writing RX");
606 /* send count elements of size byte to the debug handler */
607 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
609 armv4_5_common_t
*armv4_5
= target
->arch_info
;
610 xscale_common_t
*xscale
= armv4_5
->arch_info
;
618 jtag_add_end_state(TAP_IDLE
);
620 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
627 int endianness
= target
->endianness
;
628 while (done_count
++ < count
)
633 if (endianness
== TARGET_LITTLE_ENDIAN
)
635 t
[1]=le_to_h_u32(buffer
);
638 t
[1]=be_to_h_u32(buffer
);
642 if (endianness
== TARGET_LITTLE_ENDIAN
)
644 t
[1]=le_to_h_u16(buffer
);
647 t
[1]=be_to_h_u16(buffer
);
654 LOG_ERROR("BUG: size neither 4, 2 nor 1");
657 jtag_add_dr_out(xscale
->jtag_info
.tap
,
661 jtag_add_end_state(TAP_IDLE
));
665 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
667 LOG_ERROR("JTAG error while sending data to debug handler");
674 int xscale_send_u32(target_t
*target
, u32 value
)
676 armv4_5_common_t
*armv4_5
= target
->arch_info
;
677 xscale_common_t
*xscale
= armv4_5
->arch_info
;
679 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
680 return xscale_write_rx(target
);
683 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
685 armv4_5_common_t
*armv4_5
= target
->arch_info
;
686 xscale_common_t
*xscale
= armv4_5
->arch_info
;
690 scan_field_t fields
[3];
692 u8 field0_check_value
= 0x2;
693 u8 field0_check_mask
= 0x7;
695 u8 field2_check_value
= 0x0;
696 u8 field2_check_mask
= 0x1;
699 xscale
->hold_rst
= hold_rst
;
701 if (ext_dbg_brk
!= -1)
702 xscale
->external_debug_break
= ext_dbg_brk
;
704 jtag_add_end_state(TAP_IDLE
);
705 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
707 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
708 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
710 fields
[0].tap
= xscale
->jtag_info
.tap
;
711 fields
[0].num_bits
= 3;
712 fields
[0].out_value
= &field0
;
714 fields
[0].in_value
= &tmp
;
716 fields
[1].tap
= xscale
->jtag_info
.tap
;
717 fields
[1].num_bits
= 32;
718 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
719 fields
[1].in_value
= NULL
;
722 fields
[2].tap
= xscale
->jtag_info
.tap
;
723 fields
[2].num_bits
= 1;
724 fields
[2].out_value
= &field2
;
726 fields
[2].in_value
= &tmp2
;
728 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
730 jtag_check_value_mask(fields
+0, &field0_check_value
, &field0_check_mask
);
731 jtag_check_value_mask(fields
+2, &field2_check_value
, &field2_check_mask
);
733 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
735 LOG_ERROR("JTAG error while writing DCSR");
739 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
740 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
745 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
746 unsigned int parity (unsigned int v
)
753 LOG_DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
754 return (0x6996 >> v
) & 1;
757 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
759 armv4_5_common_t
*armv4_5
= target
->arch_info
;
760 xscale_common_t
*xscale
= armv4_5
->arch_info
;
765 scan_field_t fields
[2];
767 LOG_DEBUG("loading miniIC at 0x%8.8x", va
);
769 jtag_add_end_state(TAP_IDLE
);
770 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
772 /* CMD is b010 for Main IC and b011 for Mini IC */
774 buf_set_u32(&cmd
, 0, 3, 0x3);
776 buf_set_u32(&cmd
, 0, 3, 0x2);
778 buf_set_u32(&cmd
, 3, 3, 0x0);
780 /* virtual address of desired cache line */
781 buf_set_u32(packet
, 0, 27, va
>> 5);
783 fields
[0].tap
= xscale
->jtag_info
.tap
;
784 fields
[0].num_bits
= 6;
785 fields
[0].out_value
= &cmd
;
787 fields
[0].in_value
= NULL
;
793 fields
[1].tap
= xscale
->jtag_info
.tap
;
794 fields
[1].num_bits
= 27;
795 fields
[1].out_value
= packet
;
797 fields
[1].in_value
= NULL
;
803 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
805 fields
[0].num_bits
= 32;
806 fields
[0].out_value
= packet
;
808 fields
[1].num_bits
= 1;
809 fields
[1].out_value
= &cmd
;
811 for (word
= 0; word
< 8; word
++)
813 buf_set_u32(packet
, 0, 32, buffer
[word
]);
816 memcpy(&value
, packet
, sizeof(u32
));
819 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
822 jtag_execute_queue();
827 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
829 armv4_5_common_t
*armv4_5
= target
->arch_info
;
830 xscale_common_t
*xscale
= armv4_5
->arch_info
;
834 scan_field_t fields
[2];
836 jtag_add_end_state(TAP_IDLE
);
837 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
839 /* CMD for invalidate IC line b000, bits [6:4] b000 */
840 buf_set_u32(&cmd
, 0, 6, 0x0);
842 /* virtual address of desired cache line */
843 buf_set_u32(packet
, 0, 27, va
>> 5);
845 fields
[0].tap
= xscale
->jtag_info
.tap
;
846 fields
[0].num_bits
= 6;
847 fields
[0].out_value
= &cmd
;
849 fields
[0].in_value
= NULL
;
855 fields
[1].tap
= xscale
->jtag_info
.tap
;
856 fields
[1].num_bits
= 27;
857 fields
[1].out_value
= packet
;
859 fields
[1].in_value
= NULL
;
865 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
870 int xscale_update_vectors(target_t
*target
)
872 armv4_5_common_t
*armv4_5
= target
->arch_info
;
873 xscale_common_t
*xscale
= armv4_5
->arch_info
;
877 u32 low_reset_branch
, high_reset_branch
;
879 for (i
= 1; i
< 8; i
++)
881 /* if there's a static vector specified for this exception, override */
882 if (xscale
->static_high_vectors_set
& (1 << i
))
884 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
888 retval
=target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
889 if (retval
== ERROR_TARGET_TIMEOUT
)
891 if (retval
!=ERROR_OK
)
893 /* Some of these reads will fail as part of normal execution */
894 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
899 for (i
= 1; i
< 8; i
++)
901 if (xscale
->static_low_vectors_set
& (1 << i
))
903 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
907 retval
=target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
908 if (retval
== ERROR_TARGET_TIMEOUT
)
910 if (retval
!=ERROR_OK
)
912 /* Some of these reads will fail as part of normal execution */
913 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
918 /* calculate branches to debug handler */
919 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
920 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
922 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
923 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
925 /* invalidate and load exception vectors in mini i-cache */
926 xscale_invalidate_ic_line(target
, 0x0);
927 xscale_invalidate_ic_line(target
, 0xffff0000);
929 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
930 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
935 int xscale_arch_state(struct target_s
*target
)
937 armv4_5_common_t
*armv4_5
= target
->arch_info
;
938 xscale_common_t
*xscale
= armv4_5
->arch_info
;
942 "disabled", "enabled"
945 char *arch_dbg_reason
[] =
947 "", "\n(processor reset)", "\n(trace buffer full)"
950 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
952 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
956 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
957 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
958 "MMU: %s, D-Cache: %s, I-Cache: %s"
960 armv4_5_state_strings
[armv4_5
->core_state
],
961 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
962 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
963 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
964 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
965 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
966 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
967 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
968 arch_dbg_reason
[xscale
->arch_debug_reason
]);
973 int xscale_poll(target_t
*target
)
976 armv4_5_common_t
*armv4_5
= target
->arch_info
;
977 xscale_common_t
*xscale
= armv4_5
->arch_info
;
979 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
981 enum target_state previous_state
= target
->state
;
982 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
985 /* there's data to read from the tx register, we entered debug state */
986 xscale
->handler_running
= 1;
988 target
->state
= TARGET_HALTED
;
990 /* process debug entry, fetching current mode regs */
991 retval
= xscale_debug_entry(target
);
993 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
995 LOG_USER("error while polling TX register, reset CPU");
996 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
997 target
->state
= TARGET_HALTED
;
1000 /* debug_entry could have overwritten target state (i.e. immediate resume)
1001 * don't signal event handlers in that case
1003 if (target
->state
!= TARGET_HALTED
)
1006 /* if target was running, signal that we halted
1007 * otherwise we reentered from debug execution */
1008 if (previous_state
== TARGET_RUNNING
)
1009 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1011 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1017 int xscale_debug_entry(target_t
*target
)
1019 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1020 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1028 /* clear external dbg break (will be written on next DCSR read) */
1029 xscale
->external_debug_break
= 0;
1030 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1033 /* get r0, pc, r1 to r7 and cpsr */
1034 if ((retval
=xscale_receive(target
, buffer
, 10))!=ERROR_OK
)
1037 /* move r0 from buffer to register cache */
1038 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1039 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1040 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1041 LOG_DEBUG("r0: 0x%8.8x", buffer
[0]);
1043 /* move pc from buffer to register cache */
1044 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1045 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1046 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1047 LOG_DEBUG("pc: 0x%8.8x", buffer
[1]);
1049 /* move data from buffer to register cache */
1050 for (i
= 1; i
<= 7; i
++)
1052 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1053 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1054 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1055 LOG_DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1058 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1059 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1060 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1061 LOG_DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1063 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1064 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1066 target
->state
= TARGET_UNKNOWN
;
1067 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1068 return ERROR_TARGET_FAILURE
;
1070 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1072 if (buffer
[9] & 0x20)
1073 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1075 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1078 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1081 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1082 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1084 xscale_receive(target
, buffer
, 8);
1085 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1086 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1087 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1091 /* r8 to r14, but no spsr */
1092 xscale_receive(target
, buffer
, 7);
1095 /* move data from buffer to register cache */
1096 for (i
= 8; i
<= 14; i
++)
1098 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1099 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1100 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1103 /* examine debug reason */
1104 xscale_read_dcsr(target
);
1105 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1107 /* stored PC (for calculating fixup) */
1108 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1112 case 0x0: /* Processor reset */
1113 target
->debug_reason
= DBG_REASON_DBGRQ
;
1114 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1117 case 0x1: /* Instruction breakpoint hit */
1118 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1119 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1122 case 0x2: /* Data breakpoint hit */
1123 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1124 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1127 case 0x3: /* BKPT instruction executed */
1128 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1129 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1132 case 0x4: /* Ext. debug event */
1133 target
->debug_reason
= DBG_REASON_DBGRQ
;
1134 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1137 case 0x5: /* Vector trap occured */
1138 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1139 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1142 case 0x6: /* Trace buffer full break */
1143 target
->debug_reason
= DBG_REASON_DBGRQ
;
1144 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1147 case 0x7: /* Reserved */
1149 LOG_ERROR("Method of Entry is 'Reserved'");
1154 /* apply PC fixup */
1155 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1157 /* on the first debug entry, identify cache type */
1158 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1162 /* read cp15 cache type register */
1163 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1164 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1166 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1169 /* examine MMU and Cache settings */
1170 /* read cp15 control register */
1171 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1172 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1173 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1174 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1175 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1177 /* tracing enabled, read collected trace data */
1178 if (xscale
->trace
.buffer_enabled
)
1180 xscale_read_trace(target
);
1181 xscale
->trace
.buffer_fill
--;
1183 /* resume if we're still collecting trace data */
1184 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1185 && (xscale
->trace
.buffer_fill
> 0))
1187 xscale_resume(target
, 1, 0x0, 1, 0);
1191 xscale
->trace
.buffer_enabled
= 0;
1198 int xscale_halt(target_t
*target
)
1200 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1201 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1203 LOG_DEBUG("target->state: %s",
1204 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1206 if (target
->state
== TARGET_HALTED
)
1208 LOG_DEBUG("target was already halted");
1211 else if (target
->state
== TARGET_UNKNOWN
)
1213 /* this must not happen for a xscale target */
1214 LOG_ERROR("target was in unknown state when halt was requested");
1215 return ERROR_TARGET_INVALID
;
1217 else if (target
->state
== TARGET_RESET
)
1219 LOG_DEBUG("target->state == TARGET_RESET");
1223 /* assert external dbg break */
1224 xscale
->external_debug_break
= 1;
1225 xscale_read_dcsr(target
);
1227 target
->debug_reason
= DBG_REASON_DBGRQ
;
1233 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1235 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1236 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1237 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1240 if (xscale
->ibcr0_used
)
1242 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1246 xscale_unset_breakpoint(target
, ibcr0_bp
);
1250 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1255 if ((retval
=xscale_set_reg_u32(ibcr0
, next_pc
| 0x1))!=ERROR_OK
)
1261 int xscale_disable_single_step(struct target_s
*target
)
1263 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1264 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1265 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1268 if ((retval
=xscale_set_reg_u32(ibcr0
, 0x0))!=ERROR_OK
)
1274 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1276 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1277 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1278 breakpoint_t
*breakpoint
= target
->breakpoints
;
1287 if (target
->state
!= TARGET_HALTED
)
1289 LOG_WARNING("target not halted");
1290 return ERROR_TARGET_NOT_HALTED
;
1293 if (!debug_execution
)
1295 target_free_all_working_areas(target
);
1298 /* update vector tables */
1299 if ((retval
=xscale_update_vectors(target
))!=ERROR_OK
)
1302 /* current = 1: continue on current pc, otherwise continue at <address> */
1304 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1306 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1308 /* if we're at the reset vector, we have to simulate the branch */
1309 if (current_pc
== 0x0)
1311 arm_simulate_step(target
, NULL
);
1312 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1315 /* the front-end may request us not to handle breakpoints */
1316 if (handle_breakpoints
)
1318 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1322 /* there's a breakpoint at the current PC, we have to step over it */
1323 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1324 xscale_unset_breakpoint(target
, breakpoint
);
1326 /* calculate PC of next instruction */
1327 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1330 target_read_u32(target
, current_pc
, ¤t_opcode
);
1331 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1334 LOG_DEBUG("enable single-step");
1335 xscale_enable_single_step(target
, next_pc
);
1337 /* restore banked registers */
1338 xscale_restore_context(target
);
1340 /* send resume request (command 0x30 or 0x31)
1341 * clean the trace buffer if it is to be enabled (0x62) */
1342 if (xscale
->trace
.buffer_enabled
)
1344 xscale_send_u32(target
, 0x62);
1345 xscale_send_u32(target
, 0x31);
1348 xscale_send_u32(target
, 0x30);
1351 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1352 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1354 for (i
= 7; i
>= 0; i
--)
1357 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1358 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1362 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1363 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1365 /* wait for and process debug entry */
1366 xscale_debug_entry(target
);
1368 LOG_DEBUG("disable single-step");
1369 xscale_disable_single_step(target
);
1371 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1372 xscale_set_breakpoint(target
, breakpoint
);
1376 /* enable any pending breakpoints and watchpoints */
1377 xscale_enable_breakpoints(target
);
1378 xscale_enable_watchpoints(target
);
1380 /* restore banked registers */
1381 xscale_restore_context(target
);
1383 /* send resume request (command 0x30 or 0x31)
1384 * clean the trace buffer if it is to be enabled (0x62) */
1385 if (xscale
->trace
.buffer_enabled
)
1387 xscale_send_u32(target
, 0x62);
1388 xscale_send_u32(target
, 0x31);
1391 xscale_send_u32(target
, 0x30);
1394 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1395 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1397 for (i
= 7; i
>= 0; i
--)
1400 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1401 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1405 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1406 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1408 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1410 if (!debug_execution
)
1412 /* registers are now invalid */
1413 armv4_5_invalidate_core_regs(target
);
1414 target
->state
= TARGET_RUNNING
;
1415 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1419 target
->state
= TARGET_DEBUG_RUNNING
;
1420 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1423 LOG_DEBUG("target resumed");
1425 xscale
->handler_running
= 1;
1430 static int xscale_step_inner(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1432 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1433 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1439 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1441 /* calculate PC of next instruction */
1442 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1444 u32 current_opcode
, current_pc
;
1445 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1447 target_read_u32(target
, current_pc
, ¤t_opcode
);
1448 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1452 LOG_DEBUG("enable single-step");
1453 if ((retval
=xscale_enable_single_step(target
, next_pc
))!=ERROR_OK
)
1456 /* restore banked registers */
1457 if ((retval
=xscale_restore_context(target
))!=ERROR_OK
)
1460 /* send resume request (command 0x30 or 0x31)
1461 * clean the trace buffer if it is to be enabled (0x62) */
1462 if (xscale
->trace
.buffer_enabled
)
1464 if ((retval
=xscale_send_u32(target
, 0x62))!=ERROR_OK
)
1466 if ((retval
=xscale_send_u32(target
, 0x31))!=ERROR_OK
)
1470 if ((retval
=xscale_send_u32(target
, 0x30))!=ERROR_OK
)
1474 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32)))!=ERROR_OK
)
1476 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1478 for (i
= 7; i
>= 0; i
--)
1481 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32)))!=ERROR_OK
)
1483 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1487 if ((retval
=xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32)))!=ERROR_OK
)
1489 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1491 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1493 /* registers are now invalid */
1494 if ((retval
=armv4_5_invalidate_core_regs(target
))!=ERROR_OK
)
1497 /* wait for and process debug entry */
1498 if ((retval
=xscale_debug_entry(target
))!=ERROR_OK
)
1501 LOG_DEBUG("disable single-step");
1502 if ((retval
=xscale_disable_single_step(target
))!=ERROR_OK
)
1505 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1510 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1512 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1513 breakpoint_t
*breakpoint
= target
->breakpoints
;
1518 if (target
->state
!= TARGET_HALTED
)
1520 LOG_WARNING("target not halted");
1521 return ERROR_TARGET_NOT_HALTED
;
1524 /* current = 1: continue on current pc, otherwise continue at <address> */
1526 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1528 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1530 /* if we're at the reset vector, we have to simulate the step */
1531 if (current_pc
== 0x0)
1533 if ((retval
=arm_simulate_step(target
, NULL
))!=ERROR_OK
)
1535 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1537 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1538 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1543 /* the front-end may request us not to handle breakpoints */
1544 if (handle_breakpoints
)
1545 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1547 if ((retval
=xscale_unset_breakpoint(target
, breakpoint
))!=ERROR_OK
)
1551 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1555 xscale_set_breakpoint(target
, breakpoint
);
1558 LOG_DEBUG("target stepped");
1564 int xscale_assert_reset(target_t
*target
)
1566 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1567 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1569 LOG_DEBUG("target->state: %s",
1570 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1572 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1573 * end up in T-L-R, which would reset JTAG
1575 jtag_add_end_state(TAP_IDLE
);
1576 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
1578 /* set Hold reset, Halt mode and Trap Reset */
1579 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1580 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1581 xscale_write_dcsr(target
, 1, 0);
1583 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1584 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, 0x7f);
1585 jtag_execute_queue();
1588 jtag_add_reset(0, 1);
1590 /* sleep 1ms, to be sure we fulfill any requirements */
1591 jtag_add_sleep(1000);
1592 jtag_execute_queue();
1594 target
->state
= TARGET_RESET
;
1596 if (target
->reset_halt
)
1599 if ((retval
= target_halt(target
))!=ERROR_OK
)
1606 int xscale_deassert_reset(target_t
*target
)
1608 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1609 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1611 fileio_t debug_handler
;
1619 breakpoint_t
*breakpoint
= target
->breakpoints
;
1623 xscale
->ibcr_available
= 2;
1624 xscale
->ibcr0_used
= 0;
1625 xscale
->ibcr1_used
= 0;
1627 xscale
->dbr_available
= 2;
1628 xscale
->dbr0_used
= 0;
1629 xscale
->dbr1_used
= 0;
1631 /* mark all hardware breakpoints as unset */
1634 if (breakpoint
->type
== BKPT_HARD
)
1636 breakpoint
->set
= 0;
1638 breakpoint
= breakpoint
->next
;
1641 if (!xscale
->handler_installed
)
1644 jtag_add_reset(0, 0);
1646 /* wait 300ms; 150 and 100ms were not enough */
1647 jtag_add_sleep(300*1000);
1649 jtag_add_runtest(2030, jtag_add_end_state(TAP_IDLE
));
1650 jtag_execute_queue();
1652 /* set Hold reset, Halt mode and Trap Reset */
1653 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1654 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1655 xscale_write_dcsr(target
, 1, 0);
1657 /* Load debug handler */
1658 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1663 if ((binary_size
= debug_handler
.size
) % 4)
1665 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1669 if (binary_size
> 0x800)
1671 LOG_ERROR("debug_handler.bin: larger than 2kb");
1675 binary_size
= CEIL(binary_size
, 32) * 32;
1677 address
= xscale
->handler_address
;
1678 while (binary_size
> 0)
1683 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1688 for (i
= 0; i
< buf_cnt
; i
+= 4)
1690 /* convert LE buffer to host-endian u32 */
1691 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1694 for (; buf_cnt
< 32; buf_cnt
+= 4)
1696 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1699 /* only load addresses other than the reset vectors */
1700 if ((address
% 0x400) != 0x0)
1702 xscale_load_ic(target
, 1, address
, cache_line
);
1706 binary_size
-= buf_cnt
;
1709 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1710 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1712 jtag_add_runtest(30, jtag_add_end_state(TAP_IDLE
));
1714 jtag_add_sleep(100000);
1716 /* set Hold reset, Halt mode and Trap Reset */
1717 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1718 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1719 xscale_write_dcsr(target
, 1, 0);
1721 /* clear Hold reset to let the target run (should enter debug handler) */
1722 xscale_write_dcsr(target
, 0, 1);
1723 target
->state
= TARGET_RUNNING
;
1725 if (!target
->reset_halt
)
1727 jtag_add_sleep(10000);
1729 /* we should have entered debug now */
1730 xscale_debug_entry(target
);
1731 target
->state
= TARGET_HALTED
;
1733 /* resume the target */
1734 xscale_resume(target
, 1, 0x0, 1, 0);
1737 fileio_close(&debug_handler
);
1741 jtag_add_reset(0, 0);
1747 int xscale_soft_reset_halt(struct target_s
*target
)
1752 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1757 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1763 int xscale_full_context(target_t
*target
)
1765 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1773 if (target
->state
!= TARGET_HALTED
)
1775 LOG_WARNING("target not halted");
1776 return ERROR_TARGET_NOT_HALTED
;
1779 buffer
= malloc(4 * 8);
1781 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1782 * we can't enter User mode on an XScale (unpredictable),
1783 * but User shares registers with SYS
1785 for(i
= 1; i
< 7; i
++)
1789 /* check if there are invalid registers in the current mode
1791 for (j
= 0; j
<= 16; j
++)
1793 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1801 /* request banked registers */
1802 xscale_send_u32(target
, 0x0);
1805 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1806 tmp_cpsr
|= 0xc0; /* I/F bits */
1808 /* send CPSR for desired mode */
1809 xscale_send_u32(target
, tmp_cpsr
);
1811 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1812 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1814 xscale_receive(target
, buffer
, 8);
1815 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1816 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1817 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1821 xscale_receive(target
, buffer
, 7);
1824 /* move data from buffer to register cache */
1825 for (j
= 8; j
<= 14; j
++)
1827 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1828 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1829 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1839 int xscale_restore_context(target_t
*target
)
1841 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1847 if (target
->state
!= TARGET_HALTED
)
1849 LOG_WARNING("target not halted");
1850 return ERROR_TARGET_NOT_HALTED
;
1853 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1854 * we can't enter User mode on an XScale (unpredictable),
1855 * but User shares registers with SYS
1857 for(i
= 1; i
< 7; i
++)
1861 /* check if there are invalid registers in the current mode
1863 for (j
= 8; j
<= 14; j
++)
1865 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1869 /* if not USR/SYS, check if the SPSR needs to be written */
1870 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1872 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1880 /* send banked registers */
1881 xscale_send_u32(target
, 0x1);
1884 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1885 tmp_cpsr
|= 0xc0; /* I/F bits */
1887 /* send CPSR for desired mode */
1888 xscale_send_u32(target
, tmp_cpsr
);
1890 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1891 for (j
= 8; j
<= 14; j
++)
1893 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1894 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1897 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1899 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1900 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1908 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1910 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1911 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1916 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1918 if (target
->state
!= TARGET_HALTED
)
1920 LOG_WARNING("target not halted");
1921 return ERROR_TARGET_NOT_HALTED
;
1924 /* sanitize arguments */
1925 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1926 return ERROR_INVALID_ARGUMENTS
;
1928 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1929 return ERROR_TARGET_UNALIGNED_ACCESS
;
1931 /* send memory read request (command 0x1n, n: access size) */
1932 if ((retval
=xscale_send_u32(target
, 0x10 | size
))!=ERROR_OK
)
1935 /* send base address for read request */
1936 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
1939 /* send number of requested data words */
1940 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
1943 /* receive data from target (count times 32-bit words in host endianness) */
1944 buf32
= malloc(4 * count
);
1945 if ((retval
=xscale_receive(target
, buf32
, count
))!=ERROR_OK
)
1948 /* extract data from host-endian buffer into byte stream */
1949 for (i
= 0; i
< count
; i
++)
1954 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1958 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1962 *buffer
++ = buf32
[i
] & 0xff;
1965 LOG_ERROR("should never get here");
1972 /* examine DCSR, to see if Sticky Abort (SA) got set */
1973 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1975 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1978 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
1981 return ERROR_TARGET_DATA_ABORT
;
1987 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1989 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1990 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1993 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1995 if (target
->state
!= TARGET_HALTED
)
1997 LOG_WARNING("target not halted");
1998 return ERROR_TARGET_NOT_HALTED
;
2001 /* sanitize arguments */
2002 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2003 return ERROR_INVALID_ARGUMENTS
;
2005 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2006 return ERROR_TARGET_UNALIGNED_ACCESS
;
2008 /* send memory write request (command 0x2n, n: access size) */
2009 if ((retval
=xscale_send_u32(target
, 0x20 | size
))!=ERROR_OK
)
2012 /* send base address for read request */
2013 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
2016 /* send number of requested data words to be written*/
2017 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
2020 /* extract data from host-endian buffer into byte stream */
2022 for (i
= 0; i
< count
; i
++)
2027 value
= target_buffer_get_u32(target
, buffer
);
2028 xscale_send_u32(target
, value
);
2032 value
= target_buffer_get_u16(target
, buffer
);
2033 xscale_send_u32(target
, value
);
2038 xscale_send_u32(target
, value
);
2042 LOG_ERROR("should never get here");
2047 if ((retval
=xscale_send(target
, buffer
, count
, size
))!=ERROR_OK
)
2050 /* examine DCSR, to see if Sticky Abort (SA) got set */
2051 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
2053 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2056 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
2059 return ERROR_TARGET_DATA_ABORT
;
2065 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2067 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2070 u32
xscale_get_ttb(target_t
*target
)
2072 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2073 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2076 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2077 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2082 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2084 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2085 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2088 /* read cp15 control register */
2089 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2090 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2093 cp15_control
&= ~0x1U
;
2098 xscale_send_u32(target
, 0x50);
2099 xscale_send_u32(target
, xscale
->cache_clean_address
);
2101 /* invalidate DCache */
2102 xscale_send_u32(target
, 0x51);
2104 cp15_control
&= ~0x4U
;
2109 /* invalidate ICache */
2110 xscale_send_u32(target
, 0x52);
2111 cp15_control
&= ~0x1000U
;
2114 /* write new cp15 control register */
2115 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2117 /* execute cpwait to ensure outstanding operations complete */
2118 xscale_send_u32(target
, 0x53);
2121 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2123 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2124 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2127 /* read cp15 control register */
2128 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2129 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2132 cp15_control
|= 0x1U
;
2135 cp15_control
|= 0x4U
;
2138 cp15_control
|= 0x1000U
;
2140 /* write new cp15 control register */
2141 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2143 /* execute cpwait to ensure outstanding operations complete */
2144 xscale_send_u32(target
, 0x53);
2147 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2150 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2151 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2153 if (target
->state
!= TARGET_HALTED
)
2155 LOG_WARNING("target not halted");
2156 return ERROR_TARGET_NOT_HALTED
;
2159 if (breakpoint
->set
)
2161 LOG_WARNING("breakpoint already set");
2165 if (breakpoint
->type
== BKPT_HARD
)
2167 u32 value
= breakpoint
->address
| 1;
2168 if (!xscale
->ibcr0_used
)
2170 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2171 xscale
->ibcr0_used
= 1;
2172 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2174 else if (!xscale
->ibcr1_used
)
2176 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2177 xscale
->ibcr1_used
= 1;
2178 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2182 LOG_ERROR("BUG: no hardware comparator available");
2186 else if (breakpoint
->type
== BKPT_SOFT
)
2188 if (breakpoint
->length
== 4)
2190 /* keep the original instruction in target endianness */
2191 if((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2195 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2196 if((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2203 /* keep the original instruction in target endianness */
2204 if((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2208 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2209 if((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2214 breakpoint
->set
= 1;
2220 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2222 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2223 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2225 if (target
->state
!= TARGET_HALTED
)
2227 LOG_WARNING("target not halted");
2228 return ERROR_TARGET_NOT_HALTED
;
2231 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2233 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2234 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2237 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2239 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2240 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2243 if (breakpoint
->type
== BKPT_HARD
)
2245 xscale
->ibcr_available
--;
2251 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2254 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2255 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2257 if (target
->state
!= TARGET_HALTED
)
2259 LOG_WARNING("target not halted");
2260 return ERROR_TARGET_NOT_HALTED
;
2263 if (!breakpoint
->set
)
2265 LOG_WARNING("breakpoint not set");
2269 if (breakpoint
->type
== BKPT_HARD
)
2271 if (breakpoint
->set
== 1)
2273 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2274 xscale
->ibcr0_used
= 0;
2276 else if (breakpoint
->set
== 2)
2278 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2279 xscale
->ibcr1_used
= 0;
2281 breakpoint
->set
= 0;
2285 /* restore original instruction (kept in target endianness) */
2286 if (breakpoint
->length
== 4)
2288 if((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2295 if((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2300 breakpoint
->set
= 0;
2306 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2308 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2309 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2311 if (target
->state
!= TARGET_HALTED
)
2313 LOG_WARNING("target not halted");
2314 return ERROR_TARGET_NOT_HALTED
;
2317 if (breakpoint
->set
)
2319 xscale_unset_breakpoint(target
, breakpoint
);
2322 if (breakpoint
->type
== BKPT_HARD
)
2323 xscale
->ibcr_available
++;
2328 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2330 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2331 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2333 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2334 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2336 if (target
->state
!= TARGET_HALTED
)
2338 LOG_WARNING("target not halted");
2339 return ERROR_TARGET_NOT_HALTED
;
2342 xscale_get_reg(dbcon
);
2344 switch (watchpoint
->rw
)
2356 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2359 if (!xscale
->dbr0_used
)
2361 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2362 dbcon_value
|= enable
;
2363 xscale_set_reg_u32(dbcon
, dbcon_value
);
2364 watchpoint
->set
= 1;
2365 xscale
->dbr0_used
= 1;
2367 else if (!xscale
->dbr1_used
)
2369 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2370 dbcon_value
|= enable
<< 2;
2371 xscale_set_reg_u32(dbcon
, dbcon_value
);
2372 watchpoint
->set
= 2;
2373 xscale
->dbr1_used
= 1;
2377 LOG_ERROR("BUG: no hardware comparator available");
2384 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2386 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2387 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2389 if (target
->state
!= TARGET_HALTED
)
2391 LOG_WARNING("target not halted");
2392 return ERROR_TARGET_NOT_HALTED
;
2395 if (xscale
->dbr_available
< 1)
2397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2400 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2402 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2405 xscale
->dbr_available
--;
2410 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2412 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2413 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2414 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2415 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2417 if (target
->state
!= TARGET_HALTED
)
2419 LOG_WARNING("target not halted");
2420 return ERROR_TARGET_NOT_HALTED
;
2423 if (!watchpoint
->set
)
2425 LOG_WARNING("breakpoint not set");
2429 if (watchpoint
->set
== 1)
2431 dbcon_value
&= ~0x3;
2432 xscale_set_reg_u32(dbcon
, dbcon_value
);
2433 xscale
->dbr0_used
= 0;
2435 else if (watchpoint
->set
== 2)
2437 dbcon_value
&= ~0xc;
2438 xscale_set_reg_u32(dbcon
, dbcon_value
);
2439 xscale
->dbr1_used
= 0;
2441 watchpoint
->set
= 0;
2446 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2448 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2449 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2451 if (target
->state
!= TARGET_HALTED
)
2453 LOG_WARNING("target not halted");
2454 return ERROR_TARGET_NOT_HALTED
;
2457 if (watchpoint
->set
)
2459 xscale_unset_watchpoint(target
, watchpoint
);
2462 xscale
->dbr_available
++;
2467 void xscale_enable_watchpoints(struct target_s
*target
)
2469 watchpoint_t
*watchpoint
= target
->watchpoints
;
2473 if (watchpoint
->set
== 0)
2474 xscale_set_watchpoint(target
, watchpoint
);
2475 watchpoint
= watchpoint
->next
;
2479 void xscale_enable_breakpoints(struct target_s
*target
)
2481 breakpoint_t
*breakpoint
= target
->breakpoints
;
2483 /* set any pending breakpoints */
2486 if (breakpoint
->set
== 0)
2487 xscale_set_breakpoint(target
, breakpoint
);
2488 breakpoint
= breakpoint
->next
;
2492 int xscale_get_reg(reg_t
*reg
)
2494 xscale_reg_t
*arch_info
= reg
->arch_info
;
2495 target_t
*target
= arch_info
->target
;
2496 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2497 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2499 /* DCSR, TX and RX are accessible via JTAG */
2500 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2502 return xscale_read_dcsr(arch_info
->target
);
2504 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2506 /* 1 = consume register content */
2507 return xscale_read_tx(arch_info
->target
, 1);
2509 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2511 /* can't read from RX register (host -> debug handler) */
2514 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2516 /* can't (explicitly) read from TXRXCTRL register */
2519 else /* Other DBG registers have to be transfered by the debug handler */
2521 /* send CP read request (command 0x40) */
2522 xscale_send_u32(target
, 0x40);
2524 /* send CP register number */
2525 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2527 /* read register value */
2528 xscale_read_tx(target
, 1);
2529 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2538 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2540 xscale_reg_t
*arch_info
= reg
->arch_info
;
2541 target_t
*target
= arch_info
->target
;
2542 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2543 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2544 u32 value
= buf_get_u32(buf
, 0, 32);
2546 /* DCSR, TX and RX are accessible via JTAG */
2547 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2549 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2550 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2552 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2554 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2555 return xscale_write_rx(arch_info
->target
);
2557 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2559 /* can't write to TX register (debug-handler -> host) */
2562 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2564 /* can't (explicitly) write to TXRXCTRL register */
2567 else /* Other DBG registers have to be transfered by the debug handler */
2569 /* send CP write request (command 0x41) */
2570 xscale_send_u32(target
, 0x41);
2572 /* send CP register number */
2573 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2575 /* send CP register value */
2576 xscale_send_u32(target
, value
);
2577 buf_set_u32(reg
->value
, 0, 32, value
);
2583 /* convenience wrapper to access XScale specific registers */
2584 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2588 buf_set_u32(buf
, 0, 32, value
);
2590 return xscale_set_reg(reg
, buf
);
2593 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2595 /* get pointers to arch-specific information */
2596 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2597 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2598 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2599 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2601 /* send CP write request (command 0x41) */
2602 xscale_send_u32(target
, 0x41);
2604 /* send CP register number */
2605 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2607 /* send CP register value */
2608 xscale_send_u32(target
, value
);
2609 buf_set_u32(dcsr
->value
, 0, 32, value
);
2614 int xscale_read_trace(target_t
*target
)
2616 /* get pointers to arch-specific information */
2617 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2618 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2619 xscale_trace_data_t
**trace_data_p
;
2621 /* 258 words from debug handler
2622 * 256 trace buffer entries
2623 * 2 checkpoint addresses
2625 u32 trace_buffer
[258];
2626 int is_address
[256];
2629 if (target
->state
!= TARGET_HALTED
)
2631 LOG_WARNING("target must be stopped to read trace data");
2632 return ERROR_TARGET_NOT_HALTED
;
2635 /* send read trace buffer command (command 0x61) */
2636 xscale_send_u32(target
, 0x61);
2638 /* receive trace buffer content */
2639 xscale_receive(target
, trace_buffer
, 258);
2641 /* parse buffer backwards to identify address entries */
2642 for (i
= 255; i
>= 0; i
--)
2645 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2646 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2649 is_address
[--i
] = 1;
2651 is_address
[--i
] = 1;
2653 is_address
[--i
] = 1;
2655 is_address
[--i
] = 1;
2660 /* search first non-zero entry */
2661 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2666 LOG_DEBUG("no trace data collected");
2667 return ERROR_XSCALE_NO_TRACE_DATA
;
2670 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2673 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2674 (*trace_data_p
)->next
= NULL
;
2675 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2676 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2677 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2678 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2679 (*trace_data_p
)->depth
= 256 - j
;
2681 for (i
= j
; i
< 256; i
++)
2683 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2685 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2687 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2693 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2695 /* get pointers to arch-specific information */
2696 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2697 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2704 if (!xscale
->trace
.image
)
2705 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2707 /* search for the section the current instruction belongs to */
2708 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2710 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2711 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2720 /* current instruction couldn't be found in the image */
2721 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2724 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2727 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2728 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2729 4, buf
, &size_read
)) != ERROR_OK
)
2731 LOG_ERROR("error while reading instruction: %i", retval
);
2732 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2734 opcode
= target_buffer_get_u32(target
, buf
);
2735 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2737 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2740 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2741 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2742 2, buf
, &size_read
)) != ERROR_OK
)
2744 LOG_ERROR("error while reading instruction: %i", retval
);
2745 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2747 opcode
= target_buffer_get_u16(target
, buf
);
2748 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2752 LOG_ERROR("BUG: unknown core state encountered");
2759 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2761 /* if there are less than four entries prior to the indirect branch message
2762 * we can't extract the address */
2768 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2769 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2774 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2776 /* get pointers to arch-specific information */
2777 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2778 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2781 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2790 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2795 for (i
= 0; i
< trace_data
->depth
; i
++)
2801 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2804 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2806 case 0: /* Exceptions */
2814 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2816 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2817 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2819 case 8: /* Direct Branch */
2822 case 9: /* Indirect Branch */
2824 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2829 case 13: /* Checkpointed Indirect Branch */
2830 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2833 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2834 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2835 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2837 /* explicit fall-through */
2838 case 12: /* Checkpointed Direct Branch */
2843 next_pc
= trace_data
->chkpt0
;
2846 else if (chkpt
== 1)
2849 next_pc
= trace_data
->chkpt0
;
2854 LOG_WARNING("more than two checkpointed branches encountered");
2857 case 15: /* Roll-over */
2860 default: /* Reserved */
2861 command_print(cmd_ctx
, "--- reserved trace message ---");
2862 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2866 if (xscale
->trace
.pc_ok
)
2868 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2869 arm_instruction_t instruction
;
2871 if ((exception
== 6) || (exception
== 7))
2873 /* IRQ or FIQ exception, no instruction executed */
2877 while (executed
-- >= 0)
2879 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2881 /* can't continue tracing with no image available */
2882 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2886 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2888 /* TODO: handle incomplete images */
2892 /* a precise abort on a load to the PC is included in the incremental
2893 * word count, other instructions causing data aborts are not included
2895 if ((executed
== 0) && (exception
== 4)
2896 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2898 if ((instruction
.type
== ARM_LDM
)
2899 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2903 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2904 && (instruction
.info
.load_store
.Rd
!= 15))
2910 /* only the last instruction executed
2911 * (the one that caused the control flow change)
2912 * could be a taken branch
2914 if (((executed
== -1) && (branch
== 1)) &&
2915 (((instruction
.type
== ARM_B
) ||
2916 (instruction
.type
== ARM_BL
) ||
2917 (instruction
.type
== ARM_BLX
)) &&
2918 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2920 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2924 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2926 command_print(cmd_ctx
, "%s", instruction
.text
);
2934 xscale
->trace
.current_pc
= next_pc
;
2935 xscale
->trace
.pc_ok
= 1;
2939 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2941 arm_instruction_t instruction
;
2942 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2944 /* can't continue tracing with no image available */
2945 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2949 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2951 /* TODO: handle incomplete images */
2954 command_print(cmd_ctx
, "%s", instruction
.text
);
2957 trace_data
= trace_data
->next
;
2963 void xscale_build_reg_cache(target_t
*target
)
2965 /* get pointers to arch-specific information */
2966 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2967 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2969 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2970 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2972 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2974 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2975 armv4_5
->core_cache
= (*cache_p
);
2977 /* register a register arch-type for XScale dbg registers only once */
2978 if (xscale_reg_arch_type
== -1)
2979 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2981 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2982 cache_p
= &(*cache_p
)->next
;
2984 /* fill in values for the xscale reg cache */
2985 (*cache_p
)->name
= "XScale registers";
2986 (*cache_p
)->next
= NULL
;
2987 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2988 (*cache_p
)->num_regs
= num_regs
;
2990 for (i
= 0; i
< num_regs
; i
++)
2992 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2993 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2994 (*cache_p
)->reg_list
[i
].dirty
= 0;
2995 (*cache_p
)->reg_list
[i
].valid
= 0;
2996 (*cache_p
)->reg_list
[i
].size
= 32;
2997 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
2998 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
2999 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
3000 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
3001 arch_info
[i
] = xscale_reg_arch_info
[i
];
3002 arch_info
[i
].target
= target
;
3005 xscale
->reg_cache
= (*cache_p
);
3008 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
3013 int xscale_quit(void)
3018 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, jtag_tap_t
*tap
, const char *variant
)
3020 armv4_5_common_t
*armv4_5
;
3021 u32 high_reset_branch
, low_reset_branch
;
3024 armv4_5
= &xscale
->armv4_5_common
;
3026 /* store architecture specfic data (none so far) */
3027 xscale
->arch_info
= NULL
;
3028 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3030 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3031 xscale
->variant
= strdup(variant
);
3033 /* prepare JTAG information for the new target */
3034 xscale
->jtag_info
.tap
= tap
;
3036 xscale
->jtag_info
.dbgrx
= 0x02;
3037 xscale
->jtag_info
.dbgtx
= 0x10;
3038 xscale
->jtag_info
.dcsr
= 0x09;
3039 xscale
->jtag_info
.ldic
= 0x07;
3041 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3042 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3043 (strcmp(xscale
->variant
, "pxa26x") == 0))
3045 xscale
->jtag_info
.ir_length
= 5;
3047 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3048 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3049 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3050 (strcmp(xscale
->variant
, "ixp46x") == 0))
3052 xscale
->jtag_info
.ir_length
= 7;
3055 /* the debug handler isn't installed (and thus not running) at this time */
3056 xscale
->handler_installed
= 0;
3057 xscale
->handler_running
= 0;
3058 xscale
->handler_address
= 0xfe000800;
3060 /* clear the vectors we keep locally for reference */
3061 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3062 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3064 /* no user-specified vectors have been configured yet */
3065 xscale
->static_low_vectors_set
= 0x0;
3066 xscale
->static_high_vectors_set
= 0x0;
3068 /* calculate branches to debug handler */
3069 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3070 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3072 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3073 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3075 for (i
= 1; i
<= 7; i
++)
3077 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3078 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3081 /* 64kB aligned region used for DCache cleaning */
3082 xscale
->cache_clean_address
= 0xfffe0000;
3084 xscale
->hold_rst
= 0;
3085 xscale
->external_debug_break
= 0;
3087 xscale
->ibcr_available
= 2;
3088 xscale
->ibcr0_used
= 0;
3089 xscale
->ibcr1_used
= 0;
3091 xscale
->dbr_available
= 2;
3092 xscale
->dbr0_used
= 0;
3093 xscale
->dbr1_used
= 0;
3095 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3096 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3098 xscale
->vector_catch
= 0x1;
3100 xscale
->trace
.capture_status
= TRACE_IDLE
;
3101 xscale
->trace
.data
= NULL
;
3102 xscale
->trace
.image
= NULL
;
3103 xscale
->trace
.buffer_enabled
= 0;
3104 xscale
->trace
.buffer_fill
= 0;
3106 /* prepare ARMv4/5 specific information */
3107 armv4_5
->arch_info
= xscale
;
3108 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3109 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3110 armv4_5
->full_context
= xscale_full_context
;
3112 armv4_5_init_arch_info(target
, armv4_5
);
3114 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3115 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3116 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3117 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3118 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3119 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3120 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3121 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3126 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3127 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
)
3129 xscale_common_t
*xscale
= calloc(1,sizeof(xscale_common_t
));
3131 xscale_init_arch_info(target
, xscale
, target
->tap
, target
->variant
);
3132 xscale_build_reg_cache(target
);
3137 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3139 target_t
*target
= NULL
;
3140 armv4_5_common_t
*armv4_5
;
3141 xscale_common_t
*xscale
;
3143 u32 handler_address
;
3147 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3151 if ((target
= get_target(args
[0])) == NULL
)
3153 LOG_ERROR("target '%s' not defined", args
[0]);
3157 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3162 handler_address
= strtoul(args
[1], NULL
, 0);
3164 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3165 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3167 xscale
->handler_address
= handler_address
;
3171 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3178 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3180 target_t
*target
= NULL
;
3181 armv4_5_common_t
*armv4_5
;
3182 xscale_common_t
*xscale
;
3184 u32 cache_clean_address
;
3188 return ERROR_COMMAND_SYNTAX_ERROR
;
3191 target
= get_target(args
[0]);
3194 LOG_ERROR("target '%s' not defined", args
[0]);
3198 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3203 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3205 if (cache_clean_address
& 0xffff)
3207 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3211 xscale
->cache_clean_address
= cache_clean_address
;
3217 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3219 target_t
*target
= get_current_target(cmd_ctx
);
3220 armv4_5_common_t
*armv4_5
;
3221 xscale_common_t
*xscale
;
3223 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3228 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3231 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
3233 armv4_5_common_t
*armv4_5
;
3234 xscale_common_t
*xscale
;
3241 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3245 u32 ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3254 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3256 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3257 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3259 if (target
->state
!= TARGET_HALTED
)
3261 LOG_ERROR("Target not halted");
3262 return ERROR_TARGET_INVALID
;
3264 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3268 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3270 target_t
*target
= get_current_target(cmd_ctx
);
3271 armv4_5_common_t
*armv4_5
;
3272 xscale_common_t
*xscale
;
3274 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3279 if (target
->state
!= TARGET_HALTED
)
3281 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3287 if (strcmp("enable", args
[0]) == 0)
3289 xscale_enable_mmu_caches(target
, 1, 0, 0);
3290 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3292 else if (strcmp("disable", args
[0]) == 0)
3294 xscale_disable_mmu_caches(target
, 1, 0, 0);
3295 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3299 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3304 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3306 target_t
*target
= get_current_target(cmd_ctx
);
3307 armv4_5_common_t
*armv4_5
;
3308 xscale_common_t
*xscale
;
3309 int icache
= 0, dcache
= 0;
3311 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3316 if (target
->state
!= TARGET_HALTED
)
3318 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3322 if (strcmp(cmd
, "icache") == 0)
3324 else if (strcmp(cmd
, "dcache") == 0)
3329 if (strcmp("enable", args
[0]) == 0)
3331 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3334 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3336 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3338 else if (strcmp("disable", args
[0]) == 0)
3340 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3343 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3345 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3350 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3353 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3358 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3360 target_t
*target
= get_current_target(cmd_ctx
);
3361 armv4_5_common_t
*armv4_5
;
3362 xscale_common_t
*xscale
;
3364 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3371 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3375 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3376 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3377 xscale_write_dcsr(target
, -1, -1);
3380 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3386 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3388 target_t
*target
= get_current_target(cmd_ctx
);
3389 armv4_5_common_t
*armv4_5
;
3390 xscale_common_t
*xscale
;
3393 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3398 if (target
->state
!= TARGET_HALTED
)
3400 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3404 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3406 xscale_trace_data_t
*td
, *next_td
;
3407 xscale
->trace
.buffer_enabled
= 1;
3409 /* free old trace data */
3410 td
= xscale
->trace
.data
;
3420 xscale
->trace
.data
= NULL
;
3422 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3424 xscale
->trace
.buffer_enabled
= 0;
3427 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3430 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3432 xscale
->trace
.buffer_fill
= 1;
3434 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3436 xscale
->trace
.buffer_fill
= -1;
3439 if (xscale
->trace
.buffer_enabled
)
3441 /* if we enable the trace buffer in fill-once
3442 * mode we know the address of the first instruction */
3443 xscale
->trace
.pc_ok
= 1;
3444 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3448 /* otherwise the address is unknown, and we have no known good PC */
3449 xscale
->trace
.pc_ok
= 0;
3452 command_print(cmd_ctx
, "trace buffer %s (%s)",
3453 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3454 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3456 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3457 if (xscale
->trace
.buffer_fill
>= 0)
3458 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3460 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3465 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3468 armv4_5_common_t
*armv4_5
;
3469 xscale_common_t
*xscale
;
3473 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3477 target
= get_current_target(cmd_ctx
);
3479 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3484 if (xscale
->trace
.image
)
3486 image_close(xscale
->trace
.image
);
3487 free(xscale
->trace
.image
);
3488 command_print(cmd_ctx
, "previously loaded image found and closed");
3491 xscale
->trace
.image
= malloc(sizeof(image_t
));
3492 xscale
->trace
.image
->base_address_set
= 0;
3493 xscale
->trace
.image
->start_address_set
= 0;
3495 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3498 xscale
->trace
.image
->base_address_set
= 1;
3499 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3503 xscale
->trace
.image
->base_address_set
= 0;
3506 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3508 free(xscale
->trace
.image
);
3509 xscale
->trace
.image
= NULL
;
3516 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3518 target_t
*target
= get_current_target(cmd_ctx
);
3519 armv4_5_common_t
*armv4_5
;
3520 xscale_common_t
*xscale
;
3521 xscale_trace_data_t
*trace_data
;
3524 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3529 if (target
->state
!= TARGET_HALTED
)
3531 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3537 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3541 trace_data
= xscale
->trace
.data
;
3545 command_print(cmd_ctx
, "no trace data collected");
3549 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3558 fileio_write_u32(&file
, trace_data
->chkpt0
);
3559 fileio_write_u32(&file
, trace_data
->chkpt1
);
3560 fileio_write_u32(&file
, trace_data
->last_instruction
);
3561 fileio_write_u32(&file
, trace_data
->depth
);
3563 for (i
= 0; i
< trace_data
->depth
; i
++)
3564 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3566 trace_data
= trace_data
->next
;
3569 fileio_close(&file
);
3574 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3576 target_t
*target
= get_current_target(cmd_ctx
);
3577 armv4_5_common_t
*armv4_5
;
3578 xscale_common_t
*xscale
;
3580 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3585 xscale_analyze_trace(target
, cmd_ctx
);
3590 int xscale_handle_cp15(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3592 target_t
*target
= get_current_target(cmd_ctx
);
3593 armv4_5_common_t
*armv4_5
;
3594 xscale_common_t
*xscale
;
3596 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3601 if (target
->state
!= TARGET_HALTED
)
3603 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3610 reg_no
= strtoul(args
[0], NULL
, 0);
3611 /*translate from xscale cp15 register no to openocd register*/
3615 reg_no
= XSCALE_MAINID
;
3618 reg_no
= XSCALE_CTRL
;
3621 reg_no
= XSCALE_TTB
;
3624 reg_no
= XSCALE_DAC
;
3627 reg_no
= XSCALE_FSR
;
3630 reg_no
= XSCALE_FAR
;
3633 reg_no
= XSCALE_PID
;
3636 reg_no
= XSCALE_CPACCESS
;
3639 command_print(cmd_ctx
, "invalid register number");
3640 return ERROR_INVALID_ARGUMENTS
;
3642 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3649 /* read cp15 control register */
3650 xscale_get_reg(reg
);
3651 value
= buf_get_u32(reg
->value
, 0, 32);
3652 command_print(cmd_ctx
, "%s (/%i): 0x%x", reg
->name
, reg
->size
, value
);
3657 u32 value
= strtoul(args
[1], NULL
, 0);
3659 /* send CP write request (command 0x41) */
3660 xscale_send_u32(target
, 0x41);
3662 /* send CP register number */
3663 xscale_send_u32(target
, reg_no
);
3665 /* send CP register value */
3666 xscale_send_u32(target
, value
);
3668 /* execute cpwait to ensure outstanding operations complete */
3669 xscale_send_u32(target
, 0x53);
3673 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3679 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3681 command_t
*xscale_cmd
;
3683 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3685 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3686 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3688 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3689 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3690 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3691 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3693 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3695 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3697 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3698 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3699 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3700 COMMAND_EXEC
, "load image from <file> [base address]");
3702 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3704 armv4_5_register_commands(cmd_ctx
);