src/flash/s3c24xx_regs_nand.h

   1 /***************************************************************************
   2  *   Copyright (C) 2004, 2005 by Simtec Electronics                        *
   3  *   linux@simtec.co.uk                                                    *
   4  *   http://www.simtec.co.uk/products/SWLINUX/                             *
   5  *                                                                         *
   6  *   This program is free software; you can redistribute it and/or modify  *
   7  *   it under the terms of the GNU General Public License as published by  *
   8  *   the Free Software Foundation; version 2 of the License.               *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 /*
  22  * S3C2410 NAND register definitions
  23  */
  24
  25 #ifndef __ASM_ARM_REGS_NAND
  26 #define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
  27
  28 #define S3C2410_NFREG(x) (x)
  29
  30 #define S3C2410_NFCONF  S3C2410_NFREG(0x00)
  31 #define S3C2410_NFCMD   S3C2410_NFREG(0x04)
  32 #define S3C2410_NFADDR  S3C2410_NFREG(0x08)
  33 #define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
  34 #define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
  35 #define S3C2410_NFECC   S3C2410_NFREG(0x14)
  36
  37 #define S3C2440_NFCONT   S3C2410_NFREG(0x04)
  38 #define S3C2440_NFCMD    S3C2410_NFREG(0x08)
  39 #define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
  40 #define S3C2440_NFDATA   S3C2410_NFREG(0x10)
  41 #define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
  42 #define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
  43 #define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
  44 #define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
  45 #define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
  46 #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
  47 #define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
  48 #define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
  49 #define S3C2440_NFSECC   S3C2410_NFREG(0x34)
  50 #define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
  51 #define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
  52
  53 #define S3C2412_NFSBLK          S3C2410_NFREG(0x20)
  54 #define S3C2412_NFEBLK          S3C2410_NFREG(0x24)
  55 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
  56 #define S3C2412_NFMECC_ERR0     S3C2410_NFREG(0x2C)
  57 #define S3C2412_NFMECC_ERR1     S3C2410_NFREG(0x30)
  58 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
  59 #define S3C2412_NFMECC1         S3C2410_NFREG(0x38)
  60 #define S3C2412_NFSECC          S3C2410_NFREG(0x3C)
  61
  62 #define S3C2410_NFCONF_EN          (1 << 15)
  63 #define S3C2410_NFCONF_512BYTE     (1 << 14)
  64 #define S3C2410_NFCONF_4STEP       (1 << 13)
  65 #define S3C2410_NFCONF_INITECC     (1 << 12)
  66 #define S3C2410_NFCONF_nFCE        (1 << 11)
  67 #define S3C2410_NFCONF_TACLS(x)    ((x) << 8)
  68 #define S3C2410_NFCONF_TWRPH0(x)   ((x) << 4)
  69 #define S3C2410_NFCONF_TWRPH1(x)   ((x) << 0)
  70
  71 #define S3C2410_NFSTAT_BUSY        (1 << 0)
  72
  73 #define S3C2440_NFCONF_BUSWIDTH_8       (0 << 0)
  74 #define S3C2440_NFCONF_BUSWIDTH_16      (1 << 0)
  75 #define S3C2440_NFCONF_ADVFLASH         (1 << 3)
  76 #define S3C2440_NFCONF_TACLS(x)         ((x) << 12)
  77 #define S3C2440_NFCONF_TWRPH0(x)        ((x) << 8)
  78 #define S3C2440_NFCONF_TWRPH1(x)        ((x) << 4)
  79
  80 #define S3C2440_NFCONT_LOCKTIGHT        (1 << 13)
  81 #define S3C2440_NFCONT_SOFTLOCK         (1 << 12)
  82 #define S3C2440_NFCONT_ILLEGALACC_EN    (1 << 10)
  83 #define S3C2440_NFCONT_RNBINT_EN        (1 << 9)
  84 #define S3C2440_NFCONT_RN_FALLING       (1 << 8)
  85 #define S3C2440_NFCONT_SPARE_ECCLOCK    (1 << 6)
  86 #define S3C2440_NFCONT_MAIN_ECCLOCK     (1 << 5)
  87 #define S3C2440_NFCONT_INITECC          (1 << 4)
  88 #define S3C2440_NFCONT_nFCE                     (1 << 1)
  89 #define S3C2440_NFCONT_ENABLE           (1 << 0)
  90
  91 #define S3C2440_NFSTAT_READY            (1 << 0)
  92 #define S3C2440_NFSTAT_nCE                      (1 << 1)
  93 #define S3C2440_NFSTAT_RnB_CHANGE       (1 << 2)
  94 #define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1 << 3)
  95
  96 #define S3C2412_NFCONF_NANDBOOT         (1 << 31)
  97 #define S3C2412_NFCONF_ECCCLKCON        (1 << 30)
  98 #define S3C2412_NFCONF_ECC_MLC          (1 << 24)
  99 #define S3C2412_NFCONF_TACLS_MASK       (7 << 12)       /* 1 extra bit of Tacls */
 100
 101 #define S3C2412_NFCONT_ECC4_DIRWR       (1 << 18)
 102 #define S3C2412_NFCONT_LOCKTIGHT        (1 << 17)
 103 #define S3C2412_NFCONT_SOFTLOCK         (1 << 16)
 104 #define S3C2412_NFCONT_ECC4_ENCINT      (1 << 13)
 105 #define S3C2412_NFCONT_ECC4_DECINT      (1 << 12)
 106 #define S3C2412_NFCONT_MAIN_ECC_LOCK    (1 << 7)
 107 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1 << 5)
 108 #define S3C2412_NFCONT_nFCE1            (1 << 2)
 109 #define S3C2412_NFCONT_nFCE0            (1 << 1)
 110
 111 #define S3C2412_NFSTAT_ECC_ENCDONE      (1 << 7)
 112 #define S3C2412_NFSTAT_ECC_DECDONE      (1 << 6)
 113 #define S3C2412_NFSTAT_ILLEGAL_ACCESS   (1 << 5)
 114 #define S3C2412_NFSTAT_RnB_CHANGE       (1 << 4)
 115 #define S3C2412_NFSTAT_nFCE1            (1 << 3)
 116 #define S3C2412_NFSTAT_nFCE0            (1 << 2)
 117 #define S3C2412_NFSTAT_Res1                     (1 << 1)
 118 #define S3C2412_NFSTAT_READY            (1 << 0)
 119
 120 #define S3C2412_NFECCERR_SERRDATA(x)    (((x) >> 21) & 0xf)
 121 #define S3C2412_NFECCERR_SERRBIT(x)             (((x) >> 18) & 0x7)
 122 #define S3C2412_NFECCERR_MERRDATA(x)    (((x) >> 7) & 0x3ff)
 123 #define S3C2412_NFECCERR_MERRBIT(x)             (((x) >> 4) & 0x7)
 124 #define S3C2412_NFECCERR_SPARE_ERR(x)   (((x) >> 2) & 0x3)
 125 #define S3C2412_NFECCERR_MAIN_ERR(x)    (((x) >> 2) & 0x3)
 126 #define S3C2412_NFECCERR_NONE           (0)
 127 #define S3C2412_NFECCERR_1BIT           (1)
 128 #define S3C2412_NFECCERR_MULTIBIT       (2)
 129 #define S3C2412_NFECCERR_ECCAREA        (3)
 130
 131 #endif /* __ASM_ARM_REGS_NAND */
 132