1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
23 ***************************************************************************/
30 #include "mips_ejtag.h"
31 #include "mips32_dmaacc.h"
33 void mips_ejtag_set_instr(struct mips_ejtag
*ejtag_info
, int new_instr
)
37 tap
= ejtag_info
->tap
;
40 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != (uint32_t)new_instr
) {
41 struct scan_field field
;
44 field
.num_bits
= tap
->ir_length
;
46 buf_set_u32(t
, 0, field
.num_bits
, new_instr
);
47 field
.in_value
= NULL
;
49 jtag_add_ir_scan(tap
, &field
, TAP_IDLE
);
53 int mips_ejtag_get_idcode(struct mips_ejtag
*ejtag_info
, uint32_t *idcode
)
55 struct scan_field field
;
58 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IDCODE
);
61 field
.out_value
= NULL
;
64 jtag_add_dr_scan(ejtag_info
->tap
, 1, &field
, TAP_IDLE
);
67 retval
= jtag_execute_queue();
68 if (retval
!= ERROR_OK
) {
69 LOG_ERROR("register read failed");
73 *idcode
= buf_get_u32(field
.in_value
, 0, 32);
78 static int mips_ejtag_get_impcode(struct mips_ejtag
*ejtag_info
, uint32_t *impcode
)
80 struct scan_field field
;
83 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IMPCODE
);
86 field
.out_value
= NULL
;
89 jtag_add_dr_scan(ejtag_info
->tap
, 1, &field
, TAP_IDLE
);
92 retval
= jtag_execute_queue();
93 if (retval
!= ERROR_OK
) {
94 LOG_ERROR("register read failed");
98 *impcode
= buf_get_u32(field
.in_value
, 0, 32);
103 void mips_ejtag_add_scan_96(struct mips_ejtag
*ejtag_info
, uint32_t ctrl
, uint32_t data
, uint8_t *in_scan_buf
)
105 assert(ejtag_info
->tap
!= NULL
);
106 struct jtag_tap
*tap
= ejtag_info
->tap
;
108 struct scan_field field
;
109 uint8_t out_scan
[12];
111 /* processor access "all" register 96 bit */
114 field
.out_value
= out_scan
;
115 buf_set_u32(out_scan
, 0, 32, ctrl
);
116 buf_set_u32(out_scan
+ 4, 0, 32, data
);
117 buf_set_u32(out_scan
+ 8, 0, 32, 0);
119 field
.in_value
= in_scan_buf
;
121 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
126 int mips_ejtag_drscan_32(struct mips_ejtag
*ejtag_info
, uint32_t *data
)
128 struct jtag_tap
*tap
;
129 tap
= ejtag_info
->tap
;
132 struct scan_field field
;
138 buf_set_u32(t
, 0, field
.num_bits
, *data
);
141 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
143 retval
= jtag_execute_queue();
144 if (retval
!= ERROR_OK
) {
145 LOG_ERROR("register read failed");
149 *data
= buf_get_u32(field
.in_value
, 0, 32);
156 void mips_ejtag_drscan_32_out(struct mips_ejtag
*ejtag_info
, uint32_t data
)
159 struct jtag_tap
*tap
;
160 tap
= ejtag_info
->tap
;
163 struct scan_field field
;
167 buf_set_u32(t
, 0, field
.num_bits
, data
);
169 field
.in_value
= NULL
;
171 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
174 int mips_ejtag_drscan_8(struct mips_ejtag
*ejtag_info
, uint32_t *data
)
176 struct jtag_tap
*tap
;
177 tap
= ejtag_info
->tap
;
180 struct scan_field field
;
181 uint8_t t
[4] = {0, 0, 0, 0}, r
[4];
186 buf_set_u32(t
, 0, field
.num_bits
, *data
);
189 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
191 retval
= jtag_execute_queue();
192 if (retval
!= ERROR_OK
) {
193 LOG_ERROR("register read failed");
197 *data
= buf_get_u32(field
.in_value
, 0, 32);
202 void mips_ejtag_drscan_8_out(struct mips_ejtag
*ejtag_info
, uint8_t data
)
204 struct jtag_tap
*tap
;
205 tap
= ejtag_info
->tap
;
208 struct scan_field field
;
211 field
.out_value
= &data
;
212 field
.in_value
= NULL
;
214 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
217 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
218 int mips_ejtag_config_step(struct mips_ejtag
*ejtag_info
, int enable_step
)
220 struct pracc_queue_info ctx
= {.max_code
= 7};
221 pracc_queue_init(&ctx
);
222 if (ctx
.retval
!= ERROR_OK
)
225 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
226 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
228 pracc_add(&ctx
, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
230 pracc_add(&ctx
, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
231 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
232 pracc_add(&ctx
, 0, MIPS32_B(NEG16((ctx
.code_count
+ 1)))); /* jump to start */
233 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
235 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
237 pracc_queue_free(&ctx
);
242 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
243 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
244 * For example bcm7401 and others. At leas on some
245 * CPUs, DebugMode wont start if this bit is not removed.
247 static int disable_dcr_mp(struct mips_ejtag
*ejtag_info
)
252 retval
= mips32_dmaacc_read_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
253 if (retval
!= ERROR_OK
)
256 dcr
&= ~EJTAG_DCR_MP
;
257 retval
= mips32_dmaacc_write_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
258 if (retval
!= ERROR_OK
)
262 LOG_ERROR("Failed to remove DCR MPbit!");
266 int mips_ejtag_enter_debug(struct mips_ejtag
*ejtag_info
)
269 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
271 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
272 if (disable_dcr_mp(ejtag_info
) != ERROR_OK
)
276 /* set debug break bit */
277 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_JTAGBRK
;
278 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
280 /* break bit will be cleared by hardware */
281 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
282 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
283 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32
"", ejtag_ctrl
);
284 if ((ejtag_ctrl
& EJTAG_CTRL_BRKST
) == 0)
289 LOG_ERROR("Failed to enter Debug Mode!");
293 int mips_ejtag_exit_debug(struct mips_ejtag
*ejtag_info
)
295 uint32_t instr
= MIPS32_DRET
;
296 struct pracc_queue_info ctx
= {.max_code
= 1, .pracc_list
= &instr
, .code_count
= 1, .store_count
= 0};
298 /* execute our dret instruction */
299 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
301 /* pic32mx workaround, false pending at low core clock */
302 jtag_add_sleep(1000);
306 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
309 static void mips_ejtag_init_mmr(struct mips_ejtag
*ejtag_info
)
311 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
312 ejtag_info
->ejtag_ibs_addr
= EJTAG_V20_IBS
;
313 ejtag_info
->ejtag_iba0_addr
= EJTAG_V20_IBA0
;
314 ejtag_info
->ejtag_ibc_offs
= EJTAG_V20_IBC_OFFS
;
315 ejtag_info
->ejtag_ibm_offs
= EJTAG_V20_IBM_OFFS
;
317 ejtag_info
->ejtag_dbs_addr
= EJTAG_V20_DBS
;
318 ejtag_info
->ejtag_dba0_addr
= EJTAG_V20_DBA0
;
319 ejtag_info
->ejtag_dbc_offs
= EJTAG_V20_DBC_OFFS
;
320 ejtag_info
->ejtag_dbm_offs
= EJTAG_V20_DBM_OFFS
;
321 ejtag_info
->ejtag_dbv_offs
= EJTAG_V20_DBV_OFFS
;
323 ejtag_info
->ejtag_iba_step_size
= EJTAG_V20_IBAn_STEP
;
324 ejtag_info
->ejtag_dba_step_size
= EJTAG_V20_DBAn_STEP
;
326 ejtag_info
->ejtag_ibs_addr
= EJTAG_V25_IBS
;
327 ejtag_info
->ejtag_iba0_addr
= EJTAG_V25_IBA0
;
328 ejtag_info
->ejtag_ibm_offs
= EJTAG_V25_IBM_OFFS
;
329 ejtag_info
->ejtag_ibasid_offs
= EJTAG_V25_IBASID_OFFS
;
330 ejtag_info
->ejtag_ibc_offs
= EJTAG_V25_IBC_OFFS
;
332 ejtag_info
->ejtag_dbs_addr
= EJTAG_V25_DBS
;
333 ejtag_info
->ejtag_dba0_addr
= EJTAG_V25_DBA0
;
334 ejtag_info
->ejtag_dbm_offs
= EJTAG_V25_DBM_OFFS
;
335 ejtag_info
->ejtag_dbasid_offs
= EJTAG_V25_DBASID_OFFS
;
336 ejtag_info
->ejtag_dbc_offs
= EJTAG_V25_DBC_OFFS
;
337 ejtag_info
->ejtag_dbv_offs
= EJTAG_V25_DBV_OFFS
;
339 ejtag_info
->ejtag_iba_step_size
= EJTAG_V25_IBAn_STEP
;
340 ejtag_info
->ejtag_dba_step_size
= EJTAG_V25_DBAn_STEP
;
345 int mips_ejtag_init(struct mips_ejtag
*ejtag_info
)
349 retval
= mips_ejtag_get_impcode(ejtag_info
, &ejtag_info
->impcode
);
350 if (retval
!= ERROR_OK
)
352 LOG_DEBUG("impcode: 0x%8.8" PRIx32
"", ejtag_info
->impcode
);
354 /* get ejtag version */
355 ejtag_info
->ejtag_version
= ((ejtag_info
->impcode
>> 29) & 0x07);
357 switch (ejtag_info
->ejtag_version
) {
358 case EJTAG_VERSION_20
:
359 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
361 case EJTAG_VERSION_25
:
362 LOG_DEBUG("EJTAG: Version 2.5 Detected");
364 case EJTAG_VERSION_26
:
365 LOG_DEBUG("EJTAG: Version 2.6 Detected");
367 case EJTAG_VERSION_31
:
368 LOG_DEBUG("EJTAG: Version 3.1 Detected");
370 case EJTAG_VERSION_41
:
371 LOG_DEBUG("EJTAG: Version 4.1 Detected");
373 case EJTAG_VERSION_51
:
374 LOG_DEBUG("EJTAG: Version 5.1 Detected");
377 LOG_DEBUG("EJTAG: Unknown Version Detected");
380 LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
381 ejtag_info
->impcode
& EJTAG_IMP_R3K
? " R3k" : " R4k",
382 ejtag_info
->impcode
& EJTAG_IMP_DINT
? " DINT" : "",
383 ejtag_info
->impcode
& (1 << 22) ? " ASID_8" : "",
384 ejtag_info
->impcode
& (1 << 21) ? " ASID_6" : "",
385 ejtag_info
->impcode
& EJTAG_IMP_MIPS16
? " MIPS16" : "",
386 ejtag_info
->impcode
& EJTAG_IMP_NODMA
? " noDMA" : " DMA",
387 ejtag_info
->impcode
& EJTAG_DCR_MIPS64
? " MIPS64" : " MIPS32");
389 if ((ejtag_info
->impcode
& EJTAG_IMP_NODMA
) == 0)
390 LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
392 /* set initial state for ejtag control reg */
393 ejtag_info
->ejtag_ctrl
= EJTAG_CTRL_ROCC
| EJTAG_CTRL_PRACC
| EJTAG_CTRL_PROBEN
| EJTAG_CTRL_SETDEV
;
394 ejtag_info
->fast_access_save
= -1;
396 mips_ejtag_init_mmr(ejtag_info
);
401 int mips_ejtag_fastdata_scan(struct mips_ejtag
*ejtag_info
, int write_t
, uint32_t *data
)
403 struct jtag_tap
*tap
;
405 tap
= ejtag_info
->tap
;
408 struct scan_field fields
[2];
410 uint8_t t
[4] = {0, 0, 0, 0};
412 /* fastdata 1-bit register */
413 fields
[0].num_bits
= 1;
414 fields
[0].out_value
= &spracc
;
415 fields
[0].in_value
= NULL
;
417 /* processor access data register 32 bit */
418 fields
[1].num_bits
= 32;
419 fields
[1].out_value
= t
;
422 fields
[1].in_value
= NULL
;
423 buf_set_u32(t
, 0, 32, *data
);
425 fields
[1].in_value
= (uint8_t *) data
;
427 jtag_add_dr_scan(tap
, 2, fields
, TAP_IDLE
);
429 if (!write_t
&& data
)
430 jtag_add_callback(mips_le_to_h_u32
,
431 (jtag_callback_data_t
) data
);