src/target/arm_dpm.c

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation, Inc.,
  17  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"            /* REVISIT to become arm.h */
  25 #include "arm_dpm.h"
  26 #include <jtag/jtag.h>
  27 #include "register.h"
  28 #include "breakpoints.h"
  29 #include "target_type.h"
  30
  31
  32 /**
  33  * @file
  34  * Implements various ARM DPM operations using architectural debug registers.
  35  * These routines layer over core-specific communication methods to cope with
  36  * implementation differences between cores like ARM1136 and Cortex-A8.
  37  */
  38
  39 /*----------------------------------------------------------------------*/
  40
  41 /*
  42  * Coprocessor support
  43  */
  44
  45 /* Read coprocessor */
  46 static int dpm_mrc(struct target *target, int cpnum,
  47                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  48                 uint32_t *value)
  49 {
  50         struct arm *arm = target_to_arm(target);
  51         struct arm_dpm *dpm = arm->dpm;
  52         int retval;
  53
  54         retval = dpm->prepare(dpm);
  55         if (retval != ERROR_OK)
  56                 return retval;
  57
  58         LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
  59
  60         /* read coprocessor register into R0; return via DCC */
  61         retval = dpm->instr_read_data_r0(dpm,
  62                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  63                         value);
  64
  65         /* (void) */ dpm->finish(dpm);
  66         return retval;
  67 }
  68
  69 static int dpm_mcr(struct target *target, int cpnum,
  70                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  71                 uint32_t value)
  72 {
  73         struct arm *arm = target_to_arm(target);
  74         struct arm_dpm *dpm = arm->dpm;
  75         int retval;
  76
  77         retval = dpm->prepare(dpm);
  78         if (retval != ERROR_OK)
  79                 return retval;
  80
  81         LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
  82
  83         /* read DCC into r0; then write coprocessor register from R0 */
  84         retval = dpm->instr_write_data_r0(dpm,
  85                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  86                         value);
  87
  88         /* (void) */ dpm->finish(dpm);
  89         return retval;
  90 }
  91
  92 /*----------------------------------------------------------------------*/
  93
  94 /*
  95  * Register access utilities
  96  */
  97
  98 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  99  * Routines *must* restore the original mode before returning!!
 100  */
 101 static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
 102 {
 103         int retval;
 104         uint32_t cpsr;
 105
 106         /* restore previous mode */
 107         if (mode == ARMV4_5_MODE_ANY)
 108                 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 109
 110         /* else force to the specified mode */
 111         else
 112                 cpsr = mode;
 113
 114         retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 115
 116         if (dpm->instr_cpsr_sync)
 117                 retval = dpm->instr_cpsr_sync(dpm);
 118
 119         return retval;
 120 }
 121
 122 /* just read the register -- rely on the core mode being right */
 123 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 124 {
 125         uint32_t value;
 126         int retval;
 127
 128         switch (regnum) {
 129         case 0 ... 14:
 130                 /* return via DCC:  "MCR p14, 0, Rnum, c0, c5, 0" */
 131                 retval = dpm->instr_read_data_dcc(dpm,
 132                                 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
 133                                 &value);
 134                 break;
 135         case 15:        /* PC */
 136                 /* "MOV r0, pc"; then return via DCC */
 137                 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
 138
 139                 /* NOTE: this seems like a slightly awkward place to update
 140                  * this value ... but if the PC gets written (the only way
 141                  * to change what we compute), the arch spec says subsequent
 142                  * reads return values which are "unpredictable".  So this
 143                  * is always right except in those broken-by-intent cases.
 144                  */
 145                 switch (dpm->arm->core_state) {
 146                 case ARMV4_5_STATE_ARM:
 147                         value -= 8;
 148                         break;
 149                 case ARMV4_5_STATE_THUMB:
 150                 case ARM_STATE_THUMB_EE:
 151                         value -= 4;
 152                         break;
 153                 case ARMV4_5_STATE_JAZELLE:
 154                         /* core-specific ... ? */
 155                         LOG_WARNING("Jazelle PC adjustment unknown");
 156                         break;
 157                 }
 158                 break;
 159         default:
 160                 /* 16: "MRS r0, CPSR"; then return via DCC
 161                  * 17: "MRS r0, SPSR"; then return via DCC
 162                  */
 163                 retval = dpm->instr_read_data_r0(dpm,
 164                                 ARMV4_5_MRS(0, regnum & 1),
 165                                 &value);
 166                 break;
 167         }
 168
 169         if (retval == ERROR_OK) {
 170                 buf_set_u32(r->value, 0, 32, value);
 171                 r->valid = true;
 172                 r->dirty = false;
 173                 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
 174         }
 175
 176         return retval;
 177 }
 178
 179 /* just write the register -- rely on the core mode being right */
 180 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 181 {
 182         int retval;
 183         uint32_t value = buf_get_u32(r->value, 0, 32);
 184
 185         switch (regnum) {
 186         case 0 ... 14:
 187                 /* load register from DCC:  "MRC p14, 0, Rnum, c0, c5, 0" */
 188                 retval = dpm->instr_write_data_dcc(dpm,
 189                                 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
 190                                 value);
 191                 break;
 192         case 15:        /* PC */
 193                 /* read r0 from DCC; then "MOV pc, r0" */
 194                 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
 195                 break;
 196         default:
 197                 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
 198                  * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
 199                  */
 200                 retval = dpm->instr_write_data_r0(dpm,
 201                                 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 202                                 value);
 203
 204                 if (regnum == 16 && dpm->instr_cpsr_sync)
 205                         retval = dpm->instr_cpsr_sync(dpm);
 206
 207                 break;
 208         }
 209
 210         if (retval == ERROR_OK) {
 211                 r->dirty = false;
 212                 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
 213         }
 214
 215         return retval;
 216 }
 217
 218 /**
 219  * Read basic registers of the the current context:  R0 to R15, and CPSR;
 220  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
 221  * In normal operation this is called on entry to halting debug state,
 222  * possibly after some other operations supporting restore of debug state
 223  * or making sure the CPU is fully idle (drain write buffer, etc).
 224  */
 225 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 226 {
 227         struct arm *arm = dpm->arm;
 228         uint32_t cpsr;
 229         int retval;
 230         struct reg *r;
 231
 232         retval = dpm->prepare(dpm);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235
 236         /* read R0 first (it's used for scratch), then CPSR */
 237         r = arm->core_cache->reg_list + 0;
 238         if (!r->valid) {
 239                 retval = dpm_read_reg(dpm, r, 0);
 240                 if (retval != ERROR_OK)
 241                         goto fail;
 242         }
 243         r->dirty = true;
 244
 245         retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
 246         if (retval != ERROR_OK)
 247                 goto fail;
 248
 249         /* update core mode and state, plus shadow mapping for R8..R14 */
 250         arm_set_cpsr(arm, cpsr);
 251
 252         /* REVISIT we can probably avoid reading R1..R14, saving time... */
 253         for (unsigned i = 1; i < 16; i++) {
 254                 r = arm_reg_current(arm, i);
 255                 if (r->valid)
 256                         continue;
 257
 258                 retval = dpm_read_reg(dpm, r, i);
 259                 if (retval != ERROR_OK)
 260                         goto fail;
 261         }
 262
 263         /* NOTE: SPSR ignored (if it's even relevant). */
 264
 265         /* REVISIT the debugger can trigger various exceptions.  See the
 266          * ARMv7A architecture spec, section C5.7, for more info about
 267          * what defenses are needed; v6 debug has the most issues.
 268          */
 269
 270 fail:
 271         /* (void) */ dpm->finish(dpm);
 272         return retval;
 273 }
 274
 275 /**
 276  * Writes all modified core registers for all processor modes.  In normal
 277  * operation this is called on exit from halting debug state.
 278  *
 279  * @param dpm: represents the processor
 280  * @param bpwp: true ensures breakpoints and watchpoints are set,
 281  *      false ensures they are cleared
 282  */
 283 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 284 {
 285         struct arm *arm = dpm->arm;
 286         struct reg_cache *cache = arm->core_cache;
 287         int retval;
 288         bool did_write;
 289
 290         retval = dpm->prepare(dpm);
 291         if (retval != ERROR_OK)
 292                 goto done;
 293
 294         /* enable/disable watchpoints */
 295         for (unsigned i = 0; i < dpm->nwp; i++) {
 296                 struct dpm_wp *dwp = dpm->dwp + i;
 297                 struct watchpoint *wp = dwp->wp;
 298                 bool disable;
 299
 300                 /* Avoid needless I/O ... leave watchpoints alone
 301                  * unless they're removed, or need updating because
 302                  * of single-stepping or running debugger code.
 303                  */
 304                 if (!wp) {
 305                         if (!dwp->dirty)
 306                                 continue;
 307                         dwp->dirty = false;
 308                         /* removed or startup; we must disable it */
 309                         disable = true;
 310                 } else if (bpwp) {
 311                         if (!dwp->dirty)
 312                                 continue;
 313                         /* disabled, but we must set it */
 314                         dwp->dirty = disable = false;
 315                         wp->set = true;
 316                 } else {
 317                         if (!wp->set)
 318                                 continue;
 319                         /* set, but we must temporarily disable it */
 320                         dwp->dirty = disable = true;
 321                         wp->set = false;
 322                 }
 323
 324                 if (disable)
 325                         retval = dpm->bpwp_disable(dpm, 16 + i);
 326                 else
 327                         retval = dpm->bpwp_enable(dpm, 16 + i,
 328                                         wp->address, dwp->control);
 329
 330                 if (retval != ERROR_OK)
 331                         LOG_ERROR("%s: can't %s HW watchpoint %d",
 332                                         target_name(arm->target),
 333                                         disable ? "disable" : "enable",
 334                                         i);
 335         }
 336
 337         /* NOTE:  writes to breakpoint and watchpoint registers might
 338          * be queued, and need (efficient/batched) flushing later.
 339          */
 340
 341         /* Scan the registers until we find one that's both dirty and
 342          * eligible for flushing.  Flush that and everything else that
 343          * shares the same core mode setting.  Typically this won't
 344          * actually find anything to do...
 345          */
 346         do {
 347                 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
 348
 349                 did_write = false;
 350
 351                 /* check everything except our scratch register R0 */
 352                 for (unsigned i = 1; i < cache->num_regs; i++) {
 353                         struct arm_reg *r;
 354                         unsigned regnum;
 355
 356                         /* also skip PC, CPSR, and non-dirty */
 357                         if (i == 15)
 358                                 continue;
 359                         if (arm->cpsr == cache->reg_list + i)
 360                                 continue;
 361                         if (!cache->reg_list[i].dirty)
 362                                 continue;
 363
 364                         r = cache->reg_list[i].arch_info;
 365                         regnum = r->num;
 366
 367                         /* may need to pick and set a mode */
 368                         if (!did_write) {
 369                                 enum armv4_5_mode tmode;
 370
 371                                 did_write = true;
 372                                 mode = tmode = r->mode;
 373
 374                                 /* cope with special cases */
 375                                 switch (regnum) {
 376                                 case 8 ... 12:
 377                                         /* r8..r12 "anything but FIQ" case;
 378                                          * we "know" core mode is accurate
 379                                          * since we haven't changed it yet
 380                                          */
 381                                         if (arm->core_mode == ARMV4_5_MODE_FIQ
 382                                                         && ARMV4_5_MODE_ANY
 383                                                                 != mode)
 384                                                 tmode = ARMV4_5_MODE_USR;
 385                                         break;
 386                                 case 16:
 387                                         /* SPSR */
 388                                         regnum++;
 389                                         break;
 390                                 }
 391
 392                                 /* REVISIT error checks */
 393                                 if (tmode != ARMV4_5_MODE_ANY)
 394                                         retval = dpm_modeswitch(dpm, tmode);
 395                         }
 396                         if (r->mode != mode)
 397                                 continue;
 398
 399                         retval = dpm_write_reg(dpm,
 400                                         &cache->reg_list[i],
 401                                         regnum);
 402
 403                 }
 404
 405         } while (did_write);
 406
 407         /* Restore original CPSR ... assuming either that we changed it,
 408          * or it's dirty.  Must write PC to ensure the return address is
 409          * defined, and must not write it before CPSR.
 410          */
 411         retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
 412         arm->cpsr->dirty = false;
 413
 414         retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
 415         cache->reg_list[15].dirty = false;
 416
 417         /* flush R0 -- it's *very* dirty by now */
 418         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 419         cache->reg_list[0].dirty = false;
 420
 421         /* (void) */ dpm->finish(dpm);
 422 done:
 423         return retval;
 424 }
 425
 426 /* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
 427  * specified register ... works around flakiness from ARM core calls.
 428  * Caller already filtered out SPSR access; mode is never MODE_SYS
 429  * or MODE_ANY.
 430  */
 431 static enum armv4_5_mode dpm_mapmode(struct arm *arm,
 432                 unsigned num, enum armv4_5_mode mode)
 433 {
 434         enum armv4_5_mode amode = arm->core_mode;
 435
 436         /* don't switch if the mode is already correct */
 437         if (amode == ARMV4_5_MODE_SYS)
 438                  amode = ARMV4_5_MODE_USR;
 439         if (mode == amode)
 440                 return ARMV4_5_MODE_ANY;
 441
 442         switch (num) {
 443         /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
 444         case 0 ... 7:
 445         case 15:
 446         case 16:
 447                 break;
 448         /* r8..r12 aren't shadowed for anything except FIQ */
 449         case 8 ... 12:
 450                 if (mode == ARMV4_5_MODE_FIQ)
 451                         return mode;
 452                 break;
 453         /* r13/sp, and r14/lr are always shadowed */
 454         case 13:
 455         case 14:
 456                 return mode;
 457         default:
 458                 LOG_WARNING("invalid register #%u", num);
 459                 break;
 460         }
 461         return ARMV4_5_MODE_ANY;
 462 }
 463
 464
 465 /*
 466  * Standard ARM register accessors ... there are three methods
 467  * in "struct arm", to support individual read/write and bulk read
 468  * of registers.
 469  */
 470
 471 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 472                 int regnum, enum armv4_5_mode mode)
 473 {
 474         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 475         int retval;
 476
 477         if (regnum < 0 || regnum > 16)
 478                 return ERROR_INVALID_ARGUMENTS;
 479
 480         if (regnum == 16) {
 481                 if (mode != ARMV4_5_MODE_ANY)
 482                         regnum = 17;
 483         } else
 484                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 485
 486         /* REVISIT what happens if we try to read SPSR in a core mode
 487          * which has no such register?
 488          */
 489
 490         retval = dpm->prepare(dpm);
 491         if (retval != ERROR_OK)
 492                 return retval;
 493
 494         if (mode != ARMV4_5_MODE_ANY) {
 495                 retval = dpm_modeswitch(dpm, mode);
 496                 if (retval != ERROR_OK)
 497                         goto fail;
 498         }
 499
 500         retval = dpm_read_reg(dpm, r, regnum);
 501         /* always clean up, regardless of error */
 502
 503         if (mode != ARMV4_5_MODE_ANY)
 504                 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
 505
 506 fail:
 507         /* (void) */ dpm->finish(dpm);
 508         return retval;
 509 }
 510
 511 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
 512                 int regnum, enum armv4_5_mode mode, uint32_t value)
 513 {
 514         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 515         int retval;
 516
 517
 518         if (regnum < 0 || regnum > 16)
 519                 return ERROR_INVALID_ARGUMENTS;
 520
 521         if (regnum == 16) {
 522                 if (mode != ARMV4_5_MODE_ANY)
 523                         regnum = 17;
 524         } else
 525                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 526
 527         /* REVISIT what happens if we try to write SPSR in a core mode
 528          * which has no such register?
 529          */
 530
 531         retval = dpm->prepare(dpm);
 532         if (retval != ERROR_OK)
 533                 return retval;
 534
 535         if (mode != ARMV4_5_MODE_ANY) {
 536                 retval = dpm_modeswitch(dpm, mode);
 537                 if (retval != ERROR_OK)
 538                         goto fail;
 539         }
 540
 541         retval = dpm_write_reg(dpm, r, regnum);
 542         /* always clean up, regardless of error */
 543
 544         if (mode != ARMV4_5_MODE_ANY)
 545                 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
 546
 547 fail:
 548         /* (void) */ dpm->finish(dpm);
 549         return retval;
 550 }
 551
 552 static int arm_dpm_full_context(struct target *target)
 553 {
 554         struct arm *arm = target_to_arm(target);
 555         struct arm_dpm *dpm = arm->dpm;
 556         struct reg_cache *cache = arm->core_cache;
 557         int retval;
 558         bool did_read;
 559
 560         retval = dpm->prepare(dpm);
 561         if (retval != ERROR_OK)
 562                 goto done;
 563
 564         do {
 565                 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
 566
 567                 did_read = false;
 568
 569                 /* We "know" arm_dpm_read_current_registers() was called so
 570                  * the unmapped registers (R0..R7, PC, AND CPSR) and some
 571                  * view of R8..R14 are current.  We also "know" oddities of
 572                  * register mapping: special cases for R8..R12 and SPSR.
 573                  *
 574                  * Pick some mode with unread registers and read them all.
 575                  * Repeat until done.
 576                  */
 577                 for (unsigned i = 0; i < cache->num_regs; i++) {
 578                         struct arm_reg *r;
 579
 580                         if (cache->reg_list[i].valid)
 581                                 continue;
 582                         r = cache->reg_list[i].arch_info;
 583
 584                         /* may need to pick a mode and set CPSR */
 585                         if (!did_read) {
 586                                 did_read = true;
 587                                 mode = r->mode;
 588
 589                                 /* For R8..R12 when we've entered debug
 590                                  * state in FIQ mode... patch mode.
 591                                  */
 592                                 if (mode == ARMV4_5_MODE_ANY)
 593                                         mode = ARMV4_5_MODE_USR;
 594
 595                                 /* REVISIT error checks */
 596                                 retval = dpm_modeswitch(dpm, mode);
 597                         }
 598                         if (r->mode != mode)
 599                                 continue;
 600
 601                         /* CPSR was read, so "R16" must mean SPSR */
 602                         retval = dpm_read_reg(dpm,
 603                                         &cache->reg_list[i],
 604                                         (r->num == 16) ? 17 : r->num);
 605
 606                 }
 607
 608         } while (did_read);
 609
 610         retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
 611         /* (void) */ dpm->finish(dpm);
 612 done:
 613         return retval;
 614 }
 615
 616
 617 /*----------------------------------------------------------------------*/
 618
 619 /*
 620  * Breakpoint and Watchpoint support.
 621  *
 622  * Hardware {break,watch}points are usually left active, to minimize
 623  * debug entry/exit costs.  When they are set or cleared, it's done in
 624  * batches.  Also, DPM-conformant hardware can update debug registers
 625  * regardless of whether the CPU is running or halted ... though that
 626  * fact isn't currently leveraged.
 627  */
 628
 629 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
 630                 struct watchpoint *wp)
 631 {
 632         uint32_t addr = wp->address;
 633         uint32_t control;
 634
 635         /* this hardware doesn't support data value matching or masking */
 636         if (wp->value || wp->mask != ~(uint32_t)0) {
 637                 LOG_DEBUG("watchpoint values and masking not supported");
 638                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 639         }
 640
 641         control = (1 << 0)      /* enable */
 642                 | (3 << 1);     /* both user and privileged access */
 643
 644         switch (wp->rw) {
 645         case WPT_READ:
 646                 control |= 1 << 3;
 647                 break;
 648         case WPT_WRITE:
 649                 control |= 2 << 3;
 650                 break;
 651         case WPT_ACCESS:
 652                 control |= 3 << 3;
 653                 break;
 654         }
 655
 656         /* Match 1, 2, or all 4 byte addresses in this word.
 657          *
 658          * FIXME:  v7 hardware allows lengths up to 2 GB, and has eight
 659          * byte address select bits.  Support larger wp->length, if addr
 660          * is suitably aligned.
 661          */
 662         switch (wp->length) {
 663         case 1:
 664                 control |= (1 << (addr & 3)) << 5;
 665                 addr &= ~3;
 666                 break;
 667         case 2:
 668                 /* require 2-byte alignment */
 669                 if (!(addr & 1)) {
 670                         control |= (3 << (addr & 2)) << 5;
 671                         break;
 672                 }
 673                 /* FALL THROUGH */
 674         case 4:
 675                 /* require 4-byte alignment */
 676                 if (!(addr & 3)) {
 677                         control |= 0xf << 5;
 678                         break;
 679                 }
 680                 /* FALL THROUGH */
 681         default:
 682                 LOG_DEBUG("bad watchpoint length or alignment");
 683                 return ERROR_INVALID_ARGUMENTS;
 684         }
 685
 686         /* other control bits:
 687          * bits 9:12 == 0 ... only checking up to four byte addresses (v7 only)
 688          * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
 689          * bit 20 == 0 ... not linked to a context ID
 690          * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
 691          */
 692
 693         dpm->dwp[index].wp = wp;
 694         dpm->dwp[index].control = control;
 695         dpm->dwp[index].dirty = true;
 696
 697         /* hardware is updated in write_dirty_registers() */
 698         return ERROR_OK;
 699 }
 700
 701
 702 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
 703 {
 704         struct arm *arm = target_to_arm(target);
 705         struct arm_dpm *dpm = arm->dpm;
 706         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 707
 708         if (dpm->bpwp_enable) {
 709                 for (unsigned i = 0; i < dpm->nwp; i++) {
 710                         if (!dpm->dwp[i].wp) {
 711                                 retval = dpm_watchpoint_setup(dpm, i, wp);
 712                                 break;
 713                         }
 714                 }
 715         }
 716
 717         return retval;
 718 }
 719
 720 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 721 {
 722         struct arm *arm = target_to_arm(target);
 723         struct arm_dpm *dpm = arm->dpm;
 724         int retval = ERROR_INVALID_ARGUMENTS;
 725
 726         for (unsigned i = 0; i < dpm->nwp; i++) {
 727                 if (dpm->dwp[i].wp == wp) {
 728                         dpm->dwp[i].wp = NULL;
 729                         dpm->dwp[i].dirty = true;
 730
 731                         /* hardware is updated in write_dirty_registers() */
 732                         retval = ERROR_OK;
 733                         break;
 734                 }
 735         }
 736
 737         return retval;
 738 }
 739
 740 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 741 {
 742         switch (dpm->arm->core_state) {
 743         case ARMV4_5_STATE_ARM:
 744                 addr -= 8;
 745                 break;
 746         case ARMV4_5_STATE_THUMB:
 747         case ARM_STATE_THUMB_EE:
 748                 addr -= 4;
 749                 break;
 750         case ARMV4_5_STATE_JAZELLE:
 751                 /* ?? */
 752                 break;
 753         }
 754         dpm->wp_pc = addr;
 755 }
 756
 757 /*----------------------------------------------------------------------*/
 758
 759 /*
 760  * Other debug and support utilities
 761  */
 762
 763 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
 764 {
 765         struct target *target = dpm->arm->target;
 766
 767         dpm->dscr = dscr;
 768
 769         /* Examine debug reason */
 770         switch (DSCR_ENTRY(dscr)) {
 771         case 6:         /* Data abort (v6 only) */
 772         case 7:         /* Prefetch abort (v6 only) */
 773                 /* FALL THROUGH -- assume a v6 core in abort mode */
 774         case 0:         /* HALT request from debugger */
 775         case 4:         /* EDBGRQ */
 776                 target->debug_reason = DBG_REASON_DBGRQ;
 777                 break;
 778         case 1:         /* HW breakpoint */
 779         case 3:         /* SW BKPT */
 780         case 5:         /* vector catch */
 781                 target->debug_reason = DBG_REASON_BREAKPOINT;
 782                 break;
 783         case 2:         /* asynch watchpoint */
 784         case 10:        /* precise watchpoint */
 785                 target->debug_reason = DBG_REASON_WATCHPOINT;
 786                 break;
 787         default:
 788                 target->debug_reason = DBG_REASON_UNDEFINED;
 789                 break;
 790         }
 791 }
 792
 793 /*----------------------------------------------------------------------*/
 794
 795 /*
 796  * Setup and management support.
 797  */
 798
 799 /**
 800  * Hooks up this DPM to its associated target; call only once.
 801  * Initially this only covers the register cache.
 802  *
 803  * Oh, and watchpoints.  Yeah.
 804  */
 805 int arm_dpm_setup(struct arm_dpm *dpm)
 806 {
 807         struct arm *arm = dpm->arm;
 808         struct target *target = arm->target;
 809         struct reg_cache *cache;
 810
 811         arm->dpm = dpm;
 812
 813         /* register access setup */
 814         arm->full_context = arm_dpm_full_context;
 815         arm->read_core_reg = arm_dpm_read_core_reg;
 816         arm->write_core_reg = arm_dpm_write_core_reg;
 817
 818         cache = armv4_5_build_reg_cache(target, arm);
 819         if (!cache)
 820                 return ERROR_FAIL;
 821
 822         *register_get_last_cache_p(&target->reg_cache) = cache;
 823
 824         /* coprocessor access setup */
 825         arm->mrc = dpm_mrc;
 826         arm->mcr = dpm_mcr;
 827
 828         /* breakpoint and watchpoint setup */
 829         target->type->add_watchpoint = dpm_add_watchpoint;
 830         target->type->remove_watchpoint = dpm_remove_watchpoint;
 831
 832         /* FIXME add breakpoint support */
 833         /* FIXME add vector catch support */
 834
 835         dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
 836         dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
 837
 838         dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
 839         dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
 840
 841         if (!dpm->dbp || !dpm->dwp) {
 842                 free(dpm->dbp);
 843                 free(dpm->dwp);
 844                 return ERROR_FAIL;
 845         }
 846
 847         LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
 848                         target_name(target), dpm->nbp, dpm->nwp);
 849
 850         /* REVISIT ... and some of those breakpoints could match
 851          * execution context IDs...
 852          */
 853
 854         return ERROR_OK;
 855 }
 856
 857 /**
 858  * Reinitializes DPM state at the beginning of a new debug session
 859  * or after a reset which may have affected the debug module.
 860  */
 861 int arm_dpm_initialize(struct arm_dpm *dpm)
 862 {
 863         /* Disable all breakpoints and watchpoints at startup. */
 864         if (dpm->bpwp_disable) {
 865                 unsigned i;
 866
 867                 for (i = 0; i < dpm->nbp; i++)
 868                         (void) dpm->bpwp_disable(dpm, i);
 869                 for (i = 0; i < dpm->nwp; i++)
 870                         (void) dpm->bpwp_disable(dpm, 16 + i);
 871         } else
 872                 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
 873                         target_name(dpm->arm->target));
 874
 875         return ERROR_OK;
 876 }