src/jtag/aice/aice_port.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 by Andes Technology                                *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
   9 #define OPENOCD_JTAG_AICE_AICE_PORT_H
  10
  11 #include <target/nds32_edm.h>
  12
  13 #define AICE_MAX_NUM_CORE      (0x10)
  14
  15 #define ERROR_AICE_DISCONNECT  (-200)
  16 #define ERROR_AICE_TIMEOUT     (-201)
  17
  18 enum aice_target_state_s {
  19         AICE_DISCONNECT = 0,
  20         AICE_TARGET_DETACH,
  21         AICE_TARGET_UNKNOWN,
  22         AICE_TARGET_RUNNING,
  23         AICE_TARGET_HALTED,
  24         AICE_TARGET_RESET,
  25         AICE_TARGET_DEBUG_RUNNING,
  26 };
  27
  28 enum aice_srst_type_s {
  29         AICE_SRST = 0x1,
  30         AICE_RESET_HOLD = 0x8,
  31 };
  32
  33 enum aice_target_endian {
  34         AICE_LITTLE_ENDIAN = 0,
  35         AICE_BIG_ENDIAN,
  36 };
  37
  38 enum aice_api_s {
  39         AICE_OPEN = 0x0,
  40         AICE_CLOSE,
  41         AICE_RESET,
  42         AICE_IDCODE,
  43         AICE_SET_JTAG_CLOCK,
  44         AICE_ASSERT_SRST,
  45         AICE_RUN,
  46         AICE_HALT,
  47         AICE_STEP,
  48         AICE_READ_REG,
  49         AICE_WRITE_REG,
  50         AICE_READ_REG_64,
  51         AICE_WRITE_REG_64,
  52         AICE_READ_MEM_UNIT,
  53         AICE_WRITE_MEM_UNIT,
  54         AICE_READ_MEM_BULK,
  55         AICE_WRITE_MEM_BULK,
  56         AICE_READ_DEBUG_REG,
  57         AICE_WRITE_DEBUG_REG,
  58         AICE_STATE,
  59         AICE_MEMORY_ACCESS,
  60         AICE_MEMORY_MODE,
  61         AICE_READ_TLB,
  62         AICE_CACHE_CTL,
  63         AICE_SET_RETRY_TIMES,
  64         AICE_PROGRAM_EDM,
  65         AICE_SET_COMMAND_MODE,
  66         AICE_EXECUTE,
  67         AICE_SET_CUSTOM_SRST_SCRIPT,
  68         AICE_SET_CUSTOM_TRST_SCRIPT,
  69         AICE_SET_CUSTOM_RESTART_SCRIPT,
  70         AICE_SET_COUNT_TO_CHECK_DBGER,
  71         AICE_SET_DATA_ENDIAN,
  72 };
  73
  74 enum aice_error_s {
  75         AICE_OK,
  76         AICE_ACK,
  77         AICE_ERROR,
  78 };
  79
  80 enum aice_cache_ctl_type {
  81         AICE_CACHE_CTL_L1D_INVALALL = 0,
  82         AICE_CACHE_CTL_L1D_VA_INVAL,
  83         AICE_CACHE_CTL_L1D_WBALL,
  84         AICE_CACHE_CTL_L1D_VA_WB,
  85         AICE_CACHE_CTL_L1I_INVALALL,
  86         AICE_CACHE_CTL_L1I_VA_INVAL,
  87 };
  88
  89 enum aice_command_mode {
  90         AICE_COMMAND_MODE_NORMAL,
  91         AICE_COMMAND_MODE_PACK,
  92         AICE_COMMAND_MODE_BATCH,
  93 };
  94
  95 struct aice_port_param_s {
  96         /** */
  97         const char *device_desc;
  98         /** */
  99         uint16_t vid;
 100         /** */
 101         uint16_t pid;
 102         /** */
 103         char *adapter_name;
 104 };
 105
 106 struct aice_port_s {
 107         /** */
 108         uint32_t coreid;
 109         /** */
 110         const struct aice_port *port;
 111 };
 112
 113 /** */
 114 extern struct aice_port_api_s aice_usb_layout_api;
 115
 116 /** */
 117 struct aice_port_api_s {
 118         /** */
 119         int (*open)(struct aice_port_param_s *param);
 120         /** */
 121         int (*close)(void);
 122         /** */
 123         int (*reset)(void);
 124         /** */
 125         int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 126         /** */
 127         int (*set_jtag_clock)(uint32_t a_clock);
 128         /** */
 129         int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
 130         /** */
 131         int (*run)(uint32_t coreid);
 132         /** */
 133         int (*halt)(uint32_t coreid);
 134         /** */
 135         int (*step)(uint32_t coreid);
 136         /** */
 137         int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
 138         /** */
 139         int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
 140         /** */
 141         int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
 142         /** */
 143         int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
 144         /** */
 145         int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 146                         uint32_t count, uint8_t *buffer);
 147         /** */
 148         int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 149                         uint32_t count, const uint8_t *buffer);
 150         /** */
 151         int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 152                         uint8_t *buffer);
 153         /** */
 154         int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 155                         const uint8_t *buffer);
 156         /** */
 157         int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
 158         /** */
 159         int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
 160
 161         /** */
 162         int (*state)(uint32_t coreid, enum aice_target_state_s *state);
 163
 164         /** */
 165         int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
 166         /** */
 167         int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
 168
 169         /** */
 170         int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
 171
 172         /** */
 173         int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
 174
 175         /** */
 176         int (*set_retry_times)(uint32_t a_retry_times);
 177
 178         /** */
 179         int (*program_edm)(uint32_t coreid, char *command_sequence);
 180
 181         /** */
 182         int (*set_command_mode)(enum aice_command_mode command_mode);
 183
 184         /** */
 185         int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
 186
 187         /** */
 188         int (*set_custom_srst_script)(const char *script);
 189
 190         /** */
 191         int (*set_custom_trst_script)(const char *script);
 192
 193         /** */
 194         int (*set_custom_restart_script)(const char *script);
 195
 196         /** */
 197         int (*set_count_to_check_dbger)(uint32_t count_to_check);
 198
 199         /** */
 200         int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
 201
 202         /** */
 203         int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
 204                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 205 };
 206
 207 #define AICE_PORT_UNKNOWN       0
 208 #define AICE_PORT_AICE_USB      1
 209 #define AICE_PORT_AICE_PIPE     2
 210
 211 /** */
 212 struct aice_port {
 213         /** */
 214         const char *name;
 215         /** */
 216         int type;
 217         /** */
 218         struct aice_port_api_s *const api;
 219 };
 220
 221 /** */
 222 const struct aice_port *aice_port_get_list(void);
 223
 224 #endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */