1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
12 ***************************************************************************/
14 #ifndef OPENOCD_TARGET_CORTEX_M_H
15 #define OPENOCD_TARGET_CORTEX_M_H
18 #include "helper/bits.h"
20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
22 #define SYSTEM_CONTROL_BASE 0x400FE000
24 #define ITM_TER0 0xE0000E00
25 #define ITM_TPR 0xE0000E40
26 #define ITM_TCR 0xE0000E80
27 #define ITM_TCR_ITMENA_BIT BIT(0)
28 #define ITM_TCR_BUSY_BIT BIT(23)
29 #define ITM_LAR 0xE0000FB0
30 #define ITM_LAR_KEY 0xC5ACCE55
32 #define CPUID 0xE000ED00
34 #define ARM_CPUID_IMPLEMENTOR_POS 24
35 #define ARM_CPUID_IMPLEMENTOR_MASK (0xFF << ARM_CPUID_IMPLEMENTOR_POS)
36 #define ARM_CPUID_PARTNO_POS 4
37 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
39 #define ARM_MAKE_CPUID(impl, partno) ((((impl) << ARM_CPUID_IMPLEMENTOR_POS) & ARM_CPUID_IMPLEMENTOR_MASK) | \
40 (((partno) << ARM_CPUID_PARTNO_POS) & ARM_CPUID_PARTNO_MASK))
42 /** Known Arm Cortex masked CPU Ids
43 * This includes the implementor and part number, but _not_ the revision or
46 enum cortex_m_impl_part
{
47 CORTEX_M_PARTNO_INVALID
,
48 STAR_MC1_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0x132), /* FIXME - confirm implementor! */
49 CORTEX_M0_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC20),
50 CORTEX_M1_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC21),
51 CORTEX_M3_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC23),
52 CORTEX_M4_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC24),
53 CORTEX_M7_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC27),
54 CORTEX_M0P_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xC60),
55 CORTEX_M23_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xD20),
56 CORTEX_M33_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xD21),
57 CORTEX_M35P_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xD31),
58 CORTEX_M55_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM
, 0xD22),
59 INFINEON_SLX2_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_INFINEON
, 0xDB0),
60 REALTEK_M200_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK
, 0xd20),
61 REALTEK_M300_PARTNO
= ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK
, 0xd22),
64 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
65 #define CORTEX_M_F_HAS_FPV4 BIT(0)
66 #define CORTEX_M_F_HAS_FPV5 BIT(1)
67 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
69 struct cortex_m_part_info
{
70 enum cortex_m_impl_part impl_part
;
76 /* Debug Control Block */
77 #define DCB_DHCSR 0xE000EDF0
78 #define DCB_DCRSR 0xE000EDF4
79 #define DCB_DCRDR 0xE000EDF8
80 #define DCB_DEMCR 0xE000EDFC
81 #define DCB_DSCSR 0xE000EE08
83 #define DAUTHSTATUS 0xE000EFB8
84 #define DAUTHSTATUS_SID_MASK 0x00000030
86 #define DCRSR_WNR BIT(16)
88 #define DWT_CTRL 0xE0001000
89 #define DWT_CYCCNT 0xE0001004
90 #define DWT_PCSR 0xE000101C
91 #define DWT_COMP0 0xE0001020
92 #define DWT_MASK0 0xE0001024
93 #define DWT_FUNCTION0 0xE0001028
94 #define DWT_DEVARCH 0xE0001FBC
96 #define DWT_DEVARCH_ARMV8M_V2_0 0x101A02
97 #define DWT_DEVARCH_ARMV8M_V2_1 0x111A02
99 #define FP_CTRL 0xE0002000
100 #define FP_REMAP 0xE0002004
101 #define FP_COMP0 0xE0002008
102 #define FP_COMP1 0xE000200C
103 #define FP_COMP2 0xE0002010
104 #define FP_COMP3 0xE0002014
105 #define FP_COMP4 0xE0002018
106 #define FP_COMP5 0xE000201C
107 #define FP_COMP6 0xE0002020
108 #define FP_COMP7 0xE0002024
110 #define FPU_CPACR 0xE000ED88
111 #define FPU_FPCCR 0xE000EF34
112 #define FPU_FPCAR 0xE000EF38
113 #define FPU_FPDSCR 0xE000EF3C
115 #define TPIU_SSPSR 0xE0040000
116 #define TPIU_CSPSR 0xE0040004
117 #define TPIU_ACPR 0xE0040010
118 #define TPIU_SPPR 0xE00400F0
119 #define TPIU_FFSR 0xE0040300
120 #define TPIU_FFCR 0xE0040304
121 #define TPIU_FSCR 0xE0040308
123 /* Maximum SWO prescaler value. */
124 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
126 /* DCB_DHCSR bit and field definitions */
127 #define DBGKEY (0xA05Ful << 16)
128 #define C_DEBUGEN BIT(0)
129 #define C_HALT BIT(1)
130 #define C_STEP BIT(2)
131 #define C_MASKINTS BIT(3)
132 #define S_REGRDY BIT(16)
133 #define S_HALT BIT(17)
134 #define S_SLEEP BIT(18)
135 #define S_LOCKUP BIT(19)
136 #define S_RETIRE_ST BIT(24)
137 #define S_RESET_ST BIT(25)
139 /* DCB_DEMCR bit and field definitions */
140 #define TRCENA BIT(24)
141 #define VC_HARDERR BIT(10)
142 #define VC_INTERR BIT(9)
143 #define VC_BUSERR BIT(8)
144 #define VC_STATERR BIT(7)
145 #define VC_CHKERR BIT(6)
146 #define VC_NOCPERR BIT(5)
147 #define VC_MMERR BIT(4)
148 #define VC_CORERESET BIT(0)
150 /* DCB_DSCSR bit and field definitions */
151 #define DSCSR_CDS BIT(16)
154 #define NVIC_ICTR 0xE000E004
155 #define NVIC_ISE0 0xE000E100
156 #define NVIC_ICSR 0xE000ED04
157 #define NVIC_AIRCR 0xE000ED0C
158 #define NVIC_SHCSR 0xE000ED24
159 #define NVIC_CFSR 0xE000ED28
160 #define NVIC_MMFSRB 0xE000ED28
161 #define NVIC_BFSRB 0xE000ED29
162 #define NVIC_USFSRH 0xE000ED2A
163 #define NVIC_HFSR 0xE000ED2C
164 #define NVIC_DFSR 0xE000ED30
165 #define NVIC_MMFAR 0xE000ED34
166 #define NVIC_BFAR 0xE000ED38
167 #define NVIC_SFSR 0xE000EDE4
168 #define NVIC_SFAR 0xE000EDE8
170 /* NVIC_AIRCR bits */
171 #define AIRCR_VECTKEY (0x5FAul << 16)
172 #define AIRCR_SYSRESETREQ BIT(2)
173 #define AIRCR_VECTCLRACTIVE BIT(1)
174 #define AIRCR_VECTRESET BIT(0)
175 /* NVIC_SHCSR bits */
176 #define SHCSR_BUSFAULTENA BIT(17)
178 #define DFSR_HALTED 1
180 #define DFSR_DWTTRAP 4
181 #define DFSR_VCATCH 8
182 #define DFSR_EXTERNAL 16
185 #define FPCR_LITERAL 1
186 #define FPCR_REPLACE_REMAP (0ul << 30)
187 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
188 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
189 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
191 struct cortex_m_fp_comparator
{
195 uint32_t fpcr_address
;
198 struct cortex_m_dwt_comparator
{
203 uint32_t dwt_comparator_address
;
206 enum cortex_m_soft_reset_config
{
207 CORTEX_M_RESET_SYSRESETREQ
,
208 CORTEX_M_RESET_VECTRESET
,
211 enum cortex_m_isrmasking_mode
{
212 CORTEX_M_ISRMASK_AUTO
,
213 CORTEX_M_ISRMASK_OFF
,
215 CORTEX_M_ISRMASK_STEPONLY
,
218 struct cortex_m_common
{
219 unsigned int common_magic
;
221 struct armv7m_common armv7m
;
223 /* Context information */
225 uint32_t dcb_dhcsr_cumulated_sticky
;
226 /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
227 bool dcb_dhcsr_sticky_is_recent
;
228 uint32_t nvic_dfsr
; /* Debug Fault Status Register - shows reason for debug halt */
229 uint32_t nvic_icsr
; /* Interrupt Control State Register - shows active and pending IRQ */
231 /* Flash Patch and Breakpoint (FPB) */
232 unsigned int fp_num_lit
;
233 unsigned int fp_num_code
;
236 struct cortex_m_fp_comparator
*fp_comparator_list
;
238 /* Data Watchpoint and Trace (DWT) */
239 unsigned int dwt_num_comp
;
240 unsigned int dwt_comp_available
;
241 uint32_t dwt_devarch
;
242 struct cortex_m_dwt_comparator
*dwt_comparator_list
;
243 struct reg_cache
*dwt_cache
;
245 enum cortex_m_soft_reset_config soft_reset_config
;
246 bool vectreset_supported
;
247 enum cortex_m_isrmasking_mode isrmasking_mode
;
249 const struct cortex_m_part_info
*core_info
;
251 bool slow_register_read
; /* A register has not been ready, poll S_REGRDY */
255 /* Whether this target has the erratum that makes C_MASKINTS not apply to
256 * already pending interrupts */
257 bool maskints_erratum
;
260 static inline bool is_cortex_m_or_hla(const struct cortex_m_common
*cortex_m
)
262 return cortex_m
->common_magic
== CORTEX_M_COMMON_MAGIC
;
265 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common
*cortex_m
)
267 if (!is_cortex_m_or_hla(cortex_m
))
270 return !cortex_m
->armv7m
.is_hla_target
;
274 * @returns the pointer to the target specific struct
275 * without matching a magic number.
276 * Use in target specific service routines, where the correct
277 * type of arch_info is certain.
279 static inline struct cortex_m_common
*
280 target_to_cm(struct target
*target
)
282 return container_of(target
->arch_info
,
283 struct cortex_m_common
, armv7m
.arm
);
287 * @returns the pointer to the target specific struct
288 * or NULL if the magic number does not match.
289 * Use in a flash driver or any place where mismatch of the arch_info
292 static inline struct cortex_m_common
*
293 target_to_cortex_m_safe(struct target
*target
)
295 /* Check the parent types first to prevent peeking memory too far
296 * from arch_info pointer */
297 if (!target_to_armv7m_safe(target
))
300 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
301 if (!is_cortex_m_or_hla(cortex_m
))
308 * @returns cached value of the cpuid, masked for implementation and part.
309 * or CORTEX_M_PARTNO_INVALID if the magic number does not match
310 * or core_info is not initialised.
312 static inline enum cortex_m_impl_part
cortex_m_get_impl_part(struct target
*target
)
314 struct cortex_m_common
*cortex_m
= target_to_cortex_m_safe(target
);
316 return CORTEX_M_PARTNO_INVALID
;
318 if (!cortex_m
->core_info
)
319 return CORTEX_M_PARTNO_INVALID
;
321 return cortex_m
->core_info
->impl_part
;
324 int cortex_m_examine(struct target
*target
);
325 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
326 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
327 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
328 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
329 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
330 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
331 void cortex_m_enable_breakpoints(struct target
*target
);
332 void cortex_m_enable_watchpoints(struct target
*target
);
333 void cortex_m_deinit_target(struct target
*target
);
334 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
335 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
);
337 #endif /* OPENOCD_TARGET_CORTEX_M_H */