1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2022 by Daniel Anselmi *
6 ***************************************************************************/
14 #include "lattice_cmd.h"
16 #define ISC_PROGRAM_USERCODE 0xC2
18 #define STATUS_DONE_BIT 0x00000100
19 #define STATUS_ERROR_BITS 0x00020040
20 #define STATUS_FEA_OTP 0x00004000
21 #define STATUS_FAIL_FLAG 0x00002000
22 #define STATUS_BUSY_FLAG 0x00001000
23 #define REGISTER_ALL_BITS_1 0xffffffff
25 int lattice_ecp5_read_status(struct jtag_tap
*tap
, uint32_t *status
, uint32_t out
, bool do_idle
)
27 return lattice_read_u32_register(tap
, LSC_READ_STATUS
, status
, out
, do_idle
);
30 int lattice_ecp5_read_usercode(struct jtag_tap
*tap
, uint32_t *usercode
, uint32_t out
)
32 return lattice_read_u32_register(tap
, READ_USERCODE
, usercode
, out
, true);
35 int lattice_ecp5_write_usercode(struct lattice_pld_device
*lattice_device
, uint32_t usercode
)
37 struct jtag_tap
*tap
= lattice_device
->tap
;
41 int retval
= lattice_set_instr(tap
, ISC_ENABLE
, TAP_IDLE
);
42 if (retval
!= ERROR_OK
)
44 jtag_add_runtest(5, TAP_IDLE
);
45 jtag_add_sleep(20000);
47 retval
= lattice_set_instr(tap
, ISC_PROGRAM_USERCODE
, TAP_IDLE
);
48 if (retval
!= ERROR_OK
)
52 struct scan_field field
;
53 h_u32_to_le(buffer
, usercode
);
55 field
.out_value
= buffer
;
56 field
.in_value
= NULL
;
57 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
58 jtag_add_runtest(5, TAP_IDLE
);
61 retval
= lattice_set_instr(tap
, ISC_DISABLE
, TAP_IDLE
);
62 if (retval
!= ERROR_OK
)
64 jtag_add_runtest(5, TAP_IDLE
);
65 jtag_add_sleep(200000);
67 retval
= jtag_execute_queue();
68 if (retval
!= ERROR_OK
)
70 return lattice_verify_usercode(lattice_device
, 0x0, usercode
, REGISTER_ALL_BITS_1
);
73 static int lattice_ecp5_enable_sram_programming(struct jtag_tap
*tap
)
75 int retval
= lattice_set_instr(tap
, ISC_ENABLE
, TAP_IDLE
);
76 if (retval
!= ERROR_OK
)
79 struct scan_field field
;
82 field
.out_value
= &buffer
;
83 field
.in_value
= NULL
;
84 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
85 jtag_add_runtest(2, TAP_IDLE
);
86 jtag_add_sleep(10000);
88 return jtag_execute_queue();
91 static int lattice_ecp5_erase_sram(struct jtag_tap
*tap
)
93 int retval
= lattice_set_instr(tap
, ISC_ERASE
, TAP_IRPAUSE
);
94 if (retval
!= ERROR_OK
)
97 struct scan_field field
;
100 field
.out_value
= &buffer
;
101 field
.in_value
= NULL
;
102 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
103 jtag_add_runtest(2, TAP_IDLE
);
104 jtag_add_sleep(200000);
105 return jtag_execute_queue();
108 static int lattice_ecp5_init_address(struct jtag_tap
*tap
)
110 int retval
= lattice_set_instr(tap
, LSC_INIT_ADDRESS
, TAP_IDLE
);
111 if (retval
!= ERROR_OK
)
114 struct scan_field field
;
117 field
.out_value
= &buffer
;
118 field
.in_value
= NULL
;
119 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
120 jtag_add_runtest(2, TAP_IDLE
);
121 jtag_add_sleep(10000);
122 return jtag_execute_queue();
125 static int lattice_ecp5_program_config_map(struct jtag_tap
*tap
, struct lattice_bit_file
*bit_file
)
127 int retval
= lattice_set_instr(tap
, LSC_BITSTREAM_BURST
, TAP_IDLE
);
128 if (retval
!= ERROR_OK
)
130 jtag_add_runtest(2, TAP_IDLE
);
131 jtag_add_sleep(10000);
133 struct scan_field field
;
134 field
.num_bits
= (bit_file
->raw_bit
.length
- bit_file
->offset
) * 8;
135 field
.out_value
= bit_file
->raw_bit
.data
+ bit_file
->offset
;
136 field
.in_value
= NULL
;
137 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
138 retval
= lattice_set_instr(tap
, BYPASS
, TAP_IDLE
);
139 if (retval
!= ERROR_OK
)
141 jtag_add_runtest(100, TAP_IDLE
);
142 jtag_add_sleep(10000);
144 return jtag_execute_queue();
147 static int lattice_ecp5_exit_programming_mode(struct jtag_tap
*tap
)
149 int retval
= lattice_set_instr(tap
, ISC_DISABLE
, TAP_IDLE
);
150 if (retval
!= ERROR_OK
)
152 jtag_add_runtest(2, TAP_IDLE
);
153 jtag_add_sleep(200000);
154 retval
= lattice_set_instr(tap
, BYPASS
, TAP_IDLE
);
155 if (retval
!= ERROR_OK
)
157 jtag_add_runtest(2, TAP_IDLE
);
158 jtag_add_sleep(1000);
159 return jtag_execute_queue();
162 int lattice_ecp5_load(struct lattice_pld_device
*lattice_device
, struct lattice_bit_file
*bit_file
)
164 struct jtag_tap
*tap
= lattice_device
->tap
;
168 int retval
= lattice_preload(lattice_device
);
169 if (retval
!= ERROR_OK
)
172 retval
= lattice_ecp5_enable_sram_programming(tap
);
173 if (retval
!= ERROR_OK
)
176 const uint32_t out
= 0x0;
177 const uint32_t expected1
= 0x0;
178 const uint32_t mask1
= STATUS_ERROR_BITS
| STATUS_FEA_OTP
;
179 retval
= lattice_verify_status_register_u32(lattice_device
, out
, expected1
, mask1
, true);
180 if (retval
!= ERROR_OK
)
183 retval
= lattice_ecp5_erase_sram(tap
);
184 if (retval
!= ERROR_OK
)
187 const uint32_t mask2
= STATUS_FAIL_FLAG
| STATUS_BUSY_FLAG
;
188 retval
= lattice_verify_status_register_u32(lattice_device
, out
, expected1
, mask2
, false);
189 if (retval
!= ERROR_OK
)
192 retval
= lattice_ecp5_init_address(tap
);
193 if (retval
!= ERROR_OK
)
196 retval
= lattice_ecp5_program_config_map(tap
, bit_file
);
197 if (retval
!= ERROR_OK
)
200 retval
= lattice_ecp5_exit_programming_mode(tap
);
201 if (retval
!= ERROR_OK
)
204 const uint32_t expected2
= STATUS_DONE_BIT
;
205 const uint32_t mask3
= STATUS_DONE_BIT
| STATUS_FAIL_FLAG
;
206 return lattice_verify_status_register_u32(lattice_device
, out
, expected2
, mask3
, false);
209 int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device
*pld_device_info
)
211 if (!pld_device_info
)
214 struct jtag_tap
*tap
= pld_device_info
->tap
;
218 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) == PROGRAM_SPI
)
221 // erase configuration
222 int retval
= lattice_preload(pld_device_info
);
223 if (retval
!= ERROR_OK
)
226 retval
= lattice_ecp5_enable_sram_programming(tap
);
227 if (retval
!= ERROR_OK
)
230 retval
= lattice_ecp5_erase_sram(tap
);
231 if (retval
!= ERROR_OK
)
234 retval
= lattice_ecp5_exit_programming_mode(tap
);
235 if (retval
!= ERROR_OK
)
238 // connect jtag to spi pins
239 retval
= lattice_set_instr(tap
, PROGRAM_SPI
, TAP_IDLE
);
240 if (retval
!= ERROR_OK
)
243 struct scan_field field
;
244 uint8_t buffer
[2] = {0xfe, 0x68};
246 field
.out_value
= buffer
;
247 field
.in_value
= NULL
;
248 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
250 return jtag_execute_queue();
253 int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device
*pld_device_info
)
255 if (!pld_device_info
)
258 struct jtag_tap
*tap
= pld_device_info
->tap
;
262 /* Connecting it again takes way too long to do it multiple times for writing
263 a bitstream (ca. 0.4s each access).
264 We just leave it connected since SCS will not be active when not in shift_dr state.
265 So there is no need to change instruction, just make sure we are not in shift dr state. */
266 jtag_add_runtest(2, TAP_IDLE
);
267 return jtag_execute_queue();
270 int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device
*pld_device_info
, unsigned int *facing_read_bits
)
272 if (!pld_device_info
)
275 *facing_read_bits
= 0;
280 int lattice_ecp5_refresh(struct lattice_pld_device
*lattice_device
)
282 struct jtag_tap
*tap
= lattice_device
->tap
;
286 int retval
= lattice_preload(lattice_device
);
287 if (retval
!= ERROR_OK
)
290 retval
= lattice_set_instr(tap
, LSC_REFRESH
, TAP_IDLE
);
291 if (retval
!= ERROR_OK
)
293 jtag_add_runtest(2, TAP_IDLE
);
294 jtag_add_sleep(200000);
295 retval
= lattice_set_instr(tap
, BYPASS
, TAP_IDLE
);
296 if (retval
!= ERROR_OK
)
298 jtag_add_runtest(100, TAP_IDLE
);
299 jtag_add_sleep(1000);
301 return jtag_execute_queue();