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target/aarch64: Call aarch64_init_debug_access() earlier in aarch64_deassert_reset()
[openocd.git] / src / target / nds32_cmd.c
blob500651dbc835fe6cb2a4b28e9383cfd6414f8467
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/command.h>
24 #include "nds32.h"
25 #include "nds32_aice.h"
26 #include "nds32_disassembler.h"
27
28 extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
29 extern uint32_t nds32_edm_ops_num;
30
31 static const char *const NDS_MEMORY_ACCESS_NAME[] = {
32 "BUS",
33 "CPU",
34 };
35
36 static const char *const NDS_MEMORY_SELECT_NAME[] = {
37 "AUTO",
38 "MEM",
39 "ILM",
40 "DLM",
41 };
42
43 COMMAND_HANDLER(handle_nds32_dssim_command)
44 {
45 struct target *target = get_current_target(CMD_CTX);
46 struct nds32 *nds32 = target_to_nds32(target);
47
48 if (!is_nds32(nds32)) {
49 command_print(CMD_CTX, "current target isn't an Andes core");
50 return ERROR_FAIL;
51 }
52
53 if (CMD_ARGC > 0) {
54 if (strcmp(CMD_ARGV[0], "on") == 0)
55 nds32->step_isr_enable = true;
56 if (strcmp(CMD_ARGV[0], "off") == 0)
57 nds32->step_isr_enable = false;
58 }
59
60 command_print(CMD_CTX, "%s: $INT_MASK.DSSIM: %d", target_name(target),
61 nds32->step_isr_enable);
62
63 return ERROR_OK;
64 }
65
66 COMMAND_HANDLER(handle_nds32_memory_access_command)
67 {
68 struct target *target = get_current_target(CMD_CTX);
69 struct nds32 *nds32 = target_to_nds32(target);
70 struct aice_port_s *aice = target_to_aice(target);
71 struct nds32_memory *memory = &(nds32->memory);
72
73 if (!is_nds32(nds32)) {
74 command_print(CMD_CTX, "current target isn't an Andes core");
75 return ERROR_FAIL;
76 }
77
78 if (CMD_ARGC > 0) {
79 if (strcmp(CMD_ARGV[0], "bus") == 0)
80 memory->access_channel = NDS_MEMORY_ACC_BUS;
81 else if (strcmp(CMD_ARGV[0], "cpu") == 0)
82 memory->access_channel = NDS_MEMORY_ACC_CPU;
83 else /* default access channel is NDS_MEMORY_ACC_CPU */
84 memory->access_channel = NDS_MEMORY_ACC_CPU;
85
86 LOG_DEBUG("memory access channel is changed to %s",
87 NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
88
89 aice_memory_access(aice, memory->access_channel);
90 } else {
91 command_print(CMD_CTX, "%s: memory access channel: %s",
92 target_name(target),
93 NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
94 }
95
96 return ERROR_OK;
97 }
98
99 COMMAND_HANDLER(handle_nds32_memory_mode_command)
100 {
101 struct target *target = get_current_target(CMD_CTX);
102 struct nds32 *nds32 = target_to_nds32(target);
103 struct aice_port_s *aice = target_to_aice(target);
104
105 if (!is_nds32(nds32)) {
106 command_print(CMD_CTX, "current target isn't an Andes core");
107 return ERROR_FAIL;
108 }
109
110 if (CMD_ARGC > 0) {
111
112 if (nds32->edm.access_control == false) {
113 command_print(CMD_CTX, "%s does not support ACC_CTL. "
114 "Set memory mode to MEMORY", target_name(target));
115 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
116 } else if (nds32->edm.direct_access_local_memory == false) {
117 command_print(CMD_CTX, "%s does not support direct access "
118 "local memory. Set memory mode to MEMORY",
119 target_name(target));
120 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
121
122 /* set to ACC_CTL */
123 aice_memory_mode(aice, nds32->memory.mode);
124 } else {
125 if (strcmp(CMD_ARGV[0], "auto") == 0) {
126 nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
127 } else if (strcmp(CMD_ARGV[0], "mem") == 0) {
128 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
129 } else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
130 if (nds32->memory.ilm_base == 0)
131 command_print(CMD_CTX, "%s does not support ILM",
132 target_name(target));
133 else
134 nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
135 } else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
136 if (nds32->memory.dlm_base == 0)
137 command_print(CMD_CTX, "%s does not support DLM",
138 target_name(target));
139 else
140 nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
141 }
142
143 /* set to ACC_CTL */
144 aice_memory_mode(aice, nds32->memory.mode);
145 }
146 }
147
148 command_print(CMD_CTX, "%s: memory mode: %s",
149 target_name(target),
150 NDS_MEMORY_SELECT_NAME[nds32->memory.mode]);
151
152 return ERROR_OK;
153 }
154
155 COMMAND_HANDLER(handle_nds32_cache_command)
156 {
157 struct target *target = get_current_target(CMD_CTX);
158 struct nds32 *nds32 = target_to_nds32(target);
159 struct aice_port_s *aice = target_to_aice(target);
160 struct nds32_cache *icache = &(nds32->memory.icache);
161 struct nds32_cache *dcache = &(nds32->memory.dcache);
162 int result;
163
164 if (!is_nds32(nds32)) {
165 command_print(CMD_CTX, "current target isn't an Andes core");
166 return ERROR_FAIL;
167 }
168
169 if (CMD_ARGC > 0) {
170
171 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
172 if ((dcache->line_size != 0) && (dcache->enable == true)) {
173 /* D$ write back */
174 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
175 if (result != ERROR_OK) {
176 command_print(CMD_CTX, "%s: Write back data cache...failed",
177 target_name(target));
178 return result;
179 }
180
181 command_print(CMD_CTX, "%s: Write back data cache...done",
182 target_name(target));
183
184 /* D$ invalidate */
185 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
186 if (result != ERROR_OK) {
187 command_print(CMD_CTX, "%s: Invalidate data cache...failed",
188 target_name(target));
189 return result;
190 }
191
192 command_print(CMD_CTX, "%s: Invalidate data cache...done",
193 target_name(target));
194 } else {
195 if (dcache->line_size == 0)
196 command_print(CMD_CTX, "%s: No data cache",
197 target_name(target));
198 else
199 command_print(CMD_CTX, "%s: Data cache disabled",
200 target_name(target));
201 }
202
203 if ((icache->line_size != 0) && (icache->enable == true)) {
204 /* I$ invalidate */
205 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
206 if (result != ERROR_OK) {
207 command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
208 target_name(target));
209 return result;
210 }
211
212 command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
213 target_name(target));
214 } else {
215 if (icache->line_size == 0)
216 command_print(CMD_CTX, "%s: No instruction cache",
217 target_name(target));
218 else
219 command_print(CMD_CTX, "%s: Instruction cache disabled",
220 target_name(target));
221 }
222 } else
223 command_print(CMD_CTX, "No valid parameter");
224 }
225
226 return ERROR_OK;
227 }
228
229 COMMAND_HANDLER(handle_nds32_icache_command)
230 {
231 struct target *target = get_current_target(CMD_CTX);
232 struct nds32 *nds32 = target_to_nds32(target);
233 struct aice_port_s *aice = target_to_aice(target);
234 struct nds32_cache *icache = &(nds32->memory.icache);
235 int result;
236
237 if (!is_nds32(nds32)) {
238 command_print(CMD_CTX, "current target isn't an Andes core");
239 return ERROR_FAIL;
240 }
241
242 if (CMD_ARGC > 0) {
243
244 if (icache->line_size == 0) {
245 command_print(CMD_CTX, "%s: No instruction cache",
246 target_name(target));
247 return ERROR_OK;
248 }
249
250 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
251 if (icache->enable == true) {
252 /* I$ invalidate */
253 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
254 if (result != ERROR_OK) {
255 command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
256 target_name(target));
257 return result;
258 }
259
260 command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
261 target_name(target));
262 } else {
263 command_print(CMD_CTX, "%s: Instruction cache disabled",
264 target_name(target));
265 }
266 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
267 uint32_t value;
268 nds32_get_mapped_reg(nds32, IR8, &value);
269 nds32_set_mapped_reg(nds32, IR8, value | 0x1);
270 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
271 uint32_t value;
272 nds32_get_mapped_reg(nds32, IR8, &value);
273 nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
274 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
275 /* TODO: dump cache content */
276 } else {
277 command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
278 }
279 }
280
281 return ERROR_OK;
282 }
283
284 COMMAND_HANDLER(handle_nds32_dcache_command)
285 {
286 struct target *target = get_current_target(CMD_CTX);
287 struct nds32 *nds32 = target_to_nds32(target);
288 struct aice_port_s *aice = target_to_aice(target);
289 struct nds32_cache *dcache = &(nds32->memory.dcache);
290 int result;
291
292 if (!is_nds32(nds32)) {
293 command_print(CMD_CTX, "current target isn't an Andes core");
294 return ERROR_FAIL;
295 }
296
297 if (CMD_ARGC > 0) {
298
299 if (dcache->line_size == 0) {
300 command_print(CMD_CTX, "%s: No data cache", target_name(target));
301 return ERROR_OK;
302 }
303
304 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
305 if (dcache->enable == true) {
306 /* D$ write back */
307 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
308 if (result != ERROR_OK) {
309 command_print(CMD_CTX, "%s: Write back data cache...failed",
310 target_name(target));
311 return result;
312 }
313
314 command_print(CMD_CTX, "%s: Write back data cache...done",
315 target_name(target));
316
317 /* D$ invalidate */
318 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
319 if (result != ERROR_OK) {
320 command_print(CMD_CTX, "%s: Invalidate data cache...failed",
321 target_name(target));
322 return result;
323 }
324
325 command_print(CMD_CTX, "%s: Invalidate data cache...done",
326 target_name(target));
327 } else {
328 command_print(CMD_CTX, "%s: Data cache disabled",
329 target_name(target));
330 }
331 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
332 uint32_t value;
333 nds32_get_mapped_reg(nds32, IR8, &value);
334 nds32_set_mapped_reg(nds32, IR8, value | 0x2);
335 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
336 uint32_t value;
337 nds32_get_mapped_reg(nds32, IR8, &value);
338 nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
339 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
340 /* TODO: dump cache content */
341 } else {
342 command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
343 }
344 }
345
346 return ERROR_OK;
347 }
348
349 COMMAND_HANDLER(handle_nds32_auto_break_command)
350 {
351 struct target *target = get_current_target(CMD_CTX);
352 struct nds32 *nds32 = target_to_nds32(target);
353
354 if (!is_nds32(nds32)) {
355 command_print(CMD_CTX, "current target isn't an Andes core");
356 return ERROR_FAIL;
357 }
358
359 if (CMD_ARGC > 0) {
360 if (strcmp(CMD_ARGV[0], "on") == 0)
361 nds32->auto_convert_hw_bp = true;
362 if (strcmp(CMD_ARGV[0], "off") == 0)
363 nds32->auto_convert_hw_bp = false;
364 }
365
366 if (nds32->auto_convert_hw_bp)
367 command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: on",
368 target_name(target));
369 else
370 command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: off",
371 target_name(target));
372
373 return ERROR_OK;
374 }
375
376 COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
377 {
378 struct target *target = get_current_target(CMD_CTX);
379 struct nds32 *nds32 = target_to_nds32(target);
380
381 if (!is_nds32(nds32)) {
382 command_print(CMD_CTX, "current target isn't an Andes core");
383 return ERROR_FAIL;
384 }
385
386 if (CMD_ARGC > 0) {
387 if (strcmp(CMD_ARGV[0], "on") == 0)
388 nds32->virtual_hosting = true;
389 if (strcmp(CMD_ARGV[0], "off") == 0)
390 nds32->virtual_hosting = false;
391 }
392
393 if (nds32->virtual_hosting)
394 command_print(CMD_CTX, "%s: virtual hosting: on", target_name(target));
395 else
396 command_print(CMD_CTX, "%s: virtual hosting: off", target_name(target));
397
398 return ERROR_OK;
399 }
400
401 COMMAND_HANDLER(handle_nds32_global_stop_command)
402 {
403 struct target *target = get_current_target(CMD_CTX);
404 struct nds32 *nds32 = target_to_nds32(target);
405
406 if (!is_nds32(nds32)) {
407 command_print(CMD_CTX, "current target isn't an Andes core");
408 return ERROR_FAIL;
409 }
410
411 if (CMD_ARGC > 0) {
412 if (strcmp(CMD_ARGV[0], "on") == 0)
413 nds32->global_stop = true;
414 if (strcmp(CMD_ARGV[0], "off") == 0)
415 nds32->global_stop = false;
416 }
417
418 if (nds32->global_stop)
419 LOG_INFO("%s: global stop: on", target_name(target));
420 else
421 LOG_INFO("%s: global stop: off", target_name(target));
422
423 return ERROR_OK;
424 }
425
426 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
427 {
428 struct target *target = get_current_target(CMD_CTX);
429 struct nds32 *nds32 = target_to_nds32(target);
430
431 if (!is_nds32(nds32)) {
432 command_print(CMD_CTX, "current target isn't an Andes core");
433 return ERROR_FAIL;
434 }
435
436 if (CMD_ARGC > 0) {
437 if (strcmp(CMD_ARGV[0], "on") == 0)
438 nds32->soft_reset_halt = true;
439 if (strcmp(CMD_ARGV[0], "off") == 0)
440 nds32->soft_reset_halt = false;
441 }
442
443 if (nds32->soft_reset_halt)
444 LOG_INFO("%s: soft-reset-halt: on", target_name(target));
445 else
446 LOG_INFO("%s: soft-reset-halt: off", target_name(target));
447
448 return ERROR_OK;
449 }
450
451 COMMAND_HANDLER(handle_nds32_boot_time_command)
452 {
453 struct target *target = get_current_target(CMD_CTX);
454 struct nds32 *nds32 = target_to_nds32(target);
455
456 if (!is_nds32(nds32)) {
457 command_print(CMD_CTX, "current target isn't an Andes core");
458 return ERROR_FAIL;
459 }
460
461 if (CMD_ARGC > 0)
462 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
463
464 return ERROR_OK;
465 }
466
467 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
468 {
469 struct target *target = get_current_target(CMD_CTX);
470 struct nds32 *nds32 = target_to_nds32(target);
471
472 if (!is_nds32(nds32)) {
473 command_print(CMD_CTX, "current target isn't an Andes core");
474 return ERROR_FAIL;
475 }
476
477 nds32->edm_passcode = strdup(CMD_ARGV[0]);
478
479 return ERROR_OK;
480 }
481
482 COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
483 {
484 struct target *target = get_current_target(CMD_CTX);
485 struct nds32 *nds32 = target_to_nds32(target);
486
487 if (!is_nds32(nds32)) {
488 command_print(CMD_CTX, "current target isn't an Andes core");
489 return ERROR_FAIL;
490 }
491
492 if (CMD_ARGC > 1) {
493
494 uint32_t misc_reg_no;
495 uint32_t data;
496
497 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
498 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
499
500 if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
501 return ERROR_FAIL;
502
503 /* Just save the operation. Execute it in nds32_login() */
504 nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
505 nds32_edm_ops[nds32_edm_ops_num].value = data;
506 nds32_edm_ops_num++;
507 } else
508 return ERROR_FAIL;
509
510 return ERROR_OK;
511 }
512
513 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
514 {
515 struct target *target = get_current_target(CMD_CTX);
516 struct nds32 *nds32 = target_to_nds32(target);
517
518 if (!is_nds32(nds32)) {
519 command_print(CMD_CTX, "current target isn't an Andes core");
520 return ERROR_FAIL;
521 }
522
523 if (CMD_ARGC > 0) {
524 if (strcmp(CMD_ARGV[0], "on") == 0)
525 nds32->reset_halt_as_examine = true;
526 if (strcmp(CMD_ARGV[0], "off") == 0)
527 nds32->reset_halt_as_examine = false;
528 }
529
530 return ERROR_OK;
531 }
532
533 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
534 {
535 struct target *target = get_current_target(CMD_CTX);
536 struct nds32 *nds32 = target_to_nds32(target);
537
538 if (!is_nds32(nds32)) {
539 command_print(CMD_CTX, "current target isn't an Andes core");
540 return ERROR_FAIL;
541 }
542
543 if (CMD_ARGC > 0) {
544 if (strcmp(CMD_ARGV[0], "on") == 0)
545 nds32->keep_target_edm_ctl = true;
546 if (strcmp(CMD_ARGV[0], "off") == 0)
547 nds32->keep_target_edm_ctl = false;
548 }
549
550 return ERROR_OK;
551 }
552
553 COMMAND_HANDLER(handle_nds32_decode_command)
554 {
555 struct target *target = get_current_target(CMD_CTX);
556 struct nds32 *nds32 = target_to_nds32(target);
557
558 if (!is_nds32(nds32)) {
559 command_print(CMD_CTX, "current target isn't an Andes core");
560 return ERROR_FAIL;
561 }
562
563 if (CMD_ARGC > 1) {
564
565 uint32_t addr;
566 uint32_t insn_count;
567 uint32_t opcode;
568 uint32_t read_addr;
569 uint32_t i;
570 struct nds32_instruction instruction;
571
572 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
573 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
574
575 read_addr = addr;
576 i = 0;
577 while (i < insn_count) {
578 if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode))
579 return ERROR_FAIL;
580 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode,
581 read_addr, &instruction))
582 return ERROR_FAIL;
583
584 command_print(CMD_CTX, "%s", instruction.text);
585
586 read_addr += instruction.instruction_size;
587 i++;
588 }
589 } else if (CMD_ARGC == 1) {
590
591 uint32_t addr;
592 uint32_t opcode;
593 struct nds32_instruction instruction;
594
595 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
596
597 if (ERROR_OK != nds32_read_opcode(nds32, addr, &opcode))
598 return ERROR_FAIL;
599 if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, addr, &instruction))
600 return ERROR_FAIL;
601
602 command_print(CMD_CTX, "%s", instruction.text);
603 } else
604 return ERROR_FAIL;
605
606 return ERROR_OK;
607 }
608
609 COMMAND_HANDLER(handle_nds32_word_access_mem_command)
610 {
611 struct target *target = get_current_target(CMD_CTX);
612 struct nds32 *nds32 = target_to_nds32(target);
613
614 if (!is_nds32(nds32)) {
615 command_print(CMD_CTX, "current target isn't an Andes core");
616 return ERROR_FAIL;
617 }
618
619 if (CMD_ARGC > 0) {
620 if (strcmp(CMD_ARGV[0], "on") == 0)
621 nds32->word_access_mem = true;
622 if (strcmp(CMD_ARGV[0], "off") == 0)
623 nds32->word_access_mem = false;
624 }
625
626 return ERROR_OK;
627 }
628
629 COMMAND_HANDLER(handle_nds32_query_target_command)
630 {
631 struct target *target = get_current_target(CMD_CTX);
632 struct nds32 *nds32 = target_to_nds32(target);
633
634 if (!is_nds32(nds32)) {
635 command_print(CMD_CTX, "current target isn't an Andes core");
636 return ERROR_FAIL;
637 }
638
639 command_print(CMD_CTX, "OCD");
640
641 return ERROR_OK;
642 }
643
644 COMMAND_HANDLER(handle_nds32_query_endian_command)
645 {
646 struct target *target = get_current_target(CMD_CTX);
647 struct nds32 *nds32 = target_to_nds32(target);
648
649 if (!is_nds32(nds32)) {
650 command_print(CMD_CTX, "current target isn't an Andes core");
651 return ERROR_FAIL;
652 }
653
654 uint32_t value_psw;
655 nds32_get_mapped_reg(nds32, IR0, &value_psw);
656
657 if (value_psw & 0x20)
658 command_print(CMD_CTX, "%s: BE", target_name(target));
659 else
660 command_print(CMD_CTX, "%s: LE", target_name(target));
661
662 return ERROR_OK;
663 }
664
665 COMMAND_HANDLER(handle_nds32_query_cpuid_command)
666 {
667 struct target *target = get_current_target(CMD_CTX);
668 struct nds32 *nds32 = target_to_nds32(target);
669
670 if (!is_nds32(nds32)) {
671 command_print(CMD_CTX, "current target isn't an Andes core");
672 return ERROR_FAIL;
673 }
674
675 command_print(CMD_CTX, "CPUID: %s", target_name(target));
676
677 return ERROR_OK;
678 }
679
680 static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
681 {
682 const char *cmd_name = Jim_GetString(argv[0], NULL);
683
684 Jim_GetOptInfo goi;
685 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
686
687 if (goi.argc < 3) {
688 Jim_SetResultFormatted(goi.interp,
689 "usage: %s <address> <count> <data>", cmd_name);
690 return JIM_ERR;
691 }
692
693 int e;
694 jim_wide address;
695 e = Jim_GetOpt_Wide(&goi, &address);
696 if (e != JIM_OK)
697 return e;
698
699 jim_wide count;
700 e = Jim_GetOpt_Wide(&goi, &count);
701 if (e != JIM_OK)
702 return e;
703
704 uint32_t *data = malloc(count * sizeof(uint32_t));
705 if (data == NULL)
706 return JIM_ERR;
707
708 jim_wide i;
709 for (i = 0; i < count; i++) {
710 jim_wide tmp;
711 e = Jim_GetOpt_Wide(&goi, &tmp);
712 if (e != JIM_OK) {
713 free(data);
714 return e;
715 }
716 data[i] = (uint32_t)tmp;
717 }
718
719 /* all args must be consumed */
720 if (goi.argc != 0) {
721 free(data);
722 return JIM_ERR;
723 }
724
725 struct target *target = Jim_CmdPrivData(goi.interp);
726 int result;
727
728 result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
729
730 free(data);
731
732 return result;
733 }
734
735 static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
736 {
737 const char *cmd_name = Jim_GetString(argv[0], NULL);
738
739 Jim_GetOptInfo goi;
740 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
741
742 if (goi.argc < 3) {
743 Jim_SetResultFormatted(goi.interp,
744 "usage: %s # of pairs [<address> <data>]+", cmd_name);
745 return JIM_ERR;
746 }
747
748 int e;
749 jim_wide num_of_pairs;
750 e = Jim_GetOpt_Wide(&goi, &num_of_pairs);
751 if (e != JIM_OK)
752 return e;
753
754 struct target *target = Jim_CmdPrivData(goi.interp);
755 struct aice_port_s *aice = target_to_aice(target);
756 int result;
757 uint32_t address;
758 uint32_t data;
759 jim_wide i;
760
761 aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
762 for (i = 0; i < num_of_pairs; i++) {
763 jim_wide tmp;
764 e = Jim_GetOpt_Wide(&goi, &tmp);
765 if (e != JIM_OK)
766 break;
767 address = (uint32_t)tmp;
768
769 e = Jim_GetOpt_Wide(&goi, &tmp);
770 if (e != JIM_OK)
771 break;
772 data = (uint32_t)tmp;
773
774 result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
775 if (result != ERROR_OK)
776 break;
777 }
778 aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
779
780 /* all args must be consumed */
781 if (goi.argc != 0)
782 return JIM_ERR;
783
784 return ERROR_OK;
785 }
786
787 static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
788 {
789 const char *cmd_name = Jim_GetString(argv[0], NULL);
790
791 Jim_GetOptInfo goi;
792 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
793
794 if (goi.argc < 2) {
795 Jim_SetResultFormatted(goi.interp,
796 "usage: %s <address> <count>", cmd_name);
797 return JIM_ERR;
798 }
799
800 int e;
801 jim_wide address;
802 e = Jim_GetOpt_Wide(&goi, &address);
803 if (e != JIM_OK)
804 return e;
805
806 jim_wide count;
807 e = Jim_GetOpt_Wide(&goi, &count);
808 if (e != JIM_OK)
809 return e;
810
811 /* all args must be consumed */
812 if (goi.argc != 0)
813 return JIM_ERR;
814
815 struct target *target = Jim_CmdPrivData(goi.interp);
816 uint32_t *data = malloc(count * sizeof(uint32_t));
817 int result;
818 result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
819 char data_str[12];
820
821 jim_wide i;
822 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
823 for (i = 0; i < count; i++) {
824 sprintf(data_str, "0x%08" PRIx32 " ", data[i]);
825 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
826 }
827
828 free(data);
829
830 return result;
831 }
832
833 static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
834 {
835 const char *cmd_name = Jim_GetString(argv[0], NULL);
836
837 Jim_GetOptInfo goi;
838 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
839
840 if (goi.argc < 1) {
841 Jim_SetResultFormatted(goi.interp,
842 "usage: %s <edm_sr_name>", cmd_name);
843 return JIM_ERR;
844 }
845
846 int e;
847 const char *edm_sr_name;
848 int edm_sr_name_len;
849 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
850 if (e != JIM_OK)
851 return e;
852
853 /* all args must be consumed */
854 if (goi.argc != 0)
855 return JIM_ERR;
856
857 uint32_t edm_sr_number;
858 uint32_t edm_sr_value;
859 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
860 edm_sr_number = NDS_EDM_SR_EDM_DTR;
861 else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
862 edm_sr_number = NDS_EDM_SR_EDMSW;
863 else
864 return ERROR_FAIL;
865
866 struct target *target = Jim_CmdPrivData(goi.interp);
867 struct aice_port_s *aice = target_to_aice(target);
868 char data_str[11];
869
870 aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
871
872 sprintf(data_str, "0x%08" PRIx32, edm_sr_value);
873 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
874 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
875
876 return ERROR_OK;
877 }
878
879 static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
880 {
881 const char *cmd_name = Jim_GetString(argv[0], NULL);
882
883 Jim_GetOptInfo goi;
884 Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
885
886 if (goi.argc < 2) {
887 Jim_SetResultFormatted(goi.interp,
888 "usage: %s <edm_sr_name> <value>", cmd_name);
889 return JIM_ERR;
890 }
891
892 int e;
893 const char *edm_sr_name;
894 int edm_sr_name_len;
895 e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len);
896 if (e != JIM_OK)
897 return e;
898
899 jim_wide value;
900 e = Jim_GetOpt_Wide(&goi, &value);
901 if (e != JIM_OK)
902 return e;
903
904 /* all args must be consumed */
905 if (goi.argc != 0)
906 return JIM_ERR;
907
908 uint32_t edm_sr_number;
909 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
910 edm_sr_number = NDS_EDM_SR_EDM_DTR;
911 else
912 return ERROR_FAIL;
913
914 struct target *target = Jim_CmdPrivData(goi.interp);
915 struct aice_port_s *aice = target_to_aice(target);
916
917 aice_write_debug_reg(aice, edm_sr_number, value);
918
919 return ERROR_OK;
920 }
921
922 static const struct command_registration nds32_query_command_handlers[] = {
923 {
924 .name = "target",
925 .handler = handle_nds32_query_target_command,
926 .mode = COMMAND_EXEC,
927 .usage = "",
928 .help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
929 },
930 {
931 .name = "endian",
932 .handler = handle_nds32_query_endian_command,
933 .mode = COMMAND_EXEC,
934 .usage = "",
935 .help = "query target endian",
936 },
937 {
938 .name = "cpuid",
939 .handler = handle_nds32_query_cpuid_command,
940 .mode = COMMAND_EXEC,
941 .usage = "",
942 .help = "query CPU ID",
943 },
944
945 COMMAND_REGISTRATION_DONE
946 };
947
948 static const struct command_registration nds32_exec_command_handlers[] = {
949 {
950 .name = "dssim",
951 .handler = handle_nds32_dssim_command,
952 .mode = COMMAND_EXEC,
953 .usage = "['on'|'off']",
954 .help = "display/change $INT_MASK.DSSIM status",
955 },
956 {
957 .name = "mem_access",
958 .handler = handle_nds32_memory_access_command,
959 .mode = COMMAND_EXEC,
960 .usage = "['bus'|'cpu']",
961 .help = "display/change memory access channel",
962 },
963 {
964 .name = "mem_mode",
965 .handler = handle_nds32_memory_mode_command,
966 .mode = COMMAND_EXEC,
967 .usage = "['auto'|'mem'|'ilm'|'dlm']",
968 .help = "display/change memory mode",
969 },
970 {
971 .name = "cache",
972 .handler = handle_nds32_cache_command,
973 .mode = COMMAND_EXEC,
974 .usage = "['invalidate']",
975 .help = "cache control",
976 },
977 {
978 .name = "icache",
979 .handler = handle_nds32_icache_command,
980 .mode = COMMAND_EXEC,
981 .usage = "['invalidate'|'enable'|'disable'|'dump']",
982 .help = "icache control",
983 },
984 {
985 .name = "dcache",
986 .handler = handle_nds32_dcache_command,
987 .mode = COMMAND_EXEC,
988 .usage = "['invalidate'|'enable'|'disable'|'dump']",
989 .help = "dcache control",
990 },
991 {
992 .name = "auto_break",
993 .handler = handle_nds32_auto_break_command,
994 .mode = COMMAND_EXEC,
995 .usage = "['on'|'off']",
996 .help = "convert software breakpoints to hardware breakpoints if needed",
997 },
998 {
999 .name = "virtual_hosting",
1000 .handler = handle_nds32_virtual_hosting_command,
1001 .mode = COMMAND_ANY,
1002 .usage = "['on'|'off']",
1003 .help = "turn on/off virtual hosting",
1004 },
1005 {
1006 .name = "global_stop",
1007 .handler = handle_nds32_global_stop_command,
1008 .mode = COMMAND_ANY,
1009 .usage = "['on'|'off']",
1010 .help = "turn on/off global stop. After turning on, every load/store" \
1011 "instructions will be stopped to check memory access.",
1012 },
1013 {
1014 .name = "soft_reset_halt",
1015 .handler = handle_nds32_soft_reset_halt_command,
1016 .mode = COMMAND_ANY,
1017 .usage = "['on'|'off']",
1018 .help = "as issuing rest-halt, to use soft-reset-halt or not." \
1019 "the feature is for backward-compatible.",
1020 },
1021 {
1022 .name = "boot_time",
1023 .handler = handle_nds32_boot_time_command,
1024 .mode = COMMAND_CONFIG,
1025 .usage = "milliseconds",
1026 .help = "set the period to wait after srst.",
1027 },
1028 {
1029 .name = "login_edm_passcode",
1030 .handler = handle_nds32_login_edm_passcode_command,
1031 .mode = COMMAND_CONFIG,
1032 .usage = "passcode",
1033 .help = "set EDM passcode for secure MCU debugging.",
1034 },
1035 {
1036 .name = "login_edm_operation",
1037 .handler = handle_nds32_login_edm_operation_command,
1038 .mode = COMMAND_CONFIG,
1039 .usage = "login_edm_operation misc_reg_no value",
1040 .help = "add EDM operations for secure MCU debugging.",
1041 },
1042 {
1043 .name = "reset_halt_as_init",
1044 .handler = handle_nds32_reset_halt_as_init_command,
1045 .mode = COMMAND_CONFIG,
1046 .usage = "['on'|'off']",
1047 .help = "reset halt as openocd init.",
1048 },
1049 {
1050 .name = "keep_target_edm_ctl",
1051 .handler = handle_nds32_keep_target_edm_ctl_command,
1052 .mode = COMMAND_CONFIG,
1053 .usage = "['on'|'off']",
1054 .help = "Backup/Restore target EDM_CTL register.",
1055 },
1056 {
1057 .name = "decode",
1058 .handler = handle_nds32_decode_command,
1059 .mode = COMMAND_EXEC,
1060 .usage = "address icount",
1061 .help = "decode instruction.",
1062 },
1063 {
1064 .name = "word_access_mem",
1065 .handler = handle_nds32_word_access_mem_command,
1066 .mode = COMMAND_ANY,
1067 .usage = "['on'|'off']",
1068 .help = "Always use word-aligned address to access memory.",
1069 },
1070 {
1071 .name = "bulk_write",
1072 .jim_handler = jim_nds32_bulk_write,
1073 .mode = COMMAND_EXEC,
1074 .help = "Write multiple 32-bit words to target memory",
1075 .usage = "address count data",
1076 },
1077 {
1078 .name = "multi_write",
1079 .jim_handler = jim_nds32_multi_write,
1080 .mode = COMMAND_EXEC,
1081 .help = "Write multiple addresses/words to target memory",
1082 .usage = "num_of_pairs [address data]+",
1083 },
1084 {
1085 .name = "bulk_read",
1086 .jim_handler = jim_nds32_bulk_read,
1087 .mode = COMMAND_EXEC,
1088 .help = "Read multiple 32-bit words from target memory",
1089 .usage = "address count",
1090 },
1091 {
1092 .name = "read_edmsr",
1093 .jim_handler = jim_nds32_read_edm_sr,
1094 .mode = COMMAND_EXEC,
1095 .help = "Read EDM system register",
1096 .usage = "['edmsw'|'edm_dtr']",
1097 },
1098 {
1099 .name = "write_edmsr",
1100 .jim_handler = jim_nds32_write_edm_sr,
1101 .mode = COMMAND_EXEC,
1102 .help = "Write EDM system register",
1103 .usage = "['edm_dtr'] value",
1104 },
1105 {
1106 .name = "query",
1107 .mode = COMMAND_EXEC,
1108 .help = "Andes query command group",
1109 .usage = "",
1110 .chain = nds32_query_command_handlers,
1111 },
1112
1113 COMMAND_REGISTRATION_DONE
1114 };
1115
1116 const struct command_registration nds32_command_handlers[] = {
1117 {
1118 .name = "nds",
1119 .mode = COMMAND_ANY,
1120 .help = "Andes command group",
1121 .usage = "",
1122 .chain = nds32_exec_command_handlers,
1123 },
1124 COMMAND_REGISTRATION_DONE
1125 };
1126
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