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- preserve cortex_m3 C_MASKINTS during resume/step
[openocd.git] / src / target / armv7m.c
blobd4c6d3576f345c41fea80068b812326f2211fec1
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "replacements.h"
34
35 #include "armv7m.h"
36 #include "register.h"
37 #include "target.h"
38 #include "log.h"
39 #include "jtag.h"
40 #include "arm_jtag.h"
41
42 #include <stdlib.h>
43 #include <string.h>
44
45 #if 0
46 #define _DEBUG_INSTRUCTION_EXECUTION_
47 #endif
48
49 char* armv7m_mode_strings[] =
50 {
51 "Thread", "Thread (User)", "Handler",
52 };
53
54 char* armv7m_exception_strings[] =
55 {
56 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
57 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 };
59
60 char* armv7m_core_reg_list[] =
61 {
62 /* Registers accessed through core debug */
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 "sp", "lr", "pc",
65 "xPSR", "msp", "psp",
66 /* Registers accessed through special reg 20 */
67 "primask", "basepri", "faultmask", "control"
68 };
69
70 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
71
72 reg_t armv7m_gdb_dummy_fp_reg =
73 {
74 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
75 };
76
77 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
78
79 reg_t armv7m_gdb_dummy_fps_reg =
80 {
81 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
82 };
83
84 #ifdef ARMV7_GDB_HACKS
85 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
86
87 reg_t armv7m_gdb_dummy_cpsr_reg =
88 {
89 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
90 };
91 #endif
92
93 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
94 {
95 /* CORE_GP are accesible using the core debug registers */
96 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
107 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
108 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
109 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
110 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
111 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
112
113 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
114 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
115 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
116
117 /* CORE_SP are accesible using coreregister 20 */
118 {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
119 {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
120 {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
121 {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
122 };
123
124 int armv7m_core_reg_arch_type = -1;
125 int armv7m_dummy_core_reg_arch_type = -1;
126
127 int armv7m_restore_context(target_t *target)
128 {
129 int i;
130
131 /* get pointers to arch-specific information */
132 armv7m_common_t *armv7m = target->arch_info;
133
134 LOG_DEBUG(" ");
135
136 if (armv7m->pre_restore_context)
137 armv7m->pre_restore_context(target);
138
139 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
140 {
141 if (armv7m->core_cache->reg_list[i].dirty)
142 {
143 armv7m->write_core_reg(target, i);
144 }
145 }
146
147 if (armv7m->post_restore_context)
148 armv7m->post_restore_context(target);
149
150 return ERROR_OK;
151 }
152
153 /* Core state functions */
154 char *armv7m_exception_string(int number)
155 {
156 static char enamebuf[32];
157
158 if ((number < 0) | (number > 511))
159 return "Invalid exception";
160 if (number < 16)
161 return armv7m_exception_strings[number];
162 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
163 return enamebuf;
164 }
165
166 int armv7m_get_core_reg(reg_t *reg)
167 {
168 int retval;
169 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
170 target_t *target = armv7m_reg->target;
171 armv7m_common_t *armv7m_target = target->arch_info;
172
173 if (target->state != TARGET_HALTED)
174 {
175 return ERROR_TARGET_NOT_HALTED;
176 }
177
178 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
179
180 return retval;
181 }
182
183 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
184 {
185 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
186 target_t *target = armv7m_reg->target;
187 u32 value = buf_get_u32(buf, 0, 32);
188
189 if (target->state != TARGET_HALTED)
190 {
191 return ERROR_TARGET_NOT_HALTED;
192 }
193
194 buf_set_u32(reg->value, 0, 32, value);
195 reg->dirty = 1;
196 reg->valid = 1;
197
198 return ERROR_OK;
199 }
200
201 int armv7m_read_core_reg(struct target_s *target, int num)
202 {
203 u32 reg_value;
204 int retval;
205 armv7m_core_reg_t * armv7m_core_reg;
206
207 /* get pointers to arch-specific information */
208 armv7m_common_t *armv7m = target->arch_info;
209
210 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
211 return ERROR_INVALID_ARGUMENTS;
212
213 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
214 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
215 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
216 armv7m->core_cache->reg_list[num].valid = 1;
217 armv7m->core_cache->reg_list[num].dirty = 0;
218
219 return retval;
220 }
221
222 int armv7m_write_core_reg(struct target_s *target, int num)
223 {
224 int retval;
225 u32 reg_value;
226 armv7m_core_reg_t *armv7m_core_reg;
227
228 /* get pointers to arch-specific information */
229 armv7m_common_t *armv7m = target->arch_info;
230
231 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
232 return ERROR_INVALID_ARGUMENTS;
233
234 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
235 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
236 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
237 if (retval != ERROR_OK)
238 {
239 LOG_ERROR("JTAG failure");
240 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
241 return ERROR_JTAG_DEVICE_ERROR;
242 }
243 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
244 armv7m->core_cache->reg_list[num].valid = 1;
245 armv7m->core_cache->reg_list[num].dirty = 0;
246
247 return ERROR_OK;
248 }
249
250 int armv7m_invalidate_core_regs(target_t *target)
251 {
252 /* get pointers to arch-specific information */
253 armv7m_common_t *armv7m = target->arch_info;
254 int i;
255
256 for (i = 0; i < armv7m->core_cache->num_regs; i++)
257 {
258 armv7m->core_cache->reg_list[i].valid = 0;
259 armv7m->core_cache->reg_list[i].dirty = 0;
260 }
261
262 return ERROR_OK;
263 }
264
265 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
266 {
267 /* get pointers to arch-specific information */
268 armv7m_common_t *armv7m = target->arch_info;
269 int i;
270
271 *reg_list_size = 26;
272 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
273
274 for (i = 0; i < 16; i++)
275 {
276 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
277 }
278
279 for (i = 16; i < 24; i++)
280 {
281 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
282 }
283
284 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
285
286 #ifdef ARMV7_GDB_HACKS
287 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
288 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
289
290 /* ARMV7M is always in thumb mode, try to make GDB understand this
291 * if it does not support this arch */
292 armv7m->core_cache->reg_list[15].value[0] |= 1;
293 #else
294 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
295 #endif
296
297 return ERROR_OK;
298 }
299
300 /* run to exit point. return error if exit point was not reached. */
301 static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int timeout_ms, u32 exit_point, armv7m_common_t *armv7m)
302 {
303 u32 pc;
304 int retval;
305 /* This code relies on the target specific resume() and poll()->debug_entry()
306 * sequence to write register values to the processor and the read them back */
307 if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
308 {
309 return retval;
310 }
311
312 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
313 /* If the target fails to halt due to the breakpoint, force a halt */
314 if (retval != ERROR_OK || target->state != TARGET_HALTED)
315 {
316 if ((retval=target_halt(target))!=ERROR_OK)
317 return retval;
318 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
319 {
320 return retval;
321 }
322 return ERROR_TARGET_TIMEOUT;
323 }
324
325 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
326 if (pc != exit_point)
327 {
328 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
329 return ERROR_TARGET_TIMEOUT;
330 }
331
332 return ERROR_OK;
333 }
334
335 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
336 {
337 /* get pointers to arch-specific information */
338 armv7m_common_t *armv7m = target->arch_info;
339 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
340 enum armv7m_mode core_mode = armv7m->core_mode;
341 int retval = ERROR_OK;
342 int i;
343 u32 context[ARMV7NUMCOREREGS];
344
345 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
346 {
347 LOG_ERROR("current target isn't an ARMV7M target");
348 return ERROR_TARGET_INVALID;
349 }
350
351 if (target->state != TARGET_HALTED)
352 {
353 LOG_WARNING("target not halted");
354 return ERROR_TARGET_NOT_HALTED;
355 }
356
357 /* refresh core register cache */
358 /* Not needed if core register cache is always consistent with target process state */
359 for (i = 0; i < ARMV7NUMCOREREGS; i++)
360 {
361 if (!armv7m->core_cache->reg_list[i].valid)
362 armv7m->read_core_reg(target, i);
363 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
364 }
365
366 for (i = 0; i < num_mem_params; i++)
367 {
368 if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
369 return retval;
370 }
371
372 for (i = 0; i < num_reg_params; i++)
373 {
374 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
375 u32 regvalue;
376
377 if (!reg)
378 {
379 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
380 exit(-1);
381 }
382
383 if (reg->size != reg_params[i].size)
384 {
385 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
386 exit(-1);
387 }
388
389 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
390 armv7m_set_core_reg(reg, reg_params[i].value);
391 }
392
393 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
394 {
395 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
396 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
397 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
398 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
399 }
400
401 /* ARMV7M always runs in Thumb state */
402 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
403 {
404 LOG_ERROR("can't add breakpoint to finish algorithm execution");
405 return ERROR_TARGET_FAILURE;
406 }
407
408 retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
409
410 breakpoint_remove(target, exit_point);
411
412 if (retval != ERROR_OK)
413 {
414 return retval;
415 }
416
417 /* Read memory values to mem_params[] */
418 for (i = 0; i < num_mem_params; i++)
419 {
420 if (mem_params[i].direction != PARAM_OUT)
421 if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
422 {
423 return retval;
424 }
425 }
426
427 /* Copy core register values to reg_params[] */
428 for (i = 0; i < num_reg_params; i++)
429 {
430 if (reg_params[i].direction != PARAM_OUT)
431 {
432 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
433
434 if (!reg)
435 {
436 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
437 exit(-1);
438 }
439
440 if (reg->size != reg_params[i].size)
441 {
442 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
443 exit(-1);
444 }
445
446 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
447 }
448 }
449
450 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
451 {
452 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
453 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
454 armv7m->core_cache->reg_list[i].valid = 1;
455 armv7m->core_cache->reg_list[i].dirty = 1;
456 }
457
458 armv7m->core_mode = core_mode;
459
460 return retval;
461 }
462
463 int armv7m_arch_state(struct target_s *target)
464 {
465 /* get pointers to arch-specific information */
466 armv7m_common_t *armv7m = target->arch_info;
467
468 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
469 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
470 armv7m_mode_strings[armv7m->core_mode],
471 armv7m_exception_string(armv7m->exception_number),
472 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
473 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
474
475 return ERROR_OK;
476 }
477
478 reg_cache_t *armv7m_build_reg_cache(target_t *target)
479 {
480 /* get pointers to arch-specific information */
481 armv7m_common_t *armv7m = target->arch_info;
482
483 int num_regs = ARMV7NUMCOREREGS;
484 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
485 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
486 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
487 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
488 int i;
489
490 if (armv7m_core_reg_arch_type == -1)
491 {
492 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
493 }
494
495 register_init_dummy(&armv7m_gdb_dummy_fps_reg);
496 #ifdef ARMV7_GDB_HACKS
497 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
498 #endif
499 register_init_dummy(&armv7m_gdb_dummy_fp_reg);
500
501 /* Build the process context cache */
502 cache->name = "arm v7m registers";
503 cache->next = NULL;
504 cache->reg_list = reg_list;
505 cache->num_regs = num_regs;
506 (*cache_p) = cache;
507 armv7m->core_cache = cache;
508
509 for (i = 0; i < num_regs; i++)
510 {
511 arch_info[i] = armv7m_core_reg_list_arch_info[i];
512 arch_info[i].target = target;
513 arch_info[i].armv7m_common = armv7m;
514 reg_list[i].name = armv7m_core_reg_list[i];
515 reg_list[i].size = 32;
516 reg_list[i].value = calloc(1, 4);
517 reg_list[i].dirty = 0;
518 reg_list[i].valid = 0;
519 reg_list[i].bitfield_desc = NULL;
520 reg_list[i].num_bitfields = 0;
521 reg_list[i].arch_type = armv7m_core_reg_arch_type;
522 reg_list[i].arch_info = &arch_info[i];
523 }
524
525 return cache;
526 }
527
528 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
529 {
530 armv7m_build_reg_cache(target);
531
532 return ERROR_OK;
533 }
534
535 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
536 {
537 /* register arch-specific functions */
538
539 target->arch_info = armv7m;
540 armv7m->read_core_reg = armv7m_read_core_reg;
541 armv7m->write_core_reg = armv7m_write_core_reg;
542
543 return ERROR_OK;
544 }
545
546 int armv7m_register_commands(struct command_context_s *cmd_ctx)
547 {
548 return ERROR_OK;
549 }
550
551 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
552 {
553 working_area_t *crc_algorithm;
554 armv7m_algorithm_t armv7m_info;
555 reg_param_t reg_params[2];
556 int retval;
557
558 u16 cortex_m3_crc_code[] = {
559 0x4602, /* mov r2, r0 */
560 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
561 0x460B, /* mov r3, r1 */
562 0xF04F, 0x0400, /* mov r4, #0 */
563 0xE013, /* b ncomp */
564 /* nbyte: */
565 0x5D11, /* ldrb r1, [r2, r4] */
566 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
567 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
568
569 0xF04F, 0x0500, /* mov r5, #0 */
570 /* loop: */
571 0x2800, /* cmp r0, #0 */
572 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
573 0xF105, 0x0501, /* add r5, r5, #1 */
574 0x4630, /* mov r0, r6 */
575 0xBFB8, /* it lt */
576 0xEA86, 0x0007, /* eor r0, r6, r7 */
577 0x2D08, /* cmp r5, #8 */
578 0xD1F4, /* bne loop */
579
580 0xF104, 0x0401, /* add r4, r4, #1 */
581 /* ncomp: */
582 0x429C, /* cmp r4, r3 */
583 0xD1E9, /* bne nbyte */
584 /* end: */
585 0xE7FE, /* b end */
586 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
587 };
588
589 int i;
590
591 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
592 {
593 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
594 }
595
596 /* convert flash writing code into a buffer in target endianness */
597 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
598 if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK)
599 {
600 return retval;
601 }
602
603 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
604 armv7m_info.core_mode = ARMV7M_MODE_ANY;
605
606 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
607 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
608
609 buf_set_u32(reg_params[0].value, 0, 32, address);
610 buf_set_u32(reg_params[1].value, 0, 32, count);
611
612 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
613 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
614 {
615 LOG_ERROR("error executing cortex_m3 crc algorithm");
616 destroy_reg_param(&reg_params[0]);
617 destroy_reg_param(&reg_params[1]);
618 target_free_working_area(target, crc_algorithm);
619 return retval;
620 }
621
622 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
623
624 destroy_reg_param(&reg_params[0]);
625 destroy_reg_param(&reg_params[1]);
626
627 target_free_working_area(target, crc_algorithm);
628
629 return ERROR_OK;
630 }
631
632 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
633 {
634 working_area_t *erase_check_algorithm;
635 reg_param_t reg_params[3];
636 armv7m_algorithm_t armv7m_info;
637 int retval;
638 int i;
639
640 u16 erase_check_code[] =
641 {
642 /* loop: */
643 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
644 0xEA02, 0x0203, /* and r2, r2, r3 */
645 0x3901, /* subs r1, r1, #1 */
646 0xD1F9, /* bne loop */
647 /* end: */
648 0xE7FE, /* b end */
649 };
650
651 /* make sure we have a working area */
652 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
653 {
654 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
655 }
656
657 /* convert flash writing code into a buffer in target endianness */
658 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
659 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
660
661 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
662 armv7m_info.core_mode = ARMV7M_MODE_ANY;
663
664 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
665 buf_set_u32(reg_params[0].value, 0, 32, address);
666
667 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
668 buf_set_u32(reg_params[1].value, 0, 32, count);
669
670 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
671 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
672
673 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
674 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
675 {
676 destroy_reg_param(&reg_params[0]);
677 destroy_reg_param(&reg_params[1]);
678 destroy_reg_param(&reg_params[2]);
679 target_free_working_area(target, erase_check_algorithm);
680 return 0;
681 }
682
683 *blank = buf_get_u32(reg_params[2].value, 0, 32);
684
685 destroy_reg_param(&reg_params[0]);
686 destroy_reg_param(&reg_params[1]);
687 destroy_reg_param(&reg_params[2]);
688
689 target_free_working_area(target, erase_check_algorithm);
690
691 return ERROR_OK;
692 }
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