1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
31 /* ETM register access functionality
36 static bitfield_desc_t etm_comms_ctrl_bitfield_desc
[] =
45 static int etm_reg_arch_info
[] =
47 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
48 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
49 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
50 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
51 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
52 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
53 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
54 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
55 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
56 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
57 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
58 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
59 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
60 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
63 static int etm_reg_arch_size_info
[] =
65 32, 32, 17, 8, 3, 9, 32, 16,
66 17, 26, 25, 8, 17, 32, 32, 17,
67 32, 32, 32, 32, 32, 32, 32, 32,
68 32, 32, 32, 32, 32, 32, 32, 32,
69 7, 7, 7, 7, 7, 7, 7, 7,
70 7, 7, 7, 7, 7, 7, 7, 7,
71 32, 32, 32, 32, 32, 32, 32, 32,
72 32, 32, 32, 32, 32, 32, 32, 32,
73 32, 32, 32, 32, 32, 32, 32, 32,
74 32, 32, 32, 32, 32, 32, 32, 32,
75 16, 16, 16, 16, 18, 18, 18, 18,
76 17, 17, 17, 17, 16, 16, 16, 16,
77 17, 17, 17, 17, 17, 17, 2,
78 17, 17, 17, 17, 32, 32, 32, 32
81 static char* etm_reg_list
[] =
89 "ETM_TRACE_RESOURCE_CTRL",
93 "ETM_FIFOFULL_REGION",
99 "ETM_ADDR_COMPARATOR_VALUE1",
100 "ETM_ADDR_COMPARATOR_VALUE2",
101 "ETM_ADDR_COMPARATOR_VALUE3",
102 "ETM_ADDR_COMPARATOR_VALUE4",
103 "ETM_ADDR_COMPARATOR_VALUE5",
104 "ETM_ADDR_COMPARATOR_VALUE6",
105 "ETM_ADDR_COMPARATOR_VALUE7",
106 "ETM_ADDR_COMPARATOR_VALUE8",
107 "ETM_ADDR_COMPARATOR_VALUE9",
108 "ETM_ADDR_COMPARATOR_VALUE10",
109 "ETM_ADDR_COMPARATOR_VALUE11",
110 "ETM_ADDR_COMPARATOR_VALUE12",
111 "ETM_ADDR_COMPARATOR_VALUE13",
112 "ETM_ADDR_COMPARATOR_VALUE14",
113 "ETM_ADDR_COMPARATOR_VALUE15",
114 "ETM_ADDR_COMPARATOR_VALUE16",
115 "ETM_ADDR_ACCESS_TYPE1",
116 "ETM_ADDR_ACCESS_TYPE2",
117 "ETM_ADDR_ACCESS_TYPE3",
118 "ETM_ADDR_ACCESS_TYPE4",
119 "ETM_ADDR_ACCESS_TYPE5",
120 "ETM_ADDR_ACCESS_TYPE6",
121 "ETM_ADDR_ACCESS_TYPE7",
122 "ETM_ADDR_ACCESS_TYPE8",
123 "ETM_ADDR_ACCESS_TYPE9",
124 "ETM_ADDR_ACCESS_TYPE10",
125 "ETM_ADDR_ACCESS_TYPE11",
126 "ETM_ADDR_ACCESS_TYPE12",
127 "ETM_ADDR_ACCESS_TYPE13",
128 "ETM_ADDR_ACCESS_TYPE14",
129 "ETM_ADDR_ACCESS_TYPE15",
130 "ETM_ADDR_ACCESS_TYPE16",
131 "ETM_DATA_COMPARATOR_VALUE1",
132 "ETM_DATA_COMPARATOR_VALUE2",
133 "ETM_DATA_COMPARATOR_VALUE3",
134 "ETM_DATA_COMPARATOR_VALUE4",
135 "ETM_DATA_COMPARATOR_VALUE5",
136 "ETM_DATA_COMPARATOR_VALUE6",
137 "ETM_DATA_COMPARATOR_VALUE7",
138 "ETM_DATA_COMPARATOR_VALUE8",
139 "ETM_DATA_COMPARATOR_VALUE9",
140 "ETM_DATA_COMPARATOR_VALUE10",
141 "ETM_DATA_COMPARATOR_VALUE11",
142 "ETM_DATA_COMPARATOR_VALUE12",
143 "ETM_DATA_COMPARATOR_VALUE13",
144 "ETM_DATA_COMPARATOR_VALUE14",
145 "ETM_DATA_COMPARATOR_VALUE15",
146 "ETM_DATA_COMPARATOR_VALUE16",
147 "ETM_DATA_COMPARATOR_MASK1",
148 "ETM_DATA_COMPARATOR_MASK2",
149 "ETM_DATA_COMPARATOR_MASK3",
150 "ETM_DATA_COMPARATOR_MASK4",
151 "ETM_DATA_COMPARATOR_MASK5",
152 "ETM_DATA_COMPARATOR_MASK6",
153 "ETM_DATA_COMPARATOR_MASK7",
154 "ETM_DATA_COMPARATOR_MASK8",
155 "ETM_DATA_COMPARATOR_MASK9",
156 "ETM_DATA_COMPARATOR_MASK10",
157 "ETM_DATA_COMPARATOR_MASK11",
158 "ETM_DATA_COMPARATOR_MASK12",
159 "ETM_DATA_COMPARATOR_MASK13",
160 "ETM_DATA_COMPARATOR_MASK14",
161 "ETM_DATA_COMPARATOR_MASK15",
162 "ETM_DATA_COMPARATOR_MASK16",
163 "ETM_COUNTER_INITAL_VALUE1",
164 "ETM_COUNTER_INITAL_VALUE2",
165 "ETM_COUNTER_INITAL_VALUE3",
166 "ETM_COUNTER_INITAL_VALUE4",
167 "ETM_COUNTER_ENABLE1",
168 "ETM_COUNTER_ENABLE2",
169 "ETM_COUNTER_ENABLE3",
170 "ETM_COUNTER_ENABLE4",
171 "ETM_COUNTER_RELOAD_VALUE1",
172 "ETM_COUNTER_RELOAD_VALUE2",
173 "ETM_COUNTER_RELOAD_VALUE3",
174 "ETM_COUNTER_RELOAD_VALUE4",
175 "ETM_COUNTER_VALUE1",
176 "ETM_COUNTER_VALUE2",
177 "ETM_COUNTER_VALUE3",
178 "ETM_COUNTER_VALUE4",
179 "ETM_SEQUENCER_CTRL1",
180 "ETM_SEQUENCER_CTRL2",
181 "ETM_SEQUENCER_CTRL3",
182 "ETM_SEQUENCER_CTRL4",
183 "ETM_SEQUENCER_CTRL5",
184 "ETM_SEQUENCER_CTRL6",
185 "ETM_SEQUENCER_STATE",
186 "ETM_EXTERNAL_OUTPUT1",
187 "ETM_EXTERNAL_OUTPUT2",
188 "ETM_EXTERNAL_OUTPUT3",
189 "ETM_EXTERNAL_OUTPUT4",
190 "ETM_CONTEXTID_COMPARATOR_VALUE1",
191 "ETM_CONTEXTID_COMPARATOR_VALUE2",
192 "ETM_CONTEXTID_COMPARATOR_VALUE3",
193 "ETM_CONTEXTID_COMPARATOR_MASK"
196 static int etm_reg_arch_type
= -1;
198 static int etm_get_reg(reg_t
*reg
);
200 static command_t
*etm_cmd
= NULL
;
202 reg_cache_t
* etm_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
204 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
205 reg_t
*reg_list
= NULL
;
206 etm_reg_t
*arch_info
= NULL
;
207 int num_regs
= sizeof(etm_reg_arch_info
)/sizeof(int);
210 /* register a register arch-type for etm registers only once */
211 if (etm_reg_arch_type
== -1)
212 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
, etm_set_reg_w_exec
);
214 /* the actual registers are kept in two arrays */
215 reg_list
= calloc(num_regs
, sizeof(reg_t
));
216 arch_info
= calloc(num_regs
, sizeof(etm_reg_t
));
218 /* fill in values for the reg cache */
219 reg_cache
->name
= "etm registers";
220 reg_cache
->next
= NULL
;
221 reg_cache
->reg_list
= reg_list
;
222 reg_cache
->num_regs
= num_regs
;
224 /* set up registers */
225 for (i
= 0; i
< num_regs
; i
++)
227 reg_list
[i
].name
= etm_reg_list
[i
];
228 reg_list
[i
].size
= 32;
229 reg_list
[i
].dirty
= 0;
230 reg_list
[i
].valid
= 0;
231 reg_list
[i
].bitfield_desc
= NULL
;
232 reg_list
[i
].num_bitfields
= 0;
233 reg_list
[i
].value
= calloc(1, 4);
234 reg_list
[i
].arch_info
= &arch_info
[i
];
235 reg_list
[i
].arch_type
= etm_reg_arch_type
;
236 reg_list
[i
].size
= etm_reg_arch_size_info
[i
];
237 arch_info
[i
].addr
= etm_reg_arch_info
[i
];
238 arch_info
[i
].jtag_info
= jtag_info
;
241 /* the ETM might have an ETB connected */
242 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
244 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
248 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
252 reg_cache
->next
= etb_build_reg_cache(etb
);
254 etb
->reg_cache
= reg_cache
->next
;
261 int etm_setup(target_t
*target
)
264 uint32_t etm_ctrl_value
;
265 armv4_5_common_t
*armv4_5
= target
->arch_info
;
266 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
267 etm_context_t
*etm_ctx
= arm7_9
->etm_ctx
;
268 reg_t
*etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
270 /* initialize some ETM control register settings */
271 etm_get_reg(etm_ctrl_reg
);
272 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
274 /* clear the ETM powerdown bit (0) */
275 etm_ctrl_value
&= ~0x1;
277 /* configure port width (6:4), mode (17:16) and clocking (13) */
278 etm_ctrl_value
= (etm_ctrl_value
&
279 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
282 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
283 etm_store_reg(etm_ctrl_reg
);
285 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
288 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
290 LOG_ERROR("ETM capture driver initialization failed");
296 int etm_get_reg(reg_t
*reg
)
300 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
302 LOG_ERROR("BUG: error scheduling etm register read");
306 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
308 LOG_ERROR("register read failed");
315 int etm_read_reg_w_check(reg_t
*reg
, uint8_t* check_value
, uint8_t* check_mask
)
317 etm_reg_t
*etm_reg
= reg
->arch_info
;
318 uint8_t reg_addr
= etm_reg
->addr
& 0x7f;
319 scan_field_t fields
[3];
321 LOG_DEBUG("%i", etm_reg
->addr
);
323 jtag_set_end_state(TAP_IDLE
);
324 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
325 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
327 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
328 fields
[0].num_bits
= 32;
329 fields
[0].out_value
= reg
->value
;
330 fields
[0].in_value
= NULL
;
331 fields
[0].check_value
= NULL
;
332 fields
[0].check_mask
= NULL
;
334 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
335 fields
[1].num_bits
= 7;
336 fields
[1].out_value
= malloc(1);
337 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
338 fields
[1].in_value
= NULL
;
339 fields
[1].check_value
= NULL
;
340 fields
[1].check_mask
= NULL
;
342 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
343 fields
[2].num_bits
= 1;
344 fields
[2].out_value
= malloc(1);
345 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
346 fields
[2].in_value
= NULL
;
347 fields
[2].check_value
= NULL
;
348 fields
[2].check_mask
= NULL
;
350 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
352 fields
[0].in_value
= reg
->value
;
353 fields
[0].check_value
= check_value
;
354 fields
[0].check_mask
= check_mask
;
356 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
358 free(fields
[1].out_value
);
359 free(fields
[2].out_value
);
364 int etm_read_reg(reg_t
*reg
)
366 return etm_read_reg_w_check(reg
, NULL
, NULL
);
369 int etm_set_reg(reg_t
*reg
, uint32_t value
)
373 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
375 LOG_ERROR("BUG: error scheduling etm register write");
379 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
386 int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
390 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
392 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
394 LOG_ERROR("register write failed");
400 int etm_write_reg(reg_t
*reg
, uint32_t value
)
402 etm_reg_t
*etm_reg
= reg
->arch_info
;
403 uint8_t reg_addr
= etm_reg
->addr
& 0x7f;
404 scan_field_t fields
[3];
406 LOG_DEBUG("%i: 0x%8.8" PRIx32
"", etm_reg
->addr
, value
);
408 jtag_set_end_state(TAP_IDLE
);
409 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
410 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
412 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
413 fields
[0].num_bits
= 32;
415 fields
[0].out_value
= tmp1
;
416 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
417 fields
[0].in_value
= NULL
;
419 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
420 fields
[1].num_bits
= 7;
422 fields
[1].out_value
= &tmp2
;
423 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
424 fields
[1].in_value
= NULL
;
426 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
427 fields
[2].num_bits
= 1;
429 fields
[2].out_value
= &tmp3
;
430 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
431 fields
[2].in_value
= NULL
;
433 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
438 int etm_store_reg(reg_t
*reg
)
440 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
443 /* ETM trace analysis functionality
446 extern etm_capture_driver_t etm_dummy_capture_driver
;
447 #if BUILD_OOCD_TRACE == 1
448 extern etm_capture_driver_t oocd_trace_capture_driver
;
451 static etm_capture_driver_t
*etm_capture_drivers
[] =
454 &etm_dummy_capture_driver
,
455 #if BUILD_OOCD_TRACE == 1
456 &oocd_trace_capture_driver
,
461 char *etmv1v1_branch_reason_strings
[] =
465 "trace restarted after overflow",
467 "periodic synchronization",
473 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
482 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
484 /* search for the section the current instruction belongs to */
485 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
487 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
488 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
497 /* current instruction couldn't be found in the image */
498 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
501 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
504 if ((retval
= image_read_section(ctx
->image
, section
,
505 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
506 4, buf
, &size_read
)) != ERROR_OK
)
508 LOG_ERROR("error while reading instruction: %i", retval
);
509 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
511 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
512 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
514 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
517 if ((retval
= image_read_section(ctx
->image
, section
,
518 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
519 2, buf
, &size_read
)) != ERROR_OK
)
521 LOG_ERROR("error while reading instruction: %i", retval
);
522 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
524 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
525 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
527 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
529 LOG_ERROR("BUG: tracing of jazelle code not supported");
534 LOG_ERROR("BUG: unknown core state encountered");
541 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
543 while (ctx
->data_index
< ctx
->trace_depth
)
545 /* if the caller specified an address packet offset, skip until the
546 * we reach the n-th cycle marked with tracesync */
549 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
560 /* no tracedata output during a TD cycle
561 * or in a trigger cycle */
562 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
563 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
570 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
572 if (ctx
->data_half
== 0)
574 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
579 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
584 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
586 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
591 /* on a 4-bit port, a packet will be output during two consecutive cycles */
592 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
595 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
596 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
597 ctx
->data_index
+= 2;
606 static int etmv1_branch_address(etm_context_t
*ctx
)
614 /* quit analysis if less than two cycles are left in the trace
615 * because we can't extract the APO */
616 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
619 /* a BE could be output during an APO cycle, skip the current
620 * and continue with the new one */
621 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
623 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
626 /* address packet offset encoded in the next two cycles' pipestat bits */
627 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
628 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
630 /* count number of tracesync cycles between current pipe_index and data_index
631 * i.e. the number of tracesyncs that data_index already passed by
632 * to subtract them from the APO */
633 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
635 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
639 /* extract up to four 7-bit packets */
641 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
643 ctx
->last_branch
&= ~(0x7f << shift
);
644 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
646 } while ((packet
& 0x80) && (shift
< 28));
648 /* one last packet holding 4 bits of the address, plus the branch reason code */
649 if ((shift
== 28) && (packet
& 0x80))
651 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
653 ctx
->last_branch
&= 0x0fffffff;
654 ctx
->last_branch
|= (packet
& 0x0f) << 28;
655 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
660 ctx
->last_branch_reason
= 0;
668 /* if a full address was output, we might have branched into Jazelle state */
669 if ((shift
== 32) && (packet
& 0x80))
671 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
675 /* if we didn't branch into Jazelle state, the current processor state is
676 * encoded in bit 0 of the branch target address */
677 if (ctx
->last_branch
& 0x1)
679 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
680 ctx
->last_branch
&= ~0x1;
684 ctx
->core_state
= ARMV4_5_STATE_ARM
;
685 ctx
->last_branch
&= ~0x3;
692 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
698 for (j
= 0; j
< size
; j
++)
700 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
706 LOG_ERROR("TODO: add support for 64-bit values");
710 *data
= target_buffer_get_u32(ctx
->target
, buf
);
712 *data
= target_buffer_get_u16(ctx
->target
, buf
);
721 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
724 arm_instruction_t instruction
;
726 /* read the trace data if it wasn't read already */
727 if (ctx
->trace_depth
== 0)
728 ctx
->capture_driver
->read_trace(ctx
);
730 /* start at the beginning of the captured trace */
735 /* neither the PC nor the data pointer are valid */
739 while (ctx
->pipe_index
< ctx
->trace_depth
)
741 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
742 uint32_t next_pc
= ctx
->current_pc
;
743 uint32_t old_data_index
= ctx
->data_index
;
744 uint32_t old_data_half
= ctx
->data_half
;
745 uint32_t old_index
= ctx
->pipe_index
;
746 uint32_t last_instruction
= ctx
->last_instruction
;
748 int current_pc_ok
= ctx
->pc_ok
;
750 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
752 command_print(cmd_ctx
, "--- trigger ---");
755 /* instructions execute in IE/D or BE/D cycles */
756 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
757 ctx
->last_instruction
= ctx
->pipe_index
;
759 /* if we don't have a valid pc skip until we reach an indirect branch */
760 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
766 /* any indirect branch could have interrupted instruction flow
767 * - the branch reason code could indicate a trace discontinuity
768 * - a branch to the exception vectors indicates an exception
770 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
772 /* backup current data index, to be able to consume the branch address
773 * before examining data address and values
775 old_data_index
= ctx
->data_index
;
776 old_data_half
= ctx
->data_half
;
778 ctx
->last_instruction
= ctx
->pipe_index
;
780 if ((retval
= etmv1_branch_address(ctx
)) != 0)
782 /* negative return value from etmv1_branch_address means we ran out of packets,
783 * quit analysing the trace */
787 /* a positive return values means the current branch was abandoned,
788 * and a new branch was encountered in cycle ctx->pipe_index + retval;
790 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
791 ctx
->pipe_index
+= retval
;
795 /* skip over APO cycles */
796 ctx
->pipe_index
+= 2;
798 switch (ctx
->last_branch_reason
)
800 case 0x0: /* normal PC change */
801 next_pc
= ctx
->last_branch
;
803 case 0x1: /* tracing enabled */
804 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
805 ctx
->current_pc
= ctx
->last_branch
;
809 case 0x2: /* trace restarted after FIFO overflow */
810 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
811 ctx
->current_pc
= ctx
->last_branch
;
815 case 0x3: /* exit from debug state */
816 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
817 ctx
->current_pc
= ctx
->last_branch
;
821 case 0x4: /* periodic synchronization point */
822 next_pc
= ctx
->last_branch
;
823 /* if we had no valid PC prior to this synchronization point,
824 * we have to move on with the next trace cycle
828 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
829 ctx
->current_pc
= next_pc
;
834 default: /* reserved */
835 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
840 /* if we got here the branch was a normal PC change
841 * (or a periodic synchronization point, which means the same for that matter)
842 * if we didn't accquire a complete PC continue with the next cycle
847 /* indirect branch to the exception vector means an exception occured */
848 if ((ctx
->last_branch
<= 0x20)
849 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
851 if ((ctx
->last_branch
& 0xff) == 0x10)
853 command_print(cmd_ctx
, "data abort");
857 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
858 ctx
->current_pc
= ctx
->last_branch
;
865 /* an instruction was executed (or not, depending on the condition flags)
866 * retrieve it from the image for displaying */
867 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
868 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
869 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
871 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
873 /* can't continue tracing with no image available */
874 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
878 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
880 /* TODO: handle incomplete images
881 * for now we just quit the analsysis*/
886 cycles
= old_index
- last_instruction
;
889 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
891 uint32_t new_data_index
= ctx
->data_index
;
892 uint32_t new_data_half
= ctx
->data_half
;
894 /* in case of a branch with data, the branch target address was consumed before
895 * we temporarily go back to the saved data index */
896 if (pipestat
== STAT_BD
)
898 ctx
->data_index
= old_data_index
;
899 ctx
->data_half
= old_data_half
;
902 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
908 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
909 return ERROR_ETM_ANALYSIS_FAILED
;
910 ctx
->last_ptr
&= ~(0x7f << shift
);
911 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
913 } while ((packet
& 0x80) && (shift
< 32));
920 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
924 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
926 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
929 for (i
= 0; i
< 16; i
++)
931 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
934 if (etmv1_data(ctx
, 4, &data
) != 0)
935 return ERROR_ETM_ANALYSIS_FAILED
;
936 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
940 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
943 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
944 return ERROR_ETM_ANALYSIS_FAILED
;
945 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
949 /* restore data index after consuming BD address and data */
950 if (pipestat
== STAT_BD
)
952 ctx
->data_index
= new_data_index
;
953 ctx
->data_half
= new_data_half
;
958 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
960 if (((instruction
.type
== ARM_B
) ||
961 (instruction
.type
== ARM_BL
) ||
962 (instruction
.type
== ARM_BLX
)) &&
963 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
965 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
969 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
972 else if (pipestat
== STAT_IN
)
974 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
977 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
979 char cycles_text
[32] = "";
981 /* if the trace was captured with cycle accurate tracing enabled,
982 * output the number of cycles since the last executed instruction
984 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
986 snprintf(cycles_text
, 32, " (%i %s)",
988 (cycles
== 1) ? "cycle" : "cycles");
991 command_print(cmd_ctx
, "%s%s%s",
993 (pipestat
== STAT_IN
) ? " (not executed)" : "",
996 ctx
->current_pc
= next_pc
;
998 /* packets for an instruction don't start on or before the preceding
999 * functional pipestat (i.e. other than WT or TD)
1001 if (ctx
->data_index
<= ctx
->pipe_index
)
1003 ctx
->data_index
= ctx
->pipe_index
+ 1;
1008 ctx
->pipe_index
+= 1;
1014 static int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1017 armv4_5_common_t
*armv4_5
;
1018 arm7_9_common_t
*arm7_9
;
1019 etmv1_tracemode_t tracemode
;
1021 target
= get_current_target(cmd_ctx
);
1023 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1025 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1029 if (!arm7_9
->etm_ctx
)
1031 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1035 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1039 if (strcmp(args
[0], "none") == 0)
1041 tracemode
= ETMV1_TRACE_NONE
;
1043 else if (strcmp(args
[0], "data") == 0)
1045 tracemode
= ETMV1_TRACE_DATA
;
1047 else if (strcmp(args
[0], "address") == 0)
1049 tracemode
= ETMV1_TRACE_ADDR
;
1051 else if (strcmp(args
[0], "all") == 0)
1053 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1057 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1061 switch (strtol(args
[1], NULL
, 0))
1064 tracemode
|= ETMV1_CONTEXTID_NONE
;
1067 tracemode
|= ETMV1_CONTEXTID_8
;
1070 tracemode
|= ETMV1_CONTEXTID_16
;
1073 tracemode
|= ETMV1_CONTEXTID_32
;
1076 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1080 if (strcmp(args
[2], "enable") == 0)
1082 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1084 else if (strcmp(args
[2], "disable") == 0)
1090 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1094 if (strcmp(args
[3], "enable") == 0)
1096 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1098 else if (strcmp(args
[3], "disable") == 0)
1104 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1110 command_print(cmd_ctx
, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1114 command_print(cmd_ctx
, "current tracemode configuration:");
1116 switch (tracemode
& ETMV1_TRACE_MASK
)
1118 case ETMV1_TRACE_NONE
:
1119 command_print(cmd_ctx
, "data tracing: none");
1121 case ETMV1_TRACE_DATA
:
1122 command_print(cmd_ctx
, "data tracing: data only");
1124 case ETMV1_TRACE_ADDR
:
1125 command_print(cmd_ctx
, "data tracing: address only");
1127 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1128 command_print(cmd_ctx
, "data tracing: address and data");
1132 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1134 case ETMV1_CONTEXTID_NONE
:
1135 command_print(cmd_ctx
, "contextid tracing: none");
1137 case ETMV1_CONTEXTID_8
:
1138 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1140 case ETMV1_CONTEXTID_16
:
1141 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1143 case ETMV1_CONTEXTID_32
:
1144 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1148 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1150 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1154 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1157 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1159 command_print(cmd_ctx
, "full branch address output enabled");
1163 command_print(cmd_ctx
, "full branch address output disabled");
1166 /* only update ETM_CTRL register if tracemode changed */
1167 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1169 reg_t
*etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1171 etm_get_reg(etm_ctrl_reg
);
1173 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1174 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1175 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1176 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1177 etm_store_reg(etm_ctrl_reg
);
1179 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1181 /* invalidate old trace data */
1182 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1183 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1185 free(arm7_9
->etm_ctx
->trace_data
);
1186 arm7_9
->etm_ctx
->trace_data
= NULL
;
1188 arm7_9
->etm_ctx
->trace_depth
= 0;
1194 static int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1197 armv4_5_common_t
*armv4_5
;
1198 arm7_9_common_t
*arm7_9
;
1199 etm_portmode_t portmode
= 0x0;
1200 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1205 return ERROR_COMMAND_SYNTAX_ERROR
;
1208 target
= get_target(args
[0]);
1211 LOG_ERROR("target '%s' not defined", args
[0]);
1215 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1217 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1221 switch (strtoul(args
[1], NULL
, 0))
1224 portmode
|= ETM_PORT_4BIT
;
1227 portmode
|= ETM_PORT_8BIT
;
1230 portmode
|= ETM_PORT_16BIT
;
1233 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1237 if (strcmp("normal", args
[2]) == 0)
1239 portmode
|= ETM_PORT_NORMAL
;
1241 else if (strcmp("multiplexed", args
[2]) == 0)
1243 portmode
|= ETM_PORT_MUXED
;
1245 else if (strcmp("demultiplexed", args
[2]) == 0)
1247 portmode
|= ETM_PORT_DEMUXED
;
1251 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1255 if (strcmp("half", args
[3]) == 0)
1257 portmode
|= ETM_PORT_HALF_CLOCK
;
1259 else if (strcmp("full", args
[3]) == 0)
1261 portmode
|= ETM_PORT_FULL_CLOCK
;
1265 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1269 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1271 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1274 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1280 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1286 if (!etm_capture_drivers
[i
])
1288 /* no supported capture driver found, don't register an ETM */
1290 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1294 etm_ctx
->target
= target
;
1295 etm_ctx
->trigger_percent
= 50;
1296 etm_ctx
->trace_data
= NULL
;
1297 etm_ctx
->trace_depth
= 0;
1298 etm_ctx
->portmode
= portmode
;
1299 etm_ctx
->tracemode
= 0x0;
1300 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1301 etm_ctx
->image
= NULL
;
1302 etm_ctx
->pipe_index
= 0;
1303 etm_ctx
->data_index
= 0;
1304 etm_ctx
->current_pc
= 0x0;
1306 etm_ctx
->last_branch
= 0x0;
1307 etm_ctx
->last_branch_reason
= 0x0;
1308 etm_ctx
->last_ptr
= 0x0;
1309 etm_ctx
->ptr_ok
= 0x0;
1310 etm_ctx
->context_id
= 0x0;
1311 etm_ctx
->last_instruction
= 0;
1313 arm7_9
->etm_ctx
= etm_ctx
;
1315 return etm_register_user_commands(cmd_ctx
);
1318 int handle_etm_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1321 armv4_5_common_t
*armv4_5
;
1322 arm7_9_common_t
*arm7_9
;
1323 reg_t
*etm_config_reg
;
1324 reg_t
*etm_sys_config_reg
;
1328 target
= get_current_target(cmd_ctx
);
1330 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1332 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1336 if (!arm7_9
->etm_ctx
)
1338 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1342 etm_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CONFIG
];
1343 etm_sys_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_SYS_CONFIG
];
1345 etm_get_reg(etm_config_reg
);
1346 command_print(cmd_ctx
, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg
->value
, 0, 4));
1347 command_print(cmd_ctx
, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg
->value
, 4, 4));
1348 command_print(cmd_ctx
, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg
->value
, 8, 5));
1349 command_print(cmd_ctx
, "number of counters: %i", (int)buf_get_u32(etm_config_reg
->value
, 13, 3));
1350 command_print(cmd_ctx
, "sequencer %spresent",
1351 (buf_get_u32(etm_config_reg
->value
, 16, 1) == 1) ? "" : "not ");
1352 command_print(cmd_ctx
, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg
->value
, 17, 3));
1353 command_print(cmd_ctx
, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg
->value
, 20, 3));
1354 command_print(cmd_ctx
, "FIFO full %spresent",
1355 (buf_get_u32(etm_config_reg
->value
, 23, 1) == 1) ? "" : "not ");
1356 command_print(cmd_ctx
, "protocol version: %i", (int)buf_get_u32(etm_config_reg
->value
, 28, 3));
1358 etm_get_reg(etm_sys_config_reg
);
1360 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1372 LOG_ERROR("Illegal max_port_size");
1375 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1377 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1378 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1379 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1380 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1381 command_print(cmd_ctx
, "normal trace format %ssupported",
1382 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1383 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1384 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1385 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1386 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1387 command_print(cmd_ctx
, "FIFO full %ssupported",
1388 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1393 static int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1396 armv4_5_common_t
*armv4_5
;
1397 arm7_9_common_t
*arm7_9
;
1398 trace_status_t trace_status
;
1400 target
= get_current_target(cmd_ctx
);
1402 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1404 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1408 if (!arm7_9
->etm_ctx
)
1410 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1414 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1416 if (trace_status
== TRACE_IDLE
)
1418 command_print(cmd_ctx
, "tracing is idle");
1422 static char *completed
= " completed";
1423 static char *running
= " is running";
1424 static char *overflowed
= ", trace overflowed";
1425 static char *triggered
= ", trace triggered";
1427 command_print(cmd_ctx
, "trace collection%s%s%s",
1428 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1429 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1430 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1432 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1434 command_print(cmd_ctx
, "%i frames of trace data read", (int)(arm7_9
->etm_ctx
->trace_depth
));
1441 static int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1444 armv4_5_common_t
*armv4_5
;
1445 arm7_9_common_t
*arm7_9
;
1446 etm_context_t
*etm_ctx
;
1450 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1454 target
= get_current_target(cmd_ctx
);
1456 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1458 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1462 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1464 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1470 image_close(etm_ctx
->image
);
1471 free(etm_ctx
->image
);
1472 command_print(cmd_ctx
, "previously loaded image found and closed");
1475 etm_ctx
->image
= malloc(sizeof(image_t
));
1476 etm_ctx
->image
->base_address_set
= 0;
1477 etm_ctx
->image
->start_address_set
= 0;
1479 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1482 etm_ctx
->image
->base_address_set
= 1;
1483 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1487 etm_ctx
->image
->base_address_set
= 0;
1490 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1492 free(etm_ctx
->image
);
1493 etm_ctx
->image
= NULL
;
1500 static int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1504 armv4_5_common_t
*armv4_5
;
1505 arm7_9_common_t
*arm7_9
;
1506 etm_context_t
*etm_ctx
;
1511 command_print(cmd_ctx
, "usage: etm dump <file>");
1515 target
= get_current_target(cmd_ctx
);
1517 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1519 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1523 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1525 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1529 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1531 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1535 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1537 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1538 command_print(cmd_ctx
, "trace capture not completed");
1542 /* read the trace data if it wasn't read already */
1543 if (etm_ctx
->trace_depth
== 0)
1544 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1546 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1551 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1552 fileio_write_u32(&file
, etm_ctx
->portmode
);
1553 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1554 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1556 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1558 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1559 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1560 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1563 fileio_close(&file
);
1568 static int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1572 armv4_5_common_t
*armv4_5
;
1573 arm7_9_common_t
*arm7_9
;
1574 etm_context_t
*etm_ctx
;
1579 command_print(cmd_ctx
, "usage: etm load <file>");
1583 target
= get_current_target(cmd_ctx
);
1585 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1587 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1591 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1593 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1597 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1599 command_print(cmd_ctx
, "trace capture running, stop first");
1603 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1610 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1611 fileio_close(&file
);
1615 if (etm_ctx
->trace_depth
> 0)
1617 free(etm_ctx
->trace_data
);
1618 etm_ctx
->trace_data
= NULL
;
1623 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1624 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1625 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1626 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1628 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1629 if (etm_ctx
->trace_data
== NULL
)
1631 command_print(cmd_ctx
, "not enough memory to perform operation");
1632 fileio_close(&file
);
1636 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1638 uint32_t pipestat
, packet
, flags
;
1639 fileio_read_u32(&file
, &pipestat
);
1640 fileio_read_u32(&file
, &packet
);
1641 fileio_read_u32(&file
, &flags
);
1642 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1643 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1644 etm_ctx
->trace_data
[i
].flags
= flags
;
1647 fileio_close(&file
);
1652 static int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1655 armv4_5_common_t
*armv4_5
;
1656 arm7_9_common_t
*arm7_9
;
1657 etm_context_t
*etm_ctx
;
1659 target
= get_current_target(cmd_ctx
);
1661 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1663 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1667 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1669 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1675 uint32_t new_value
= strtoul(args
[0], NULL
, 0);
1677 if ((new_value
< 2) || (new_value
> 100))
1679 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1683 etm_ctx
->trigger_percent
= new_value
;
1687 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1692 static int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1695 armv4_5_common_t
*armv4_5
;
1696 arm7_9_common_t
*arm7_9
;
1697 etm_context_t
*etm_ctx
;
1698 reg_t
*etm_ctrl_reg
;
1700 target
= get_current_target(cmd_ctx
);
1702 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1704 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1708 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1710 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1714 /* invalidate old tracing data */
1715 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1716 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1718 free(arm7_9
->etm_ctx
->trace_data
);
1719 arm7_9
->etm_ctx
->trace_data
= NULL
;
1721 arm7_9
->etm_ctx
->trace_depth
= 0;
1723 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1724 etm_get_reg(etm_ctrl_reg
);
1726 /* Clear programming bit (10), set port selection bit (11) */
1727 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1729 etm_store_reg(etm_ctrl_reg
);
1730 jtag_execute_queue();
1732 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1737 static int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1740 armv4_5_common_t
*armv4_5
;
1741 arm7_9_common_t
*arm7_9
;
1742 etm_context_t
*etm_ctx
;
1743 reg_t
*etm_ctrl_reg
;
1745 target
= get_current_target(cmd_ctx
);
1747 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1749 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1753 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1755 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1759 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1760 etm_get_reg(etm_ctrl_reg
);
1762 /* Set programming bit (10), clear port selection bit (11) */
1763 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1765 etm_store_reg(etm_ctrl_reg
);
1766 jtag_execute_queue();
1768 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1773 static int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1776 armv4_5_common_t
*armv4_5
;
1777 arm7_9_common_t
*arm7_9
;
1778 etm_context_t
*etm_ctx
;
1781 target
= get_current_target(cmd_ctx
);
1783 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1785 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1789 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1791 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1795 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
1799 case ERROR_ETM_ANALYSIS_FAILED
:
1800 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
1802 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1803 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
1805 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
1806 command_print(cmd_ctx
, "no image available for trace analysis");
1809 command_print(cmd_ctx
, "unknown error: %i", retval
);
1816 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1818 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1820 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
1821 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1826 int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
1828 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
1829 COMMAND_EXEC
, "configure trace mode <none | data | address | all> "
1830 "<context_id_bits> <cycle_accurate> <branch_output>");
1832 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
1833 COMMAND_EXEC
, "display info about the current target's ETM");
1835 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
1836 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1837 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
1838 COMMAND_EXEC
, "display current target's ETM status");
1839 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
1840 COMMAND_EXEC
, "start ETM trace collection");
1841 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
1842 COMMAND_EXEC
, "stop ETM trace collection");
1844 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
1845 COMMAND_EXEC
, "anaylze collected ETM trace");
1847 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
1848 COMMAND_EXEC
, "load image from <file> [base address]");
1850 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
1851 COMMAND_EXEC
, "dump captured trace data <file>");
1852 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
1853 COMMAND_EXEC
, "load trace data for analysis <file>");